1 #ifndef MDP5_XML
2 #define MDP5_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12 - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29 - /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30
31 Copyright (C) 2013-2021 by the following authors:
32 - Rob Clark <robdclark@gmail.com> (robclark)
33 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
34
35 Permission is hereby granted, free of charge, to any person obtaining
36 a copy of this software and associated documentation files (the
37 "Software"), to deal in the Software without restriction, including
38 without limitation the rights to use, copy, modify, merge, publish,
39 distribute, sublicense, and/or sell copies of the Software, and to
40 permit persons to whom the Software is furnished to do so, subject to
41 the following conditions:
42
43 The above copyright notice and this permission notice (including the
44 next paragraph) shall be included in all copies or substantial
45 portions of the Software.
46
47 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
48 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
49 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
50 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
51 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
52 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
53 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
54 */
55
56
57 enum mdp5_intf_type {
58 INTF_DISABLED = 0,
59 INTF_DSI = 1,
60 INTF_HDMI = 3,
61 INTF_LCDC = 5,
62 INTF_eDP = 9,
63 INTF_VIRTUAL = 100,
64 INTF_WB = 101,
65 };
66
67 enum mdp5_intfnum {
68 NO_INTF = 0,
69 INTF0 = 1,
70 INTF1 = 2,
71 INTF2 = 3,
72 INTF3 = 4,
73 };
74
75 enum mdp5_pipe {
76 SSPP_NONE = 0,
77 SSPP_VIG0 = 1,
78 SSPP_VIG1 = 2,
79 SSPP_VIG2 = 3,
80 SSPP_RGB0 = 4,
81 SSPP_RGB1 = 5,
82 SSPP_RGB2 = 6,
83 SSPP_DMA0 = 7,
84 SSPP_DMA1 = 8,
85 SSPP_VIG3 = 9,
86 SSPP_RGB3 = 10,
87 SSPP_CURSOR0 = 11,
88 SSPP_CURSOR1 = 12,
89 };
90
91 enum mdp5_format {
92 DUMMY = 0,
93 };
94
95 enum mdp5_ctl_mode {
96 MODE_NONE = 0,
97 MODE_WB_0_BLOCK = 1,
98 MODE_WB_1_BLOCK = 2,
99 MODE_WB_0_LINE = 3,
100 MODE_WB_1_LINE = 4,
101 MODE_WB_2_LINE = 5,
102 };
103
104 enum mdp5_pack_3d {
105 PACK_3D_FRAME_INT = 0,
106 PACK_3D_H_ROW_INT = 1,
107 PACK_3D_V_ROW_INT = 2,
108 PACK_3D_COL_INT = 3,
109 };
110
111 enum mdp5_scale_filter {
112 SCALE_FILTER_NEAREST = 0,
113 SCALE_FILTER_BIL = 1,
114 SCALE_FILTER_PCMN = 2,
115 SCALE_FILTER_CA = 3,
116 };
117
118 enum mdp5_pipe_bwc {
119 BWC_LOSSLESS = 0,
120 BWC_Q_HIGH = 1,
121 BWC_Q_MED = 2,
122 };
123
124 enum mdp5_cursor_format {
125 CURSOR_FMT_ARGB8888 = 0,
126 CURSOR_FMT_ARGB1555 = 2,
127 CURSOR_FMT_ARGB4444 = 4,
128 };
129
130 enum mdp5_cursor_alpha {
131 CURSOR_ALPHA_CONST = 0,
132 CURSOR_ALPHA_PER_PIXEL = 2,
133 };
134
135 enum mdp5_igc_type {
136 IGC_VIG = 0,
137 IGC_RGB = 1,
138 IGC_DMA = 2,
139 IGC_DSPP = 3,
140 };
141
142 enum mdp5_data_format {
143 DATA_FORMAT_RGB = 0,
144 DATA_FORMAT_YUV = 1,
145 };
146
147 enum mdp5_block_size {
148 BLOCK_SIZE_64 = 0,
149 BLOCK_SIZE_128 = 1,
150 };
151
152 enum mdp5_rotate_mode {
153 ROTATE_0 = 0,
154 ROTATE_90 = 1,
155 };
156
157 enum mdp5_chroma_downsample_method {
158 DS_MTHD_NO_PIXEL_DROP = 0,
159 DS_MTHD_PIXEL_DROP = 1,
160 };
161
162 #define MDP5_IRQ_WB_0_DONE 0x00000001
163 #define MDP5_IRQ_WB_1_DONE 0x00000002
164 #define MDP5_IRQ_WB_2_DONE 0x00000010
165 #define MDP5_IRQ_PING_PONG_0_DONE 0x00000100
166 #define MDP5_IRQ_PING_PONG_1_DONE 0x00000200
167 #define MDP5_IRQ_PING_PONG_2_DONE 0x00000400
168 #define MDP5_IRQ_PING_PONG_3_DONE 0x00000800
169 #define MDP5_IRQ_PING_PONG_0_RD_PTR 0x00001000
170 #define MDP5_IRQ_PING_PONG_1_RD_PTR 0x00002000
171 #define MDP5_IRQ_PING_PONG_2_RD_PTR 0x00004000
172 #define MDP5_IRQ_PING_PONG_3_RD_PTR 0x00008000
173 #define MDP5_IRQ_PING_PONG_0_WR_PTR 0x00010000
174 #define MDP5_IRQ_PING_PONG_1_WR_PTR 0x00020000
175 #define MDP5_IRQ_PING_PONG_2_WR_PTR 0x00040000
176 #define MDP5_IRQ_PING_PONG_3_WR_PTR 0x00080000
177 #define MDP5_IRQ_PING_PONG_0_AUTO_REF 0x00100000
178 #define MDP5_IRQ_PING_PONG_1_AUTO_REF 0x00200000
179 #define MDP5_IRQ_PING_PONG_2_AUTO_REF 0x00400000
180 #define MDP5_IRQ_PING_PONG_3_AUTO_REF 0x00800000
181 #define MDP5_IRQ_INTF0_UNDER_RUN 0x01000000
182 #define MDP5_IRQ_INTF0_VSYNC 0x02000000
183 #define MDP5_IRQ_INTF1_UNDER_RUN 0x04000000
184 #define MDP5_IRQ_INTF1_VSYNC 0x08000000
185 #define MDP5_IRQ_INTF2_UNDER_RUN 0x10000000
186 #define MDP5_IRQ_INTF2_VSYNC 0x20000000
187 #define MDP5_IRQ_INTF3_UNDER_RUN 0x40000000
188 #define MDP5_IRQ_INTF3_VSYNC 0x80000000
189 #define REG_MDSS_HW_VERSION 0x00000000
190 #define MDSS_HW_VERSION_STEP__MASK 0x0000ffff
191 #define MDSS_HW_VERSION_STEP__SHIFT 0
MDSS_HW_VERSION_STEP(uint32_t val)192 static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val)
193 {
194 return ((val) << MDSS_HW_VERSION_STEP__SHIFT) & MDSS_HW_VERSION_STEP__MASK;
195 }
196 #define MDSS_HW_VERSION_MINOR__MASK 0x0fff0000
197 #define MDSS_HW_VERSION_MINOR__SHIFT 16
MDSS_HW_VERSION_MINOR(uint32_t val)198 static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val)
199 {
200 return ((val) << MDSS_HW_VERSION_MINOR__SHIFT) & MDSS_HW_VERSION_MINOR__MASK;
201 }
202 #define MDSS_HW_VERSION_MAJOR__MASK 0xf0000000
203 #define MDSS_HW_VERSION_MAJOR__SHIFT 28
MDSS_HW_VERSION_MAJOR(uint32_t val)204 static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val)
205 {
206 return ((val) << MDSS_HW_VERSION_MAJOR__SHIFT) & MDSS_HW_VERSION_MAJOR__MASK;
207 }
208
209 #define REG_MDSS_HW_INTR_STATUS 0x00000010
210 #define MDSS_HW_INTR_STATUS_INTR_MDP 0x00000001
211 #define MDSS_HW_INTR_STATUS_INTR_DSI0 0x00000010
212 #define MDSS_HW_INTR_STATUS_INTR_DSI1 0x00000020
213 #define MDSS_HW_INTR_STATUS_INTR_HDMI 0x00000100
214 #define MDSS_HW_INTR_STATUS_INTR_EDP 0x00001000
215
216 #define REG_MDP5_HW_VERSION 0x00000000
217 #define MDP5_HW_VERSION_STEP__MASK 0x0000ffff
218 #define MDP5_HW_VERSION_STEP__SHIFT 0
MDP5_HW_VERSION_STEP(uint32_t val)219 static inline uint32_t MDP5_HW_VERSION_STEP(uint32_t val)
220 {
221 return ((val) << MDP5_HW_VERSION_STEP__SHIFT) & MDP5_HW_VERSION_STEP__MASK;
222 }
223 #define MDP5_HW_VERSION_MINOR__MASK 0x0fff0000
224 #define MDP5_HW_VERSION_MINOR__SHIFT 16
MDP5_HW_VERSION_MINOR(uint32_t val)225 static inline uint32_t MDP5_HW_VERSION_MINOR(uint32_t val)
226 {
227 return ((val) << MDP5_HW_VERSION_MINOR__SHIFT) & MDP5_HW_VERSION_MINOR__MASK;
228 }
229 #define MDP5_HW_VERSION_MAJOR__MASK 0xf0000000
230 #define MDP5_HW_VERSION_MAJOR__SHIFT 28
MDP5_HW_VERSION_MAJOR(uint32_t val)231 static inline uint32_t MDP5_HW_VERSION_MAJOR(uint32_t val)
232 {
233 return ((val) << MDP5_HW_VERSION_MAJOR__SHIFT) & MDP5_HW_VERSION_MAJOR__MASK;
234 }
235
236 #define REG_MDP5_DISP_INTF_SEL 0x00000004
237 #define MDP5_DISP_INTF_SEL_INTF0__MASK 0x000000ff
238 #define MDP5_DISP_INTF_SEL_INTF0__SHIFT 0
MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val)239 static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val)
240 {
241 return ((val) << MDP5_DISP_INTF_SEL_INTF0__SHIFT) & MDP5_DISP_INTF_SEL_INTF0__MASK;
242 }
243 #define MDP5_DISP_INTF_SEL_INTF1__MASK 0x0000ff00
244 #define MDP5_DISP_INTF_SEL_INTF1__SHIFT 8
MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val)245 static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val)
246 {
247 return ((val) << MDP5_DISP_INTF_SEL_INTF1__SHIFT) & MDP5_DISP_INTF_SEL_INTF1__MASK;
248 }
249 #define MDP5_DISP_INTF_SEL_INTF2__MASK 0x00ff0000
250 #define MDP5_DISP_INTF_SEL_INTF2__SHIFT 16
MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val)251 static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val)
252 {
253 return ((val) << MDP5_DISP_INTF_SEL_INTF2__SHIFT) & MDP5_DISP_INTF_SEL_INTF2__MASK;
254 }
255 #define MDP5_DISP_INTF_SEL_INTF3__MASK 0xff000000
256 #define MDP5_DISP_INTF_SEL_INTF3__SHIFT 24
MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val)257 static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val)
258 {
259 return ((val) << MDP5_DISP_INTF_SEL_INTF3__SHIFT) & MDP5_DISP_INTF_SEL_INTF3__MASK;
260 }
261
262 #define REG_MDP5_INTR_EN 0x00000010
263
264 #define REG_MDP5_INTR_STATUS 0x00000014
265
266 #define REG_MDP5_INTR_CLEAR 0x00000018
267
268 #define REG_MDP5_HIST_INTR_EN 0x0000001c
269
270 #define REG_MDP5_HIST_INTR_STATUS 0x00000020
271
272 #define REG_MDP5_HIST_INTR_CLEAR 0x00000024
273
274 #define REG_MDP5_SPARE_0 0x00000028
275 #define MDP5_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN 0x00000001
276
REG_MDP5_SMP_ALLOC_W(uint32_t i0)277 static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000080 + 0x4*i0; }
278
REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0)279 static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000080 + 0x4*i0; }
280 #define MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK 0x000000ff
281 #define MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT 0
MDP5_SMP_ALLOC_W_REG_CLIENT0(uint32_t val)282 static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT0(uint32_t val)
283 {
284 return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK;
285 }
286 #define MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK 0x0000ff00
287 #define MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT 8
MDP5_SMP_ALLOC_W_REG_CLIENT1(uint32_t val)288 static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT1(uint32_t val)
289 {
290 return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK;
291 }
292 #define MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK 0x00ff0000
293 #define MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT 16
MDP5_SMP_ALLOC_W_REG_CLIENT2(uint32_t val)294 static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT2(uint32_t val)
295 {
296 return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK;
297 }
298
REG_MDP5_SMP_ALLOC_R(uint32_t i0)299 static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000130 + 0x4*i0; }
300
REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0)301 static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000130 + 0x4*i0; }
302 #define MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK 0x000000ff
303 #define MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT 0
MDP5_SMP_ALLOC_R_REG_CLIENT0(uint32_t val)304 static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT0(uint32_t val)
305 {
306 return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK;
307 }
308 #define MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK 0x0000ff00
309 #define MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT 8
MDP5_SMP_ALLOC_R_REG_CLIENT1(uint32_t val)310 static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT1(uint32_t val)
311 {
312 return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK;
313 }
314 #define MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK 0x00ff0000
315 #define MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT 16
MDP5_SMP_ALLOC_R_REG_CLIENT2(uint32_t val)316 static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT2(uint32_t val)
317 {
318 return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK;
319 }
320
__offset_IGC(enum mdp5_igc_type idx)321 static inline uint32_t __offset_IGC(enum mdp5_igc_type idx)
322 {
323 switch (idx) {
324 case IGC_VIG: return 0x00000200;
325 case IGC_RGB: return 0x00000210;
326 case IGC_DMA: return 0x00000220;
327 case IGC_DSPP: return 0x00000300;
328 default: return INVALID_IDX(idx);
329 }
330 }
REG_MDP5_IGC(enum mdp5_igc_type i0)331 static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); }
332
REG_MDP5_IGC_LUT(enum mdp5_igc_type i0,uint32_t i1)333 static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
334
REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0,uint32_t i1)335 static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
336 #define MDP5_IGC_LUT_REG_VAL__MASK 0x00000fff
337 #define MDP5_IGC_LUT_REG_VAL__SHIFT 0
MDP5_IGC_LUT_REG_VAL(uint32_t val)338 static inline uint32_t MDP5_IGC_LUT_REG_VAL(uint32_t val)
339 {
340 return ((val) << MDP5_IGC_LUT_REG_VAL__SHIFT) & MDP5_IGC_LUT_REG_VAL__MASK;
341 }
342 #define MDP5_IGC_LUT_REG_INDEX_UPDATE 0x02000000
343 #define MDP5_IGC_LUT_REG_DISABLE_PIPE_0 0x10000000
344 #define MDP5_IGC_LUT_REG_DISABLE_PIPE_1 0x20000000
345 #define MDP5_IGC_LUT_REG_DISABLE_PIPE_2 0x40000000
346
347 #define REG_MDP5_SPLIT_DPL_EN 0x000002f4
348
349 #define REG_MDP5_SPLIT_DPL_UPPER 0x000002f8
350 #define MDP5_SPLIT_DPL_UPPER_SMART_PANEL 0x00000002
351 #define MDP5_SPLIT_DPL_UPPER_SMART_PANEL_FREE_RUN 0x00000004
352 #define MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX 0x00000010
353 #define MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX 0x00000100
354
355 #define REG_MDP5_SPLIT_DPL_LOWER 0x000003f0
356 #define MDP5_SPLIT_DPL_LOWER_SMART_PANEL 0x00000002
357 #define MDP5_SPLIT_DPL_LOWER_SMART_PANEL_FREE_RUN 0x00000004
358 #define MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC 0x00000010
359 #define MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC 0x00000100
360
__offset_CTL(uint32_t idx)361 static inline uint32_t __offset_CTL(uint32_t idx)
362 {
363 switch (idx) {
364 case 0: return (mdp5_cfg->ctl.base[0]);
365 case 1: return (mdp5_cfg->ctl.base[1]);
366 case 2: return (mdp5_cfg->ctl.base[2]);
367 case 3: return (mdp5_cfg->ctl.base[3]);
368 case 4: return (mdp5_cfg->ctl.base[4]);
369 default: return INVALID_IDX(idx);
370 }
371 }
REG_MDP5_CTL(uint32_t i0)372 static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); }
373
__offset_LAYER(uint32_t idx)374 static inline uint32_t __offset_LAYER(uint32_t idx)
375 {
376 switch (idx) {
377 case 0: return 0x00000000;
378 case 1: return 0x00000004;
379 case 2: return 0x00000008;
380 case 3: return 0x0000000c;
381 case 4: return 0x00000010;
382 case 5: return 0x00000024;
383 default: return INVALID_IDX(idx);
384 }
385 }
REG_MDP5_CTL_LAYER(uint32_t i0,uint32_t i1)386 static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
387
REG_MDP5_CTL_LAYER_REG(uint32_t i0,uint32_t i1)388 static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
389 #define MDP5_CTL_LAYER_REG_VIG0__MASK 0x00000007
390 #define MDP5_CTL_LAYER_REG_VIG0__SHIFT 0
MDP5_CTL_LAYER_REG_VIG0(uint32_t val)391 static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(uint32_t val)
392 {
393 return ((val) << MDP5_CTL_LAYER_REG_VIG0__SHIFT) & MDP5_CTL_LAYER_REG_VIG0__MASK;
394 }
395 #define MDP5_CTL_LAYER_REG_VIG1__MASK 0x00000038
396 #define MDP5_CTL_LAYER_REG_VIG1__SHIFT 3
MDP5_CTL_LAYER_REG_VIG1(uint32_t val)397 static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(uint32_t val)
398 {
399 return ((val) << MDP5_CTL_LAYER_REG_VIG1__SHIFT) & MDP5_CTL_LAYER_REG_VIG1__MASK;
400 }
401 #define MDP5_CTL_LAYER_REG_VIG2__MASK 0x000001c0
402 #define MDP5_CTL_LAYER_REG_VIG2__SHIFT 6
MDP5_CTL_LAYER_REG_VIG2(uint32_t val)403 static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(uint32_t val)
404 {
405 return ((val) << MDP5_CTL_LAYER_REG_VIG2__SHIFT) & MDP5_CTL_LAYER_REG_VIG2__MASK;
406 }
407 #define MDP5_CTL_LAYER_REG_RGB0__MASK 0x00000e00
408 #define MDP5_CTL_LAYER_REG_RGB0__SHIFT 9
MDP5_CTL_LAYER_REG_RGB0(uint32_t val)409 static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(uint32_t val)
410 {
411 return ((val) << MDP5_CTL_LAYER_REG_RGB0__SHIFT) & MDP5_CTL_LAYER_REG_RGB0__MASK;
412 }
413 #define MDP5_CTL_LAYER_REG_RGB1__MASK 0x00007000
414 #define MDP5_CTL_LAYER_REG_RGB1__SHIFT 12
MDP5_CTL_LAYER_REG_RGB1(uint32_t val)415 static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(uint32_t val)
416 {
417 return ((val) << MDP5_CTL_LAYER_REG_RGB1__SHIFT) & MDP5_CTL_LAYER_REG_RGB1__MASK;
418 }
419 #define MDP5_CTL_LAYER_REG_RGB2__MASK 0x00038000
420 #define MDP5_CTL_LAYER_REG_RGB2__SHIFT 15
MDP5_CTL_LAYER_REG_RGB2(uint32_t val)421 static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(uint32_t val)
422 {
423 return ((val) << MDP5_CTL_LAYER_REG_RGB2__SHIFT) & MDP5_CTL_LAYER_REG_RGB2__MASK;
424 }
425 #define MDP5_CTL_LAYER_REG_DMA0__MASK 0x001c0000
426 #define MDP5_CTL_LAYER_REG_DMA0__SHIFT 18
MDP5_CTL_LAYER_REG_DMA0(uint32_t val)427 static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(uint32_t val)
428 {
429 return ((val) << MDP5_CTL_LAYER_REG_DMA0__SHIFT) & MDP5_CTL_LAYER_REG_DMA0__MASK;
430 }
431 #define MDP5_CTL_LAYER_REG_DMA1__MASK 0x00e00000
432 #define MDP5_CTL_LAYER_REG_DMA1__SHIFT 21
MDP5_CTL_LAYER_REG_DMA1(uint32_t val)433 static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(uint32_t val)
434 {
435 return ((val) << MDP5_CTL_LAYER_REG_DMA1__SHIFT) & MDP5_CTL_LAYER_REG_DMA1__MASK;
436 }
437 #define MDP5_CTL_LAYER_REG_BORDER_COLOR 0x01000000
438 #define MDP5_CTL_LAYER_REG_CURSOR_OUT 0x02000000
439 #define MDP5_CTL_LAYER_REG_VIG3__MASK 0x1c000000
440 #define MDP5_CTL_LAYER_REG_VIG3__SHIFT 26
MDP5_CTL_LAYER_REG_VIG3(uint32_t val)441 static inline uint32_t MDP5_CTL_LAYER_REG_VIG3(uint32_t val)
442 {
443 return ((val) << MDP5_CTL_LAYER_REG_VIG3__SHIFT) & MDP5_CTL_LAYER_REG_VIG3__MASK;
444 }
445 #define MDP5_CTL_LAYER_REG_RGB3__MASK 0xe0000000
446 #define MDP5_CTL_LAYER_REG_RGB3__SHIFT 29
MDP5_CTL_LAYER_REG_RGB3(uint32_t val)447 static inline uint32_t MDP5_CTL_LAYER_REG_RGB3(uint32_t val)
448 {
449 return ((val) << MDP5_CTL_LAYER_REG_RGB3__SHIFT) & MDP5_CTL_LAYER_REG_RGB3__MASK;
450 }
451
REG_MDP5_CTL_OP(uint32_t i0)452 static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); }
453 #define MDP5_CTL_OP_MODE__MASK 0x0000000f
454 #define MDP5_CTL_OP_MODE__SHIFT 0
MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val)455 static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val)
456 {
457 return ((val) << MDP5_CTL_OP_MODE__SHIFT) & MDP5_CTL_OP_MODE__MASK;
458 }
459 #define MDP5_CTL_OP_INTF_NUM__MASK 0x00000070
460 #define MDP5_CTL_OP_INTF_NUM__SHIFT 4
MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val)461 static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val)
462 {
463 return ((val) << MDP5_CTL_OP_INTF_NUM__SHIFT) & MDP5_CTL_OP_INTF_NUM__MASK;
464 }
465 #define MDP5_CTL_OP_CMD_MODE 0x00020000
466 #define MDP5_CTL_OP_PACK_3D_ENABLE 0x00080000
467 #define MDP5_CTL_OP_PACK_3D__MASK 0x00300000
468 #define MDP5_CTL_OP_PACK_3D__SHIFT 20
MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val)469 static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val)
470 {
471 return ((val) << MDP5_CTL_OP_PACK_3D__SHIFT) & MDP5_CTL_OP_PACK_3D__MASK;
472 }
473
REG_MDP5_CTL_FLUSH(uint32_t i0)474 static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); }
475 #define MDP5_CTL_FLUSH_VIG0 0x00000001
476 #define MDP5_CTL_FLUSH_VIG1 0x00000002
477 #define MDP5_CTL_FLUSH_VIG2 0x00000004
478 #define MDP5_CTL_FLUSH_RGB0 0x00000008
479 #define MDP5_CTL_FLUSH_RGB1 0x00000010
480 #define MDP5_CTL_FLUSH_RGB2 0x00000020
481 #define MDP5_CTL_FLUSH_LM0 0x00000040
482 #define MDP5_CTL_FLUSH_LM1 0x00000080
483 #define MDP5_CTL_FLUSH_LM2 0x00000100
484 #define MDP5_CTL_FLUSH_LM3 0x00000200
485 #define MDP5_CTL_FLUSH_LM4 0x00000400
486 #define MDP5_CTL_FLUSH_DMA0 0x00000800
487 #define MDP5_CTL_FLUSH_DMA1 0x00001000
488 #define MDP5_CTL_FLUSH_DSPP0 0x00002000
489 #define MDP5_CTL_FLUSH_DSPP1 0x00004000
490 #define MDP5_CTL_FLUSH_DSPP2 0x00008000
491 #define MDP5_CTL_FLUSH_WB 0x00010000
492 #define MDP5_CTL_FLUSH_CTL 0x00020000
493 #define MDP5_CTL_FLUSH_VIG3 0x00040000
494 #define MDP5_CTL_FLUSH_RGB3 0x00080000
495 #define MDP5_CTL_FLUSH_LM5 0x00100000
496 #define MDP5_CTL_FLUSH_DSPP3 0x00200000
497 #define MDP5_CTL_FLUSH_CURSOR_0 0x00400000
498 #define MDP5_CTL_FLUSH_CURSOR_1 0x00800000
499 #define MDP5_CTL_FLUSH_CHROMADOWN_0 0x04000000
500 #define MDP5_CTL_FLUSH_TIMING_3 0x10000000
501 #define MDP5_CTL_FLUSH_TIMING_2 0x20000000
502 #define MDP5_CTL_FLUSH_TIMING_1 0x40000000
503 #define MDP5_CTL_FLUSH_TIMING_0 0x80000000
504
REG_MDP5_CTL_START(uint32_t i0)505 static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); }
506
REG_MDP5_CTL_PACK_3D(uint32_t i0)507 static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); }
508
__offset_LAYER_EXT(uint32_t idx)509 static inline uint32_t __offset_LAYER_EXT(uint32_t idx)
510 {
511 switch (idx) {
512 case 0: return 0x00000040;
513 case 1: return 0x00000044;
514 case 2: return 0x00000048;
515 case 3: return 0x0000004c;
516 case 4: return 0x00000050;
517 case 5: return 0x00000054;
518 default: return INVALID_IDX(idx);
519 }
520 }
REG_MDP5_CTL_LAYER_EXT(uint32_t i0,uint32_t i1)521 static inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); }
522
REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0,uint32_t i1)523 static inline uint32_t REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); }
524 #define MDP5_CTL_LAYER_EXT_REG_VIG0_BIT3 0x00000001
525 #define MDP5_CTL_LAYER_EXT_REG_VIG1_BIT3 0x00000004
526 #define MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3 0x00000010
527 #define MDP5_CTL_LAYER_EXT_REG_VIG3_BIT3 0x00000040
528 #define MDP5_CTL_LAYER_EXT_REG_RGB0_BIT3 0x00000100
529 #define MDP5_CTL_LAYER_EXT_REG_RGB1_BIT3 0x00000400
530 #define MDP5_CTL_LAYER_EXT_REG_RGB2_BIT3 0x00001000
531 #define MDP5_CTL_LAYER_EXT_REG_RGB3_BIT3 0x00004000
532 #define MDP5_CTL_LAYER_EXT_REG_DMA0_BIT3 0x00010000
533 #define MDP5_CTL_LAYER_EXT_REG_DMA1_BIT3 0x00040000
534 #define MDP5_CTL_LAYER_EXT_REG_CURSOR0__MASK 0x00f00000
535 #define MDP5_CTL_LAYER_EXT_REG_CURSOR0__SHIFT 20
MDP5_CTL_LAYER_EXT_REG_CURSOR0(enum mdp_mixer_stage_id val)536 static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR0(enum mdp_mixer_stage_id val)
537 {
538 return ((val) << MDP5_CTL_LAYER_EXT_REG_CURSOR0__SHIFT) & MDP5_CTL_LAYER_EXT_REG_CURSOR0__MASK;
539 }
540 #define MDP5_CTL_LAYER_EXT_REG_CURSOR1__MASK 0x3c000000
541 #define MDP5_CTL_LAYER_EXT_REG_CURSOR1__SHIFT 26
MDP5_CTL_LAYER_EXT_REG_CURSOR1(enum mdp_mixer_stage_id val)542 static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR1(enum mdp_mixer_stage_id val)
543 {
544 return ((val) << MDP5_CTL_LAYER_EXT_REG_CURSOR1__SHIFT) & MDP5_CTL_LAYER_EXT_REG_CURSOR1__MASK;
545 }
546
__offset_PIPE(enum mdp5_pipe idx)547 static inline uint32_t __offset_PIPE(enum mdp5_pipe idx)
548 {
549 switch (idx) {
550 case SSPP_NONE: return (INVALID_IDX(idx));
551 case SSPP_VIG0: return (mdp5_cfg->pipe_vig.base[0]);
552 case SSPP_VIG1: return (mdp5_cfg->pipe_vig.base[1]);
553 case SSPP_VIG2: return (mdp5_cfg->pipe_vig.base[2]);
554 case SSPP_RGB0: return (mdp5_cfg->pipe_rgb.base[0]);
555 case SSPP_RGB1: return (mdp5_cfg->pipe_rgb.base[1]);
556 case SSPP_RGB2: return (mdp5_cfg->pipe_rgb.base[2]);
557 case SSPP_DMA0: return (mdp5_cfg->pipe_dma.base[0]);
558 case SSPP_DMA1: return (mdp5_cfg->pipe_dma.base[1]);
559 case SSPP_VIG3: return (mdp5_cfg->pipe_vig.base[3]);
560 case SSPP_RGB3: return (mdp5_cfg->pipe_rgb.base[3]);
561 case SSPP_CURSOR0: return (mdp5_cfg->pipe_cursor.base[0]);
562 case SSPP_CURSOR1: return (mdp5_cfg->pipe_cursor.base[1]);
563 default: return INVALID_IDX(idx);
564 }
565 }
REG_MDP5_PIPE(enum mdp5_pipe i0)566 static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
567
REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0)568 static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE(i0); }
569 #define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK 0x00080000
570 #define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT 19
MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(enum mdp5_data_format val)571 static inline uint32_t MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(enum mdp5_data_format val)
572 {
573 return ((val) << MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK;
574 }
575 #define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK 0x00040000
576 #define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT 18
MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(enum mdp5_data_format val)577 static inline uint32_t MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(enum mdp5_data_format val)
578 {
579 return ((val) << MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK;
580 }
581 #define MDP5_PIPE_OP_MODE_CSC_1_EN 0x00020000
582
REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0)583 static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offset_PIPE(i0); }
584
REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0)585 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offset_PIPE(i0); }
586
REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0)587 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offset_PIPE(i0); }
588
REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0)589 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + __offset_PIPE(i0); }
590 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK 0x00001fff
591 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT 0
MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(uint32_t val)592 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(uint32_t val)
593 {
594 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK;
595 }
596 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK 0x1fff0000
597 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT 16
MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(uint32_t val)598 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(uint32_t val)
599 {
600 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK;
601 }
602
REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0)603 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + __offset_PIPE(i0); }
604 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK 0x00001fff
605 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT 0
MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(uint32_t val)606 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(uint32_t val)
607 {
608 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK;
609 }
610 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK 0x1fff0000
611 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT 16
MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(uint32_t val)612 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(uint32_t val)
613 {
614 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK;
615 }
616
REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0)617 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + __offset_PIPE(i0); }
618 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK 0x00001fff
619 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT 0
MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(uint32_t val)620 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(uint32_t val)
621 {
622 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK;
623 }
624 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK 0x1fff0000
625 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT 16
MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(uint32_t val)626 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(uint32_t val)
627 {
628 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK;
629 }
630
REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0)631 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + __offset_PIPE(i0); }
632 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK 0x00001fff
633 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT 0
MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(uint32_t val)634 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(uint32_t val)
635 {
636 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK;
637 }
638 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK 0x1fff0000
639 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT 16
MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(uint32_t val)640 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(uint32_t val)
641 {
642 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK;
643 }
644
REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0)645 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + __offset_PIPE(i0); }
646 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK 0x00001fff
647 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT 0
MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(uint32_t val)648 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(uint32_t val)
649 {
650 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK;
651 }
652
REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0,uint32_t i1)653 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
654
REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0,uint32_t i1)655 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
656 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK 0x000000ff
657 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT 0
MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(uint32_t val)658 static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(uint32_t val)
659 {
660 return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK;
661 }
662 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK 0x0000ff00
663 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT 8
MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(uint32_t val)664 static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(uint32_t val)
665 {
666 return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK;
667 }
668
REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0,uint32_t i1)669 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
670
REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0,uint32_t i1)671 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
672 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK 0x000000ff
673 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT 0
MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(uint32_t val)674 static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(uint32_t val)
675 {
676 return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK;
677 }
678 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK 0x0000ff00
679 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT 8
MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(uint32_t val)680 static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(uint32_t val)
681 {
682 return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK;
683 }
684
REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0,uint32_t i1)685 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
686
REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0,uint32_t i1)687 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
688 #define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK 0x000001ff
689 #define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT 0
MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(uint32_t val)690 static inline uint32_t MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(uint32_t val)
691 {
692 return ((val) << MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK;
693 }
694
REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0,uint32_t i1)695 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
696
REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0,uint32_t i1)697 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
698 #define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK 0x000001ff
699 #define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT 0
MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(uint32_t val)700 static inline uint32_t MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(uint32_t val)
701 {
702 return ((val) << MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK;
703 }
704
REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0)705 static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
706 #define MDP5_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000
707 #define MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT 16
MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val)708 static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
709 {
710 return ((val) << MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_SIZE_HEIGHT__MASK;
711 }
712 #define MDP5_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff
713 #define MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT 0
MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val)714 static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val)
715 {
716 return ((val) << MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_SIZE_WIDTH__MASK;
717 }
718
REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0)719 static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset_PIPE(i0); }
720 #define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK 0xffff0000
721 #define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT 16
MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val)722 static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val)
723 {
724 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK;
725 }
726 #define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK 0x0000ffff
727 #define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT 0
MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val)728 static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val)
729 {
730 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK;
731 }
732
REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0)733 static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(i0); }
734 #define MDP5_PIPE_SRC_XY_Y__MASK 0xffff0000
735 #define MDP5_PIPE_SRC_XY_Y__SHIFT 16
MDP5_PIPE_SRC_XY_Y(uint32_t val)736 static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val)
737 {
738 return ((val) << MDP5_PIPE_SRC_XY_Y__SHIFT) & MDP5_PIPE_SRC_XY_Y__MASK;
739 }
740 #define MDP5_PIPE_SRC_XY_X__MASK 0x0000ffff
741 #define MDP5_PIPE_SRC_XY_X__SHIFT 0
MDP5_PIPE_SRC_XY_X(uint32_t val)742 static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val)
743 {
744 return ((val) << MDP5_PIPE_SRC_XY_X__SHIFT) & MDP5_PIPE_SRC_XY_X__MASK;
745 }
746
REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0)747 static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIPE(i0); }
748 #define MDP5_PIPE_OUT_SIZE_HEIGHT__MASK 0xffff0000
749 #define MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT 16
MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val)750 static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val)
751 {
752 return ((val) << MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_OUT_SIZE_HEIGHT__MASK;
753 }
754 #define MDP5_PIPE_OUT_SIZE_WIDTH__MASK 0x0000ffff
755 #define MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT 0
MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val)756 static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val)
757 {
758 return ((val) << MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT) & MDP5_PIPE_OUT_SIZE_WIDTH__MASK;
759 }
760
REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0)761 static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(i0); }
762 #define MDP5_PIPE_OUT_XY_Y__MASK 0xffff0000
763 #define MDP5_PIPE_OUT_XY_Y__SHIFT 16
MDP5_PIPE_OUT_XY_Y(uint32_t val)764 static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val)
765 {
766 return ((val) << MDP5_PIPE_OUT_XY_Y__SHIFT) & MDP5_PIPE_OUT_XY_Y__MASK;
767 }
768 #define MDP5_PIPE_OUT_XY_X__MASK 0x0000ffff
769 #define MDP5_PIPE_OUT_XY_X__SHIFT 0
MDP5_PIPE_OUT_XY_X(uint32_t val)770 static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val)
771 {
772 return ((val) << MDP5_PIPE_OUT_XY_X__SHIFT) & MDP5_PIPE_OUT_XY_X__MASK;
773 }
774
REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0)775 static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PIPE(i0); }
776
REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0)777 static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PIPE(i0); }
778
REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0)779 static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PIPE(i0); }
780
REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0)781 static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PIPE(i0); }
782
REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0)783 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset_PIPE(i0); }
784 #define MDP5_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff
785 #define MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT 0
MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val)786 static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val)
787 {
788 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P0__MASK;
789 }
790 #define MDP5_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000
791 #define MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT 16
MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val)792 static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val)
793 {
794 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P1__MASK;
795 }
796
REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0)797 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset_PIPE(i0); }
798 #define MDP5_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff
799 #define MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT 0
MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val)800 static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val)
801 {
802 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P2__MASK;
803 }
804 #define MDP5_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000
805 #define MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT 16
MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val)806 static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val)
807 {
808 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P3__MASK;
809 }
810
REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0)811 static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __offset_PIPE(i0); }
812
REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0)813 static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_PIPE(i0); }
814 #define MDP5_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
815 #define MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)816 static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
817 {
818 return ((val) << MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_G_BPC__MASK;
819 }
820 #define MDP5_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
821 #define MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT 2
MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)822 static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
823 {
824 return ((val) << MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_B_BPC__MASK;
825 }
826 #define MDP5_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
827 #define MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT 4
MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)828 static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
829 {
830 return ((val) << MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_R_BPC__MASK;
831 }
832 #define MDP5_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
833 #define MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT 6
MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)834 static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
835 {
836 return ((val) << MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_A_BPC__MASK;
837 }
838 #define MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100
839 #define MDP5_PIPE_SRC_FORMAT_CPP__MASK 0x00000600
840 #define MDP5_PIPE_SRC_FORMAT_CPP__SHIFT 9
MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val)841 static inline uint32_t MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val)
842 {
843 return ((val) << MDP5_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CPP__MASK;
844 }
845 #define MDP5_PIPE_SRC_FORMAT_ROT90 0x00000800
846 #define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00003000
847 #define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 12
MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)848 static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
849 {
850 return ((val) << MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK;
851 }
852 #define MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000
853 #define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000
854 #define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK 0x00180000
855 #define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT 19
MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(enum mdp_fetch_type val)856 static inline uint32_t MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(enum mdp_fetch_type val)
857 {
858 return ((val) << MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT) & MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK;
859 }
860 #define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x01800000
861 #define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT 23
MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)862 static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)
863 {
864 return ((val) << MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
865 }
866
REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0)867 static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_PIPE(i0); }
868 #define MDP5_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff
869 #define MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT 0
MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val)870 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
871 {
872 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM0__MASK;
873 }
874 #define MDP5_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00
875 #define MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT 8
MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val)876 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
877 {
878 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM1__MASK;
879 }
880 #define MDP5_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000
881 #define MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT 16
MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val)882 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
883 {
884 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM2__MASK;
885 }
886 #define MDP5_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000
887 #define MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT 24
MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val)888 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
889 {
890 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM3__MASK;
891 }
892
REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0)893 static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_PIPE(i0); }
894 #define MDP5_PIPE_SRC_OP_MODE_BWC_EN 0x00000001
895 #define MDP5_PIPE_SRC_OP_MODE_BWC__MASK 0x00000006
896 #define MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT 1
MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val)897 static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val)
898 {
899 return ((val) << MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT) & MDP5_PIPE_SRC_OP_MODE_BWC__MASK;
900 }
901 #define MDP5_PIPE_SRC_OP_MODE_FLIP_LR 0x00002000
902 #define MDP5_PIPE_SRC_OP_MODE_FLIP_UD 0x00004000
903 #define MDP5_PIPE_SRC_OP_MODE_IGC_EN 0x00010000
904 #define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_0 0x00020000
905 #define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_1 0x00040000
906 #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE 0x00400000
907 #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE_ODD 0x00800000
908 #define MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE 0x80000000
909
REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0)910 static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0); }
911
REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0)912 static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset_PIPE(i0); }
913
REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0)914 static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PIPE(i0); }
915
REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0)916 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __offset_PIPE(i0); }
917
REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0)918 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __offset_PIPE(i0); }
919
REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0)920 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __offset_PIPE(i0); }
921
REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0)922 static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __offset_PIPE(i0); }
923
REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0)924 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __offset_PIPE(i0); }
925
REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0)926 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __offset_PIPE(i0); }
927
REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0)928 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __offset_PIPE(i0); }
929
REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0)930 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __offset_PIPE(i0); }
931
REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0)932 static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_PIPE(i0); }
933 #define MDP5_PIPE_DECIMATION_VERT__MASK 0x000000ff
934 #define MDP5_PIPE_DECIMATION_VERT__SHIFT 0
MDP5_PIPE_DECIMATION_VERT(uint32_t val)935 static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val)
936 {
937 return ((val) << MDP5_PIPE_DECIMATION_VERT__SHIFT) & MDP5_PIPE_DECIMATION_VERT__MASK;
938 }
939 #define MDP5_PIPE_DECIMATION_HORZ__MASK 0x0000ff00
940 #define MDP5_PIPE_DECIMATION_HORZ__SHIFT 8
MDP5_PIPE_DECIMATION_HORZ(uint32_t val)941 static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val)
942 {
943 return ((val) << MDP5_PIPE_DECIMATION_HORZ__SHIFT) & MDP5_PIPE_DECIMATION_HORZ__MASK;
944 }
945
__offset_SW_PIX_EXT(enum mdp_component_type idx)946 static inline uint32_t __offset_SW_PIX_EXT(enum mdp_component_type idx)
947 {
948 switch (idx) {
949 case COMP_0: return 0x00000100;
950 case COMP_1_2: return 0x00000110;
951 case COMP_3: return 0x00000120;
952 default: return INVALID_IDX(idx);
953 }
954 }
REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0,enum mdp_component_type i1)955 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
956
REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0,enum mdp_component_type i1)957 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
958 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK 0x000000ff
959 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT 0
MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(uint32_t val)960 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(uint32_t val)
961 {
962 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK;
963 }
964 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK 0x0000ff00
965 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT 8
MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(int32_t val)966 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(int32_t val)
967 {
968 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK;
969 }
970 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK 0x00ff0000
971 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT 16
MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(uint32_t val)972 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(uint32_t val)
973 {
974 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK;
975 }
976 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK 0xff000000
977 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT 24
MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(int32_t val)978 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(int32_t val)
979 {
980 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK;
981 }
982
REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0,enum mdp_component_type i1)983 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000004 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
984 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK 0x000000ff
985 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT 0
MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(uint32_t val)986 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(uint32_t val)
987 {
988 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK;
989 }
990 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK 0x0000ff00
991 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT 8
MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(int32_t val)992 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(int32_t val)
993 {
994 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK;
995 }
996 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK 0x00ff0000
997 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT 16
MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(uint32_t val)998 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(uint32_t val)
999 {
1000 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK;
1001 }
1002 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK 0xff000000
1003 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT 24
MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(int32_t val)1004 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(int32_t val)
1005 {
1006 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK;
1007 }
1008
REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0,enum mdp_component_type i1)1009 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000008 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
1010 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK 0x0000ffff
1011 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT 0
MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(uint32_t val)1012 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(uint32_t val)
1013 {
1014 return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK;
1015 }
1016 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK 0xffff0000
1017 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT 16
MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(uint32_t val)1018 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(uint32_t val)
1019 {
1020 return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK;
1021 }
1022
REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0)1023 static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0); }
1024 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN 0x00000001
1025 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN 0x00000002
1026 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK 0x00000300
1027 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT 8
MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(enum mdp5_scale_filter val)1028 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(enum mdp5_scale_filter val)
1029 {
1030 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK;
1031 }
1032 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK 0x00000c00
1033 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT 10
MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(enum mdp5_scale_filter val)1034 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(enum mdp5_scale_filter val)
1035 {
1036 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK;
1037 }
1038 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK 0x00003000
1039 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT 12
MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(enum mdp5_scale_filter val)1040 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(enum mdp5_scale_filter val)
1041 {
1042 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK;
1043 }
1044 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__MASK 0x0000c000
1045 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__SHIFT 14
MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(enum mdp5_scale_filter val)1046 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(enum mdp5_scale_filter val)
1047 {
1048 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__MASK;
1049 }
1050 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__MASK 0x00030000
1051 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__SHIFT 16
MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(enum mdp5_scale_filter val)1052 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(enum mdp5_scale_filter val)
1053 {
1054 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__MASK;
1055 }
1056 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__MASK 0x000c0000
1057 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__SHIFT 18
MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(enum mdp5_scale_filter val)1058 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(enum mdp5_scale_filter val)
1059 {
1060 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__MASK;
1061 }
1062
REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0)1063 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __offset_PIPE(i0); }
1064
REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0)1065 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __offset_PIPE(i0); }
1066
REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0)1067 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 + __offset_PIPE(i0); }
1068
REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0)1069 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c + __offset_PIPE(i0); }
1070
REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0)1071 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __offset_PIPE(i0); }
1072
REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0)1073 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __offset_PIPE(i0); }
1074
__offset_LM(uint32_t idx)1075 static inline uint32_t __offset_LM(uint32_t idx)
1076 {
1077 switch (idx) {
1078 case 0: return (mdp5_cfg->lm.base[0]);
1079 case 1: return (mdp5_cfg->lm.base[1]);
1080 case 2: return (mdp5_cfg->lm.base[2]);
1081 case 3: return (mdp5_cfg->lm.base[3]);
1082 case 4: return (mdp5_cfg->lm.base[4]);
1083 case 5: return (mdp5_cfg->lm.base[5]);
1084 default: return INVALID_IDX(idx);
1085 }
1086 }
REG_MDP5_LM(uint32_t i0)1087 static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
1088
REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0)1089 static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
1090 #define MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA 0x00000002
1091 #define MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA 0x00000004
1092 #define MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA 0x00000008
1093 #define MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA 0x00000010
1094 #define MDP5_LM_BLEND_COLOR_OUT_STAGE4_FG_ALPHA 0x00000020
1095 #define MDP5_LM_BLEND_COLOR_OUT_STAGE5_FG_ALPHA 0x00000040
1096 #define MDP5_LM_BLEND_COLOR_OUT_STAGE6_FG_ALPHA 0x00000080
1097 #define MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT 0x80000000
1098
REG_MDP5_LM_OUT_SIZE(uint32_t i0)1099 static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); }
1100 #define MDP5_LM_OUT_SIZE_HEIGHT__MASK 0xffff0000
1101 #define MDP5_LM_OUT_SIZE_HEIGHT__SHIFT 16
MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val)1102 static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val)
1103 {
1104 return ((val) << MDP5_LM_OUT_SIZE_HEIGHT__SHIFT) & MDP5_LM_OUT_SIZE_HEIGHT__MASK;
1105 }
1106 #define MDP5_LM_OUT_SIZE_WIDTH__MASK 0x0000ffff
1107 #define MDP5_LM_OUT_SIZE_WIDTH__SHIFT 0
MDP5_LM_OUT_SIZE_WIDTH(uint32_t val)1108 static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val)
1109 {
1110 return ((val) << MDP5_LM_OUT_SIZE_WIDTH__SHIFT) & MDP5_LM_OUT_SIZE_WIDTH__MASK;
1111 }
1112
REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0)1113 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0); }
1114
REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0)1115 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0); }
1116
__offset_BLEND(uint32_t idx)1117 static inline uint32_t __offset_BLEND(uint32_t idx)
1118 {
1119 switch (idx) {
1120 case 0: return 0x00000020;
1121 case 1: return 0x00000050;
1122 case 2: return 0x00000080;
1123 case 3: return 0x000000b0;
1124 case 4: return 0x00000230;
1125 case 5: return 0x00000260;
1126 case 6: return 0x00000290;
1127 default: return INVALID_IDX(idx);
1128 }
1129 }
REG_MDP5_LM_BLEND(uint32_t i0,uint32_t i1)1130 static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); }
1131
REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0,uint32_t i1)1132 static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); }
1133 #define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK 0x00000003
1134 #define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT 0
MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val)1135 static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val)
1136 {
1137 return ((val) << MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK;
1138 }
1139 #define MDP5_LM_BLEND_OP_MODE_FG_INV_ALPHA 0x00000004
1140 #define MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA 0x00000008
1141 #define MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA 0x00000010
1142 #define MDP5_LM_BLEND_OP_MODE_FG_TRANSP_EN 0x00000020
1143 #define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK 0x00000300
1144 #define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT 8
MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val)1145 static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val)
1146 {
1147 return ((val) << MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK;
1148 }
1149 #define MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA 0x00000400
1150 #define MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA 0x00000800
1151 #define MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA 0x00001000
1152 #define MDP5_LM_BLEND_OP_MODE_BG_TRANSP_EN 0x00002000
1153
REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0,uint32_t i1)1154 static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_LM(i0) + __offset_BLEND(i1); }
1155
REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0,uint32_t i1)1156 static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_LM(i0) + __offset_BLEND(i1); }
1157
REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0,uint32_t i1)1158 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_LM(i0) + __offset_BLEND(i1); }
1159
REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0,uint32_t i1)1160 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_LM(i0) + __offset_BLEND(i1); }
1161
REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0,uint32_t i1)1162 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_LM(i0) + __offset_BLEND(i1); }
1163
REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0,uint32_t i1)1164 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_LM(i0) + __offset_BLEND(i1); }
1165
REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0,uint32_t i1)1166 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000001c + __offset_LM(i0) + __offset_BLEND(i1); }
1167
REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0,uint32_t i1)1168 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + __offset_BLEND(i1); }
1169
REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0,uint32_t i1)1170 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_LM(i0) + __offset_BLEND(i1); }
1171
REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0,uint32_t i1)1172 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_LM(i0) + __offset_BLEND(i1); }
1173
REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0)1174 static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i0); }
1175 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK 0x0000ffff
1176 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT 0
MDP5_LM_CURSOR_IMG_SIZE_SRC_W(uint32_t val)1177 static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_W(uint32_t val)
1178 {
1179 return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK;
1180 }
1181 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK 0xffff0000
1182 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT 16
MDP5_LM_CURSOR_IMG_SIZE_SRC_H(uint32_t val)1183 static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_H(uint32_t val)
1184 {
1185 return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK;
1186 }
1187
REG_MDP5_LM_CURSOR_SIZE(uint32_t i0)1188 static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); }
1189 #define MDP5_LM_CURSOR_SIZE_ROI_W__MASK 0x0000ffff
1190 #define MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT 0
MDP5_LM_CURSOR_SIZE_ROI_W(uint32_t val)1191 static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_W(uint32_t val)
1192 {
1193 return ((val) << MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_W__MASK;
1194 }
1195 #define MDP5_LM_CURSOR_SIZE_ROI_H__MASK 0xffff0000
1196 #define MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT 16
MDP5_LM_CURSOR_SIZE_ROI_H(uint32_t val)1197 static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_H(uint32_t val)
1198 {
1199 return ((val) << MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_H__MASK;
1200 }
1201
REG_MDP5_LM_CURSOR_XY(uint32_t i0)1202 static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); }
1203 #define MDP5_LM_CURSOR_XY_SRC_X__MASK 0x0000ffff
1204 #define MDP5_LM_CURSOR_XY_SRC_X__SHIFT 0
MDP5_LM_CURSOR_XY_SRC_X(uint32_t val)1205 static inline uint32_t MDP5_LM_CURSOR_XY_SRC_X(uint32_t val)
1206 {
1207 return ((val) << MDP5_LM_CURSOR_XY_SRC_X__SHIFT) & MDP5_LM_CURSOR_XY_SRC_X__MASK;
1208 }
1209 #define MDP5_LM_CURSOR_XY_SRC_Y__MASK 0xffff0000
1210 #define MDP5_LM_CURSOR_XY_SRC_Y__SHIFT 16
MDP5_LM_CURSOR_XY_SRC_Y(uint32_t val)1211 static inline uint32_t MDP5_LM_CURSOR_XY_SRC_Y(uint32_t val)
1212 {
1213 return ((val) << MDP5_LM_CURSOR_XY_SRC_Y__SHIFT) & MDP5_LM_CURSOR_XY_SRC_Y__MASK;
1214 }
1215
REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0)1216 static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0); }
1217 #define MDP5_LM_CURSOR_STRIDE_STRIDE__MASK 0x0000ffff
1218 #define MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT 0
MDP5_LM_CURSOR_STRIDE_STRIDE(uint32_t val)1219 static inline uint32_t MDP5_LM_CURSOR_STRIDE_STRIDE(uint32_t val)
1220 {
1221 return ((val) << MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT) & MDP5_LM_CURSOR_STRIDE_STRIDE__MASK;
1222 }
1223
REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0)1224 static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0); }
1225 #define MDP5_LM_CURSOR_FORMAT_FORMAT__MASK 0x00000007
1226 #define MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT 0
MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format val)1227 static inline uint32_t MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format val)
1228 {
1229 return ((val) << MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT) & MDP5_LM_CURSOR_FORMAT_FORMAT__MASK;
1230 }
1231
REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0)1232 static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(i0); }
1233
REG_MDP5_LM_CURSOR_START_XY(uint32_t i0)1234 static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i0); }
1235 #define MDP5_LM_CURSOR_START_XY_X_START__MASK 0x0000ffff
1236 #define MDP5_LM_CURSOR_START_XY_X_START__SHIFT 0
MDP5_LM_CURSOR_START_XY_X_START(uint32_t val)1237 static inline uint32_t MDP5_LM_CURSOR_START_XY_X_START(uint32_t val)
1238 {
1239 return ((val) << MDP5_LM_CURSOR_START_XY_X_START__SHIFT) & MDP5_LM_CURSOR_START_XY_X_START__MASK;
1240 }
1241 #define MDP5_LM_CURSOR_START_XY_Y_START__MASK 0xffff0000
1242 #define MDP5_LM_CURSOR_START_XY_Y_START__SHIFT 16
MDP5_LM_CURSOR_START_XY_Y_START(uint32_t val)1243 static inline uint32_t MDP5_LM_CURSOR_START_XY_Y_START(uint32_t val)
1244 {
1245 return ((val) << MDP5_LM_CURSOR_START_XY_Y_START__SHIFT) & MDP5_LM_CURSOR_START_XY_Y_START__MASK;
1246 }
1247
REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0)1248 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_LM(i0); }
1249 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN 0x00000001
1250 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK 0x00000006
1251 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT 1
MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(enum mdp5_cursor_alpha val)1252 static inline uint32_t MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(enum mdp5_cursor_alpha val)
1253 {
1254 return ((val) << MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT) & MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK;
1255 }
1256 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_TRANSP_EN 0x00000008
1257
REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0)1258 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_LM(i0); }
1259
REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0)1260 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __offset_LM(i0); }
1261
REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0)1262 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __offset_LM(i0); }
1263
REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0)1264 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __offset_LM(i0); }
1265
REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0)1266 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __offset_LM(i0); }
1267
REG_MDP5_LM_GC_LUT_BASE(uint32_t i0)1268 static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); }
1269
__offset_DSPP(uint32_t idx)1270 static inline uint32_t __offset_DSPP(uint32_t idx)
1271 {
1272 switch (idx) {
1273 case 0: return (mdp5_cfg->dspp.base[0]);
1274 case 1: return (mdp5_cfg->dspp.base[1]);
1275 case 2: return (mdp5_cfg->dspp.base[2]);
1276 case 3: return (mdp5_cfg->dspp.base[3]);
1277 default: return INVALID_IDX(idx);
1278 }
1279 }
REG_MDP5_DSPP(uint32_t i0)1280 static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
1281
REG_MDP5_DSPP_OP_MODE(uint32_t i0)1282 static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
1283 #define MDP5_DSPP_OP_MODE_IGC_LUT_EN 0x00000001
1284 #define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK 0x0000000e
1285 #define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT 1
MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val)1286 static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val)
1287 {
1288 return ((val) << MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT) & MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK;
1289 }
1290 #define MDP5_DSPP_OP_MODE_PCC_EN 0x00000010
1291 #define MDP5_DSPP_OP_MODE_DITHER_EN 0x00000100
1292 #define MDP5_DSPP_OP_MODE_HIST_EN 0x00010000
1293 #define MDP5_DSPP_OP_MODE_AUTO_CLEAR 0x00020000
1294 #define MDP5_DSPP_OP_MODE_HIST_LUT_EN 0x00080000
1295 #define MDP5_DSPP_OP_MODE_PA_EN 0x00100000
1296 #define MDP5_DSPP_OP_MODE_GAMUT_EN 0x00800000
1297 #define MDP5_DSPP_OP_MODE_GAMUT_ORDER 0x01000000
1298
REG_MDP5_DSPP_PCC_BASE(uint32_t i0)1299 static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0); }
1300
REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0)1301 static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(i0); }
1302
REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0)1303 static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP(i0); }
1304
REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0)1305 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP(i0); }
1306
REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0)1307 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP(i0); }
1308
REG_MDP5_DSPP_PA_BASE(uint32_t i0)1309 static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); }
1310
REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0)1311 static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0); }
1312
REG_MDP5_DSPP_GC_BASE(uint32_t i0)1313 static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); }
1314
__offset_PP(uint32_t idx)1315 static inline uint32_t __offset_PP(uint32_t idx)
1316 {
1317 switch (idx) {
1318 case 0: return (mdp5_cfg->pp.base[0]);
1319 case 1: return (mdp5_cfg->pp.base[1]);
1320 case 2: return (mdp5_cfg->pp.base[2]);
1321 case 3: return (mdp5_cfg->pp.base[3]);
1322 default: return INVALID_IDX(idx);
1323 }
1324 }
REG_MDP5_PP(uint32_t i0)1325 static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }
1326
REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0)1327 static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }
1328
REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0)1329 static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { return 0x00000004 + __offset_PP(i0); }
1330 #define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK 0x0007ffff
1331 #define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT 0
MDP5_PP_SYNC_CONFIG_VSYNC_COUNT(uint32_t val)1332 static inline uint32_t MDP5_PP_SYNC_CONFIG_VSYNC_COUNT(uint32_t val)
1333 {
1334 return ((val) << MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT) & MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK;
1335 }
1336 #define MDP5_PP_SYNC_CONFIG_VSYNC_COUNTER_EN 0x00080000
1337 #define MDP5_PP_SYNC_CONFIG_VSYNC_IN_EN 0x00100000
1338
REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0)1339 static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { return 0x00000008 + __offset_PP(i0); }
1340
REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0)1341 static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { return 0x0000000c + __offset_PP(i0); }
1342 #define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK 0x0000ffff
1343 #define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT 0
MDP5_PP_SYNC_WRCOUNT_LINE_COUNT(uint32_t val)1344 static inline uint32_t MDP5_PP_SYNC_WRCOUNT_LINE_COUNT(uint32_t val)
1345 {
1346 return ((val) << MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK;
1347 }
1348 #define MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK 0xffff0000
1349 #define MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__SHIFT 16
MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT(uint32_t val)1350 static inline uint32_t MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT(uint32_t val)
1351 {
1352 return ((val) << MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK;
1353 }
1354
REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0)1355 static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { return 0x00000010 + __offset_PP(i0); }
1356
REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0)1357 static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { return 0x00000014 + __offset_PP(i0); }
1358 #define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK 0x0000ffff
1359 #define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT 0
MDP5_PP_INT_COUNT_VAL_LINE_COUNT(uint32_t val)1360 static inline uint32_t MDP5_PP_INT_COUNT_VAL_LINE_COUNT(uint32_t val)
1361 {
1362 return ((val) << MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK;
1363 }
1364 #define MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK 0xffff0000
1365 #define MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__SHIFT 16
MDP5_PP_INT_COUNT_VAL_FRAME_COUNT(uint32_t val)1366 static inline uint32_t MDP5_PP_INT_COUNT_VAL_FRAME_COUNT(uint32_t val)
1367 {
1368 return ((val) << MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK;
1369 }
1370
REG_MDP5_PP_SYNC_THRESH(uint32_t i0)1371 static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { return 0x00000018 + __offset_PP(i0); }
1372 #define MDP5_PP_SYNC_THRESH_START__MASK 0x0000ffff
1373 #define MDP5_PP_SYNC_THRESH_START__SHIFT 0
MDP5_PP_SYNC_THRESH_START(uint32_t val)1374 static inline uint32_t MDP5_PP_SYNC_THRESH_START(uint32_t val)
1375 {
1376 return ((val) << MDP5_PP_SYNC_THRESH_START__SHIFT) & MDP5_PP_SYNC_THRESH_START__MASK;
1377 }
1378 #define MDP5_PP_SYNC_THRESH_CONTINUE__MASK 0xffff0000
1379 #define MDP5_PP_SYNC_THRESH_CONTINUE__SHIFT 16
MDP5_PP_SYNC_THRESH_CONTINUE(uint32_t val)1380 static inline uint32_t MDP5_PP_SYNC_THRESH_CONTINUE(uint32_t val)
1381 {
1382 return ((val) << MDP5_PP_SYNC_THRESH_CONTINUE__SHIFT) & MDP5_PP_SYNC_THRESH_CONTINUE__MASK;
1383 }
1384
REG_MDP5_PP_START_POS(uint32_t i0)1385 static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { return 0x0000001c + __offset_PP(i0); }
1386
REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0)1387 static inline uint32_t REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) { return 0x00000020 + __offset_PP(i0); }
1388
REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0)1389 static inline uint32_t REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) { return 0x00000024 + __offset_PP(i0); }
1390
REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0)1391 static inline uint32_t REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) { return 0x00000028 + __offset_PP(i0); }
1392
REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0)1393 static inline uint32_t REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) { return 0x0000002c + __offset_PP(i0); }
1394
REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0)1395 static inline uint32_t REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) { return 0x00000030 + __offset_PP(i0); }
1396
REG_MDP5_PP_FBC_MODE(uint32_t i0)1397 static inline uint32_t REG_MDP5_PP_FBC_MODE(uint32_t i0) { return 0x00000034 + __offset_PP(i0); }
1398
REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0)1399 static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x00000038 + __offset_PP(i0); }
1400
REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0)1401 static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0); }
1402
__offset_WB(uint32_t idx)1403 static inline uint32_t __offset_WB(uint32_t idx)
1404 {
1405 switch (idx) {
1406 #if 0 /* TEMPORARY until patch that adds wb.base[] is merged */
1407 case 0: return (mdp5_cfg->wb.base[0]);
1408 case 1: return (mdp5_cfg->wb.base[1]);
1409 case 2: return (mdp5_cfg->wb.base[2]);
1410 case 3: return (mdp5_cfg->wb.base[3]);
1411 case 4: return (mdp5_cfg->wb.base[4]);
1412 #endif
1413 default: return INVALID_IDX(idx);
1414 }
1415 }
REG_MDP5_WB(uint32_t i0)1416 static inline uint32_t REG_MDP5_WB(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }
1417
REG_MDP5_WB_DST_FORMAT(uint32_t i0)1418 static inline uint32_t REG_MDP5_WB_DST_FORMAT(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }
1419 #define MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK 0x00000003
1420 #define MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT 0
MDP5_WB_DST_FORMAT_DSTC0_OUT(uint32_t val)1421 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC0_OUT(uint32_t val)
1422 {
1423 return ((val) << MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK;
1424 }
1425 #define MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK 0x0000000c
1426 #define MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT 2
MDP5_WB_DST_FORMAT_DSTC1_OUT(uint32_t val)1427 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC1_OUT(uint32_t val)
1428 {
1429 return ((val) << MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK;
1430 }
1431 #define MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK 0x00000030
1432 #define MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT 4
MDP5_WB_DST_FORMAT_DSTC2_OUT(uint32_t val)1433 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC2_OUT(uint32_t val)
1434 {
1435 return ((val) << MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK;
1436 }
1437 #define MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK 0x000000c0
1438 #define MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT 6
MDP5_WB_DST_FORMAT_DSTC3_OUT(uint32_t val)1439 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC3_OUT(uint32_t val)
1440 {
1441 return ((val) << MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK;
1442 }
1443 #define MDP5_WB_DST_FORMAT_DSTC3_EN 0x00000100
1444 #define MDP5_WB_DST_FORMAT_DST_BPP__MASK 0x00000600
1445 #define MDP5_WB_DST_FORMAT_DST_BPP__SHIFT 9
MDP5_WB_DST_FORMAT_DST_BPP(uint32_t val)1446 static inline uint32_t MDP5_WB_DST_FORMAT_DST_BPP(uint32_t val)
1447 {
1448 return ((val) << MDP5_WB_DST_FORMAT_DST_BPP__SHIFT) & MDP5_WB_DST_FORMAT_DST_BPP__MASK;
1449 }
1450 #define MDP5_WB_DST_FORMAT_PACK_COUNT__MASK 0x00003000
1451 #define MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT 12
MDP5_WB_DST_FORMAT_PACK_COUNT(uint32_t val)1452 static inline uint32_t MDP5_WB_DST_FORMAT_PACK_COUNT(uint32_t val)
1453 {
1454 return ((val) << MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT) & MDP5_WB_DST_FORMAT_PACK_COUNT__MASK;
1455 }
1456 #define MDP5_WB_DST_FORMAT_DST_ALPHA_X 0x00004000
1457 #define MDP5_WB_DST_FORMAT_PACK_TIGHT 0x00020000
1458 #define MDP5_WB_DST_FORMAT_PACK_ALIGN_MSB 0x00040000
1459 #define MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK 0x00180000
1460 #define MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT 19
MDP5_WB_DST_FORMAT_WRITE_PLANES(uint32_t val)1461 static inline uint32_t MDP5_WB_DST_FORMAT_WRITE_PLANES(uint32_t val)
1462 {
1463 return ((val) << MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT) & MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK;
1464 }
1465 #define MDP5_WB_DST_FORMAT_DST_DITHER_EN 0x00400000
1466 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK 0x03800000
1467 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT 23
MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP(uint32_t val)1468 static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP(uint32_t val)
1469 {
1470 return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK;
1471 }
1472 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK 0x3c000000
1473 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT 26
MDP5_WB_DST_FORMAT_DST_CHROMA_SITE(uint32_t val)1474 static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SITE(uint32_t val)
1475 {
1476 return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK;
1477 }
1478 #define MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK 0xc0000000
1479 #define MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT 30
MDP5_WB_DST_FORMAT_FRAME_FORMAT(uint32_t val)1480 static inline uint32_t MDP5_WB_DST_FORMAT_FRAME_FORMAT(uint32_t val)
1481 {
1482 return ((val) << MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT) & MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK;
1483 }
1484
REG_MDP5_WB_DST_OP_MODE(uint32_t i0)1485 static inline uint32_t REG_MDP5_WB_DST_OP_MODE(uint32_t i0) { return 0x00000004 + __offset_WB(i0); }
1486 #define MDP5_WB_DST_OP_MODE_BWC_ENC_EN 0x00000001
1487 #define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK 0x00000006
1488 #define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT 1
MDP5_WB_DST_OP_MODE_BWC_ENC_OP(uint32_t val)1489 static inline uint32_t MDP5_WB_DST_OP_MODE_BWC_ENC_OP(uint32_t val)
1490 {
1491 return ((val) << MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT) & MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK;
1492 }
1493 #define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK 0x00000010
1494 #define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT 4
MDP5_WB_DST_OP_MODE_BLOCK_SIZE(uint32_t val)1495 static inline uint32_t MDP5_WB_DST_OP_MODE_BLOCK_SIZE(uint32_t val)
1496 {
1497 return ((val) << MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT) & MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK;
1498 }
1499 #define MDP5_WB_DST_OP_MODE_ROT_MODE__MASK 0x00000020
1500 #define MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT 5
MDP5_WB_DST_OP_MODE_ROT_MODE(uint32_t val)1501 static inline uint32_t MDP5_WB_DST_OP_MODE_ROT_MODE(uint32_t val)
1502 {
1503 return ((val) << MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT) & MDP5_WB_DST_OP_MODE_ROT_MODE__MASK;
1504 }
1505 #define MDP5_WB_DST_OP_MODE_ROT_EN 0x00000040
1506 #define MDP5_WB_DST_OP_MODE_CSC_EN 0x00000100
1507 #define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK 0x00000200
1508 #define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT 9
MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT(uint32_t val)1509 static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT(uint32_t val)
1510 {
1511 return ((val) << MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK;
1512 }
1513 #define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK 0x00000400
1514 #define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT 10
MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT(uint32_t val)1515 static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT(uint32_t val)
1516 {
1517 return ((val) << MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK;
1518 }
1519 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_EN 0x00000800
1520 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK 0x00001000
1521 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT 12
MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT(uint32_t val)1522 static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT(uint32_t val)
1523 {
1524 return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK;
1525 }
1526 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK 0x00002000
1527 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT 13
MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD(uint32_t val)1528 static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD(uint32_t val)
1529 {
1530 return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK;
1531 }
1532 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK 0x00004000
1533 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT 14
MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD(uint32_t val)1534 static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD(uint32_t val)
1535 {
1536 return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK;
1537 }
1538
REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0)1539 static inline uint32_t REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) { return 0x00000008 + __offset_WB(i0); }
1540 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK 0x00000003
1541 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT 0
MDP5_WB_DST_PACK_PATTERN_ELEMENT0(uint32_t val)1542 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT0(uint32_t val)
1543 {
1544 return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK;
1545 }
1546 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK 0x00000300
1547 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT 8
MDP5_WB_DST_PACK_PATTERN_ELEMENT1(uint32_t val)1548 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT1(uint32_t val)
1549 {
1550 return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK;
1551 }
1552 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK 0x00030000
1553 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT 16
MDP5_WB_DST_PACK_PATTERN_ELEMENT2(uint32_t val)1554 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT2(uint32_t val)
1555 {
1556 return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK;
1557 }
1558 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK 0x03000000
1559 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT 24
MDP5_WB_DST_PACK_PATTERN_ELEMENT3(uint32_t val)1560 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT3(uint32_t val)
1561 {
1562 return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK;
1563 }
1564
REG_MDP5_WB_DST0_ADDR(uint32_t i0)1565 static inline uint32_t REG_MDP5_WB_DST0_ADDR(uint32_t i0) { return 0x0000000c + __offset_WB(i0); }
1566
REG_MDP5_WB_DST1_ADDR(uint32_t i0)1567 static inline uint32_t REG_MDP5_WB_DST1_ADDR(uint32_t i0) { return 0x00000010 + __offset_WB(i0); }
1568
REG_MDP5_WB_DST2_ADDR(uint32_t i0)1569 static inline uint32_t REG_MDP5_WB_DST2_ADDR(uint32_t i0) { return 0x00000014 + __offset_WB(i0); }
1570
REG_MDP5_WB_DST3_ADDR(uint32_t i0)1571 static inline uint32_t REG_MDP5_WB_DST3_ADDR(uint32_t i0) { return 0x00000018 + __offset_WB(i0); }
1572
REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0)1573 static inline uint32_t REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) { return 0x0000001c + __offset_WB(i0); }
1574 #define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK 0x0000ffff
1575 #define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT 0
MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE(uint32_t val)1576 static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE(uint32_t val)
1577 {
1578 return ((val) << MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK;
1579 }
1580 #define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK 0xffff0000
1581 #define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT 16
MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE(uint32_t val)1582 static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE(uint32_t val)
1583 {
1584 return ((val) << MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK;
1585 }
1586
REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0)1587 static inline uint32_t REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) { return 0x00000020 + __offset_WB(i0); }
1588 #define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK 0x0000ffff
1589 #define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT 0
MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE(uint32_t val)1590 static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE(uint32_t val)
1591 {
1592 return ((val) << MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK;
1593 }
1594 #define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK 0xffff0000
1595 #define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT 16
MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE(uint32_t val)1596 static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE(uint32_t val)
1597 {
1598 return ((val) << MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK;
1599 }
1600
REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0)1601 static inline uint32_t REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) { return 0x00000024 + __offset_WB(i0); }
1602
REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0)1603 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) { return 0x00000030 + __offset_WB(i0); }
1604
REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0)1605 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) { return 0x00000034 + __offset_WB(i0); }
1606
REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0)1607 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) { return 0x00000038 + __offset_WB(i0); }
1608
REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0)1609 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) { return 0x0000003c + __offset_WB(i0); }
1610
REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0)1611 static inline uint32_t REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) { return 0x00000048 + __offset_WB(i0); }
1612
REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0)1613 static inline uint32_t REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) { return 0x00000050 + __offset_WB(i0); }
1614
REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0)1615 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) { return 0x00000060 + __offset_WB(i0); }
1616
REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0)1617 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) { return 0x00000064 + __offset_WB(i0); }
1618
REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0)1619 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) { return 0x00000068 + __offset_WB(i0); }
1620
REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0)1621 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) { return 0x0000006c + __offset_WB(i0); }
1622
REG_MDP5_WB_OUT_SIZE(uint32_t i0)1623 static inline uint32_t REG_MDP5_WB_OUT_SIZE(uint32_t i0) { return 0x00000074 + __offset_WB(i0); }
1624 #define MDP5_WB_OUT_SIZE_DST_W__MASK 0x0000ffff
1625 #define MDP5_WB_OUT_SIZE_DST_W__SHIFT 0
MDP5_WB_OUT_SIZE_DST_W(uint32_t val)1626 static inline uint32_t MDP5_WB_OUT_SIZE_DST_W(uint32_t val)
1627 {
1628 return ((val) << MDP5_WB_OUT_SIZE_DST_W__SHIFT) & MDP5_WB_OUT_SIZE_DST_W__MASK;
1629 }
1630 #define MDP5_WB_OUT_SIZE_DST_H__MASK 0xffff0000
1631 #define MDP5_WB_OUT_SIZE_DST_H__SHIFT 16
MDP5_WB_OUT_SIZE_DST_H(uint32_t val)1632 static inline uint32_t MDP5_WB_OUT_SIZE_DST_H(uint32_t val)
1633 {
1634 return ((val) << MDP5_WB_OUT_SIZE_DST_H__SHIFT) & MDP5_WB_OUT_SIZE_DST_H__MASK;
1635 }
1636
REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0)1637 static inline uint32_t REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) { return 0x00000078 + __offset_WB(i0); }
1638
REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0)1639 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) { return 0x00000260 + __offset_WB(i0); }
1640 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK 0x00001fff
1641 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT 0
MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11(uint32_t val)1642 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11(uint32_t val)
1643 {
1644 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK;
1645 }
1646 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK 0x1fff0000
1647 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT 16
MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12(uint32_t val)1648 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12(uint32_t val)
1649 {
1650 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK;
1651 }
1652
REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0)1653 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) { return 0x00000264 + __offset_WB(i0); }
1654 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK 0x00001fff
1655 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT 0
MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13(uint32_t val)1656 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13(uint32_t val)
1657 {
1658 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK;
1659 }
1660 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK 0x1fff0000
1661 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT 16
MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21(uint32_t val)1662 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21(uint32_t val)
1663 {
1664 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK;
1665 }
1666
REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0)1667 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) { return 0x00000268 + __offset_WB(i0); }
1668 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK 0x00001fff
1669 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT 0
MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22(uint32_t val)1670 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22(uint32_t val)
1671 {
1672 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK;
1673 }
1674 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK 0x1fff0000
1675 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT 16
MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23(uint32_t val)1676 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23(uint32_t val)
1677 {
1678 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK;
1679 }
1680
REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0)1681 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) { return 0x0000026c + __offset_WB(i0); }
1682 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK 0x00001fff
1683 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT 0
MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31(uint32_t val)1684 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31(uint32_t val)
1685 {
1686 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK;
1687 }
1688 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK 0x1fff0000
1689 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT 16
MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32(uint32_t val)1690 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32(uint32_t val)
1691 {
1692 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK;
1693 }
1694
REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0)1695 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) { return 0x00000270 + __offset_WB(i0); }
1696 #define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK 0x00001fff
1697 #define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT 0
MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33(uint32_t val)1698 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33(uint32_t val)
1699 {
1700 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK;
1701 }
1702
REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0,uint32_t i1)1703 static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
1704
REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0,uint32_t i1)1705 static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
1706 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK 0x000000ff
1707 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT 0
MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH(uint32_t val)1708 static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH(uint32_t val)
1709 {
1710 return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK;
1711 }
1712 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK 0x0000ff00
1713 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT 8
MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW(uint32_t val)1714 static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW(uint32_t val)
1715 {
1716 return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK;
1717 }
1718
REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0,uint32_t i1)1719 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
1720
REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0,uint32_t i1)1721 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
1722 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK 0x000000ff
1723 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT 0
MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH(uint32_t val)1724 static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH(uint32_t val)
1725 {
1726 return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK;
1727 }
1728 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK 0x0000ff00
1729 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT 8
MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW(uint32_t val)1730 static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW(uint32_t val)
1731 {
1732 return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK;
1733 }
1734
REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0,uint32_t i1)1735 static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
1736
REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0,uint32_t i1)1737 static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
1738 #define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK 0x000001ff
1739 #define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT 0
MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE(uint32_t val)1740 static inline uint32_t MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE(uint32_t val)
1741 {
1742 return ((val) << MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK;
1743 }
1744
REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0,uint32_t i1)1745 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
1746
REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0,uint32_t i1)1747 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
1748 #define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK 0x000001ff
1749 #define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT 0
MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE(uint32_t val)1750 static inline uint32_t MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE(uint32_t val)
1751 {
1752 return ((val) << MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK;
1753 }
1754
__offset_INTF(uint32_t idx)1755 static inline uint32_t __offset_INTF(uint32_t idx)
1756 {
1757 switch (idx) {
1758 case 0: return (mdp5_cfg->intf.base[0]);
1759 case 1: return (mdp5_cfg->intf.base[1]);
1760 case 2: return (mdp5_cfg->intf.base[2]);
1761 case 3: return (mdp5_cfg->intf.base[3]);
1762 case 4: return (mdp5_cfg->intf.base[4]);
1763 default: return INVALID_IDX(idx);
1764 }
1765 }
REG_MDP5_INTF(uint32_t i0)1766 static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
1767
REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0)1768 static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
1769
REG_MDP5_INTF_CONFIG(uint32_t i0)1770 static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); }
1771
REG_MDP5_INTF_HSYNC_CTL(uint32_t i0)1772 static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0); }
1773 #define MDP5_INTF_HSYNC_CTL_PULSEW__MASK 0x0000ffff
1774 #define MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT 0
MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val)1775 static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val)
1776 {
1777 return ((val) << MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT) & MDP5_INTF_HSYNC_CTL_PULSEW__MASK;
1778 }
1779 #define MDP5_INTF_HSYNC_CTL_PERIOD__MASK 0xffff0000
1780 #define MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT 16
MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val)1781 static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val)
1782 {
1783 return ((val) << MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT) & MDP5_INTF_HSYNC_CTL_PERIOD__MASK;
1784 }
1785
REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0)1786 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0); }
1787
REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0)1788 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0); }
1789
REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0)1790 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(i0); }
1791
REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0)1792 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(i0); }
1793
REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0)1794 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i0); }
1795
REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0)1796 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_INTF(i0); }
1797
REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0)1798 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_INTF(i0); }
1799
REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0)1800 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_INTF(i0); }
1801
REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0)1802 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_INTF(i0); }
1803 #define MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK 0x7fffffff
1804 #define MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT 0
MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val)1805 static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val)
1806 {
1807 return ((val) << MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK;
1808 }
1809 #define MDP5_INTF_ACTIVE_VSTART_F0_ACTIVE_V_ENABLE 0x80000000
1810
REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0)1811 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_INTF(i0); }
1812 #define MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK 0x7fffffff
1813 #define MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT 0
MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val)1814 static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val)
1815 {
1816 return ((val) << MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK;
1817 }
1818
REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0)1819 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INTF(i0); }
1820
REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0)1821 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INTF(i0); }
1822
REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0)1823 static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(i0); }
1824 #define MDP5_INTF_DISPLAY_HCTL_START__MASK 0x0000ffff
1825 #define MDP5_INTF_DISPLAY_HCTL_START__SHIFT 0
MDP5_INTF_DISPLAY_HCTL_START(uint32_t val)1826 static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val)
1827 {
1828 return ((val) << MDP5_INTF_DISPLAY_HCTL_START__SHIFT) & MDP5_INTF_DISPLAY_HCTL_START__MASK;
1829 }
1830 #define MDP5_INTF_DISPLAY_HCTL_END__MASK 0xffff0000
1831 #define MDP5_INTF_DISPLAY_HCTL_END__SHIFT 16
MDP5_INTF_DISPLAY_HCTL_END(uint32_t val)1832 static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val)
1833 {
1834 return ((val) << MDP5_INTF_DISPLAY_HCTL_END__SHIFT) & MDP5_INTF_DISPLAY_HCTL_END__MASK;
1835 }
1836
REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0)1837 static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i0); }
1838 #define MDP5_INTF_ACTIVE_HCTL_START__MASK 0x00007fff
1839 #define MDP5_INTF_ACTIVE_HCTL_START__SHIFT 0
MDP5_INTF_ACTIVE_HCTL_START(uint32_t val)1840 static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val)
1841 {
1842 return ((val) << MDP5_INTF_ACTIVE_HCTL_START__SHIFT) & MDP5_INTF_ACTIVE_HCTL_START__MASK;
1843 }
1844 #define MDP5_INTF_ACTIVE_HCTL_END__MASK 0x7fff0000
1845 #define MDP5_INTF_ACTIVE_HCTL_END__SHIFT 16
MDP5_INTF_ACTIVE_HCTL_END(uint32_t val)1846 static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val)
1847 {
1848 return ((val) << MDP5_INTF_ACTIVE_HCTL_END__SHIFT) & MDP5_INTF_ACTIVE_HCTL_END__MASK;
1849 }
1850 #define MDP5_INTF_ACTIVE_HCTL_ACTIVE_H_ENABLE 0x80000000
1851
REG_MDP5_INTF_BORDER_COLOR(uint32_t i0)1852 static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(i0); }
1853
REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0)1854 static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_INTF(i0); }
1855
REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0)1856 static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0); }
1857
REG_MDP5_INTF_POLARITY_CTL(uint32_t i0)1858 static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(i0); }
1859 #define MDP5_INTF_POLARITY_CTL_HSYNC_LOW 0x00000001
1860 #define MDP5_INTF_POLARITY_CTL_VSYNC_LOW 0x00000002
1861 #define MDP5_INTF_POLARITY_CTL_DATA_EN_LOW 0x00000004
1862
REG_MDP5_INTF_TEST_CTL(uint32_t i0)1863 static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0); }
1864
REG_MDP5_INTF_TP_COLOR0(uint32_t i0)1865 static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0); }
1866
REG_MDP5_INTF_TP_COLOR1(uint32_t i0)1867 static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0); }
1868
REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0)1869 static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __offset_INTF(i0); }
1870
REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0)1871 static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(i0); }
1872
REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0)1873 static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offset_INTF(i0); }
1874
REG_MDP5_INTF_FRAME_COUNT(uint32_t i0)1875 static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i0); }
1876
REG_MDP5_INTF_LINE_COUNT(uint32_t i0)1877 static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0); }
1878
REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0)1879 static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_INTF(i0); }
1880
REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0)1881 static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __offset_INTF(i0); }
1882
REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0)1883 static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offset_INTF(i0); }
1884
REG_MDP5_INTF_TPG_ENABLE(uint32_t i0)1885 static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0); }
1886
REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0)1887 static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_INTF(i0); }
1888
REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0)1889 static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_INTF(i0); }
1890
REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0)1891 static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offset_INTF(i0); }
1892
REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0)1893 static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF(i0); }
1894
REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0)1895 static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_INTF(i0); }
1896
REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0)1897 static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 + __offset_INTF(i0); }
1898
REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0)1899 static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_INTF(i0); }
1900
__offset_AD(uint32_t idx)1901 static inline uint32_t __offset_AD(uint32_t idx)
1902 {
1903 switch (idx) {
1904 case 0: return (mdp5_cfg->ad.base[0]);
1905 case 1: return (mdp5_cfg->ad.base[1]);
1906 default: return INVALID_IDX(idx);
1907 }
1908 }
REG_MDP5_AD(uint32_t i0)1909 static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
1910
REG_MDP5_AD_BYPASS(uint32_t i0)1911 static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
1912
REG_MDP5_AD_CTRL_0(uint32_t i0)1913 static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); }
1914
REG_MDP5_AD_CTRL_1(uint32_t i0)1915 static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); }
1916
REG_MDP5_AD_FRAME_SIZE(uint32_t i0)1917 static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); }
1918
REG_MDP5_AD_CON_CTRL_0(uint32_t i0)1919 static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); }
1920
REG_MDP5_AD_CON_CTRL_1(uint32_t i0)1921 static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); }
1922
REG_MDP5_AD_STR_MAN(uint32_t i0)1923 static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); }
1924
REG_MDP5_AD_VAR(uint32_t i0)1925 static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); }
1926
REG_MDP5_AD_DITH(uint32_t i0)1927 static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); }
1928
REG_MDP5_AD_DITH_CTRL(uint32_t i0)1929 static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); }
1930
REG_MDP5_AD_AMP_LIM(uint32_t i0)1931 static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); }
1932
REG_MDP5_AD_SLOPE(uint32_t i0)1933 static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); }
1934
REG_MDP5_AD_BW_LVL(uint32_t i0)1935 static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); }
1936
REG_MDP5_AD_LOGO_POS(uint32_t i0)1937 static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); }
1938
REG_MDP5_AD_LUT_FI(uint32_t i0)1939 static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); }
1940
REG_MDP5_AD_LUT_CC(uint32_t i0)1941 static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); }
1942
REG_MDP5_AD_STR_LIM(uint32_t i0)1943 static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); }
1944
REG_MDP5_AD_CALIB_AB(uint32_t i0)1945 static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); }
1946
REG_MDP5_AD_CALIB_CD(uint32_t i0)1947 static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); }
1948
REG_MDP5_AD_MODE_SEL(uint32_t i0)1949 static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); }
1950
REG_MDP5_AD_TFILT_CTRL(uint32_t i0)1951 static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); }
1952
REG_MDP5_AD_BL_MINMAX(uint32_t i0)1953 static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); }
1954
REG_MDP5_AD_BL(uint32_t i0)1955 static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); }
1956
REG_MDP5_AD_BL_MAX(uint32_t i0)1957 static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); }
1958
REG_MDP5_AD_AL(uint32_t i0)1959 static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); }
1960
REG_MDP5_AD_AL_MIN(uint32_t i0)1961 static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); }
1962
REG_MDP5_AD_AL_FILT(uint32_t i0)1963 static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); }
1964
REG_MDP5_AD_CFG_BUF(uint32_t i0)1965 static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); }
1966
REG_MDP5_AD_LUT_AL(uint32_t i0)1967 static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); }
1968
REG_MDP5_AD_TARG_STR(uint32_t i0)1969 static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); }
1970
REG_MDP5_AD_START_CALC(uint32_t i0)1971 static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); }
1972
REG_MDP5_AD_STR_OUT(uint32_t i0)1973 static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); }
1974
REG_MDP5_AD_BL_OUT(uint32_t i0)1975 static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); }
1976
REG_MDP5_AD_CALC_DONE(uint32_t i0)1977 static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); }
1978
1979
1980 #endif /* MDP5_XML */
1981