1 /* 2 * Copyright 2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef DDR_REG_H 9 #define DDR_REG_H 10 11 #define SDRAM_CS_CONFIG_EN 0x80000000 12 13 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration 14 */ 15 #define SDRAM_CFG_MEM_EN 0x80000000 16 #define SDRAM_CFG_SREN 0x40000000 17 #define SDRAM_CFG_ECC_EN 0x20000000 18 #define SDRAM_CFG_RD_EN 0x10000000 19 #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 20 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 21 #define SDRAM_CFG_DYN_PWR 0x00200000 22 #define SDRAM_CFG_DBW_MASK 0x00180000 23 #define SDRAM_CFG_DBW_SHIFT 19 24 #define SDRAM_CFG_32_BW 0x00080000 25 #define SDRAM_CFG_16_BW 0x00100000 26 #define SDRAM_CFG_8_BW 0x00180000 27 #define SDRAM_CFG_8_BE 0x00040000 28 #define SDRAM_CFG_2T_EN 0x00008000 29 #define SDRAM_CFG_MEM_HLT 0x00000002 30 #define SDRAM_CFG_BI 0x00000001 31 32 #define SDRAM_CFG2_FRC_SR 0x80000000 33 #define SDRAM_CFG2_FRC_SR_CLEAR ~(SDRAM_CFG2_FRC_SR) 34 #define SDRAM_CFG2_D_INIT 0x00000010 35 #define SDRAM_CFG2_AP_EN 0x00000020 36 #define SDRAM_CFG2_ODT_ONLY_READ 2 37 38 #define SDRAM_CFG3_DDRC_RST 0x80000000 39 40 #define SDRAM_INTERVAL_REFINT 0xFFFF0000 41 #define SDRAM_INTERVAL_REFINT_CLEAR ~(SDRAM_INTERVAL_REFINT) 42 #define SDRAM_INTERVAL_BSTOPRE 0x3FFF 43 44 /* DDR_MD_CNTL */ 45 #define MD_CNTL_MD_EN 0x80000000 46 #define MD_CNTL_CS_SEL(x) (((x) & 0x7) << 28) 47 #define MD_CNTL_MD_SEL(x) (((x) & 0xf) << 24) 48 #define MD_CNTL_CKE(x) (((x) & 0x3) << 20) 49 50 /* DDR_CDR1 */ 51 #define DDR_CDR1_DHC_EN 0x80000000 52 #define DDR_CDR1_ODT_SHIFT 17 53 #define DDR_CDR1_ODT_MASK 0x6 54 #define DDR_CDR2_ODT_MASK 0x1 55 #define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT) 56 #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK) 57 #define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8)) 58 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 59 #define DDR_CDR2_VREF_RANGE_2 0x00000040 60 #define DDR_CDR_ODT_OFF 0x0 61 #define DDR_CDR_ODT_100ohm 0x1 62 #define DDR_CDR_ODT_120OHM 0x2 63 #define DDR_CDR_ODT_80ohm 0x3 64 #define DDR_CDR_ODT_60ohm 0x4 65 #define DDR_CDR_ODT_40ohm 0x5 66 #define DDR_CDR_ODT_50ohm 0x6 67 #define DDR_CDR_ODT_30ohm 0x7 68 69 70 /* DDR ERR_DISABLE */ 71 #define DDR_ERR_DISABLE_APED (1 << 8) /* Address parity error disable */ 72 #define DDR_ERR_DISABLE_SBED (1 << 2) /* Address parity error disable */ 73 #define DDR_ERR_DISABLE_MBED (1 << 3) /* Address parity error disable */ 74 75 /* Mode Registers */ 76 #define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */ 77 #define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */ 78 79 /* DDR DSR2 register */ 80 #define DDR_DSR_2_PHY_INIT_CMPLT 0x4 81 82 /* SDRAM TIMING_CFG_10 register */ 83 #define DDR_TIMING_CFG_10_T_STAB 0x7FFF 84 85 /* DEBUG 2 register */ 86 #define DDR_DBG_2_MEM_IDLE 0x00000002 87 88 /* DEBUG 26 register */ 89 #define DDR_DEBUG_26_BIT_6 (0x1 << 6) 90 #define DDR_DEBUG_26_BIT_7 (0x1 << 7) 91 #define DDR_DEBUG_26_BIT_12 (0x1 << 12) 92 #define DDR_DEBUG_26_BIT_13 (0x1 << 13) 93 #define DDR_DEBUG_26_BIT_14 (0x1 << 14) 94 #define DDR_DEBUG_26_BIT_15 (0x1 << 15) 95 #define DDR_DEBUG_26_BIT_16 (0x1 << 16) 96 #define DDR_DEBUG_26_BIT_17 (0x1 << 17) 97 #define DDR_DEBUG_26_BIT_18 (0x1 << 18) 98 #define DDR_DEBUG_26_BIT_19 (0x1 << 19) 99 #define DDR_DEBUG_26_BIT_24 (0x1 << 24) 100 #define DDR_DEBUG_26_BIT_25 (0x1 << 25) 101 102 #define DDR_DEBUG_26_BIT_24_CLEAR ~(DDR_DEBUG_26_BIT_24) 103 104 /* DEBUG_29 register */ 105 #define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */ 106 107 #define DDR_INIT_ADDR_EXT_UIA (1 << 31) 108 109 #endif /* DDR_REG_H */ 110