1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Copyright (C) 2016 BayLibre, SAS
4  * Author: Neil Armstrong <narmstrong@baylibre.com>
5  */
6 
7 /* Video Clock */
8 
9 #ifndef __MESON_VCLK_H
10 #define __MESON_VCLK_H
11 
12 #include <drm/drm_modes.h>
13 
14 struct meson_drm;
15 
16 enum {
17 	MESON_VCLK_TARGET_CVBS = 0,
18 	MESON_VCLK_TARGET_HDMI = 1,
19 	MESON_VCLK_TARGET_DMT = 2,
20 };
21 
22 /* 27MHz is the CVBS Pixel Clock */
23 #define MESON_VCLK_CVBS			27000
24 
25 enum drm_mode_status
26 meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq);
27 enum drm_mode_status
28 meson_vclk_vic_supported_freq(struct meson_drm *priv, unsigned int phy_freq,
29 			      unsigned int vclk_freq);
30 
31 void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
32 		      unsigned int phy_freq, unsigned int vclk_freq,
33 		      unsigned int venc_freq, unsigned int dac_freq,
34 		      bool hdmi_use_enci);
35 
36 #endif /* __MESON_VCLK_H */
37