1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Taken from the linux kernel file of the same name 4 * 5 * (C) Copyright 2012 6 * Graeme Russ, <graeme.russ@gmail.com> 7 */ 8 9 #ifndef _ASM_X86_MSR_INDEX_H 10 #define _ASM_X86_MSR_INDEX_H 11 12 #ifndef __ASSEMBLY__ 13 #include <linux/bitops.h> 14 #endif 15 16 /* CPU model specific register (MSR) numbers */ 17 18 /* x86-64 specific MSRs */ 19 #define MSR_EFER 0xc0000080 /* extended feature register */ 20 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 21 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 22 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 23 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 24 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 25 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 26 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 27 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 28 29 /* EFER bits: */ 30 #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 31 #define _EFER_LME 8 /* Long mode enable */ 32 #define _EFER_LMA 10 /* Long mode active (read-only) */ 33 #define _EFER_NX 11 /* No execute enable */ 34 #define _EFER_SVME 12 /* Enable virtualization */ 35 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 36 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 37 38 #define EFER_SCE (1<<_EFER_SCE) 39 #define EFER_LME (1<<_EFER_LME) 40 #define EFER_LMA (1<<_EFER_LMA) 41 #define EFER_NX (1<<_EFER_NX) 42 #define EFER_SVME (1<<_EFER_SVME) 43 #define EFER_LMSLE (1<<_EFER_LMSLE) 44 #define EFER_FFXSR (1<<_EFER_FFXSR) 45 46 /* Intel MSRs. Some also available on other CPUs */ 47 #define MSR_PIC_MSG_CONTROL 0x2e 48 #define PLATFORM_INFO_SET_TDP (1 << 29) 49 50 #define MSR_MTRR_CAP_MSR 0x0fe 51 #define MSR_MTRR_CAP_SMRR (1 << 11) 52 #define MSR_MTRR_CAP_WC (1 << 10) 53 #define MSR_MTRR_CAP_FIX (1 << 8) 54 #define MSR_MTRR_CAP_VCNT 0xff 55 56 #define MSR_IA32_PERFCTR0 0x000000c1 57 #define MSR_IA32_PERFCTR1 0x000000c2 58 #define MSR_FSB_FREQ 0x000000cd 59 #define MSR_NHM_PLATFORM_INFO 0x000000ce 60 61 #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 62 #define NHM_C3_AUTO_DEMOTE (1UL << 25) 63 #define NHM_C1_AUTO_DEMOTE (1UL << 26) 64 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 65 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 66 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 67 68 #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0x000000cd 69 #define MSR_PLATFORM_INFO 0x000000ce 70 #define MSR_PMG_CST_CONFIG_CONTROL 0x000000e2 71 /* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ 72 #define PKG_C_STATE_LIMIT_C2_MASK BIT(1) 73 /* Set MSR_PMG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/ 74 #define CORE_C_STATE_LIMIT_C10_MASK 0x70 75 /* Set MSR_PMG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */ 76 #define IO_MWAIT_REDIRECT_MASK BIT(10) 77 /* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */ 78 #define CST_CFG_LOCK_MASK BIT(15) 79 #define SINGLE_PCTL BIT(11) 80 81 /* ACPI PMIO Offset to C-state register */ 82 #define ACPI_PMIO_CST_REG (ACPI_BASE_ADDRESS + 0x14) 83 84 #define MSR_MTRRcap 0x000000fe 85 #define MSR_IA32_BBL_CR_CTL 0x00000119 86 #define MSR_IA32_BBL_CR_CTL3 0x0000011e 87 #define MSR_POWER_MISC 0x00000120 88 #define FLUSH_DL1_L2 (1 << 8) 89 #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) 90 #define ENABLE_INDP_AUTOCM_MASK (1 << 3) 91 92 #define MSR_EMULATE_PM_TIMER 0x121 93 #define EMULATE_DELAY_OFFSET_VALUE 20 94 #define EMULATE_PM_TMR_EN (1 << 16) 95 #define EMULATE_DELAY_VALUE 0x13 96 97 #define MSR_FEATURE_CONFIG 0x13c 98 #define FEATURE_CONFIG_RESERVED_MASK 0x3ULL 99 #define FEATURE_CONFIG_LOCK (1 << 0) 100 101 #define MSR_IA32_SYSENTER_CS 0x00000174 102 #define MSR_IA32_SYSENTER_ESP 0x00000175 103 #define MSR_IA32_SYSENTER_EIP 0x00000176 104 105 #define MSR_IA32_MCG_CAP 0x00000179 106 #define MSR_IA32_MCG_STATUS 0x0000017a 107 #define MSR_IA32_MCG_CTL 0x0000017b 108 109 #define MSR_FLEX_RATIO 0x194 110 #define FLEX_RATIO_LOCK (1 << 20) 111 #define FLEX_RATIO_EN (1 << 16) 112 /* This is burst mode BIT 38 in IA32_MISC_ENABLE MSR at offset 1A0h */ 113 #define BURST_MODE_DISABLE (1 << 6) 114 115 #define MSR_IA32_MISC_ENABLE 0x000001a0 116 117 /* MISC_ENABLE bits: architectural */ 118 #define MISC_ENABLE_FAST_STRING BIT_ULL(0) 119 #define MISC_ENABLE_TCC BIT_ULL(1) 120 #define MISC_DISABLE_TURBO BIT_ULL(6) 121 #define MISC_ENABLE_EMON BIT_ULL(7) 122 #define MISC_ENABLE_BTS_UNAVAIL BIT_ULL(11) 123 #define MISC_ENABLE_PEBS_UNAVAIL BIT_ULL(12) 124 #define MISC_ENABLE_ENHANCED_SPEEDSTEP BIT_ULL(16) 125 #define MISC_ENABLE_MWAIT BIT_ULL(18) 126 #define MISC_ENABLE_LIMIT_CPUID BIT_ULL(22) 127 #define MISC_ENABLE_XTPR_DISABLE BIT_ULL(23) 128 #define MISC_ENABLE_XD_DISABLE BIT_ULL(34) 129 130 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 131 #define MISC_ENABLE_X87_COMPAT BIT_ULL(2) 132 #define MISC_ENABLE_TM1 BIT_ULL(3) 133 #define MISC_ENABLE_SPLIT_LOCK_DISABLE BIT_ULL(4) 134 #define MISC_ENABLE_L3CACHE_DISABLE BIT_ULL(6) 135 #define MISC_ENABLE_SUPPRESS_LOCK BIT_ULL(8) 136 #define MISC_ENABLE_PREFETCH_DISABLE BIT_ULL(9) 137 #define MISC_ENABLE_FERR BIT_ULL(10) 138 #define MISC_ENABLE_FERR_MULTIPLEX BIT_ULL(10) 139 #define MISC_ENABLE_TM2 BIT_ULL(13) 140 #define MISC_ENABLE_ADJ_PREF_DISABLE BIT_ULL(19) 141 #define MISC_ENABLE_SPEEDSTEP_LOCK BIT_ULL(20) 142 #define MISC_ENABLE_L1D_CONTEXT BIT_ULL(24) 143 #define MISC_ENABLE_DCU_PREF_DISABLE BIT_ULL(37) 144 #define MISC_ENABLE_TURBO_DISABLE BIT_ULL(38) 145 #define MISC_ENABLE_IP_PREF_DISABLE BIT_ULL(39) 146 147 #define MSR_TEMPERATURE_TARGET 0x1a2 148 #define MSR_PREFETCH_CTL 0x1a4 149 #define PREFETCH_L1_DISABLE (1 << 0) 150 #define PREFETCH_L2_DISABLE (1 << 2) 151 #define MSR_OFFCORE_RSP_0 0x000001a6 152 #define MSR_OFFCORE_RSP_1 0x000001a7 153 #define MSR_MISC_PWR_MGMT 0x1aa 154 #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) 155 #define MSR_TURBO_RATIO_LIMIT 0x000001ad 156 157 #define MSR_IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 158 #define ENERGY_POLICY_PERFORMANCE 0 159 #define ENERGY_POLICY_NORMAL 6 160 #define ENERGY_POLICY_POWERSAVE 15 161 162 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 163 164 #define PACKAGE_THERM_STATUS_PROCHOT BIT(0) 165 #define PACKAGE_THERM_STATUS_POWER_LIMIT BIT(10) 166 167 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 168 169 #define PACKAGE_THERM_INT_HIGH_ENABLE BIT(0) 170 #define PACKAGE_THERM_INT_LOW_ENABLE BIT(1) 171 #define PACKAGE_THERM_INT_PLN_ENABLE BIT(24) 172 173 #define MSR_LBR_SELECT 0x000001c8 174 #define MSR_LBR_TOS 0x000001c9 175 #define MSR_IA32_PLATFORM_DCA_CAP 0x1f8 176 #define MSR_POWER_CTL 0x000001fc 177 #define MSR_LBR_NHM_FROM 0x00000680 178 #define MSR_LBR_NHM_TO 0x000006c0 179 #define MSR_LBR_CORE_FROM 0x00000040 180 #define MSR_LBR_CORE_TO 0x00000060 181 182 #define MSR_IA32_PEBS_ENABLE 0x000003f1 183 #define MSR_IA32_DS_AREA 0x00000600 184 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 185 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 186 187 #define MSR_MTRRfix64K_00000 0x00000250 188 #define MSR_MTRRfix16K_80000 0x00000258 189 #define MSR_MTRRfix16K_A0000 0x00000259 190 #define MSR_MTRRfix4K_C0000 0x00000268 191 #define MSR_MTRRfix4K_C8000 0x00000269 192 #define MSR_MTRRfix4K_D0000 0x0000026a 193 #define MSR_MTRRfix4K_D8000 0x0000026b 194 #define MSR_MTRRfix4K_E0000 0x0000026c 195 #define MSR_MTRRfix4K_E8000 0x0000026d 196 #define MSR_MTRRfix4K_F0000 0x0000026e 197 #define MSR_MTRRfix4K_F8000 0x0000026f 198 #define MSR_MTRRdefType 0x000002ff 199 200 #define MSR_IA32_CR_PAT 0x00000277 201 202 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 203 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 204 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 205 #define MSR_IA32_LASTINTFROMIP 0x000001dd 206 #define MSR_IA32_LASTINTTOIP 0x000001de 207 208 /* DEBUGCTLMSR bits (others vary by model): */ 209 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 210 /* single-step on branches */ 211 #define DEBUGCTLMSR_BTF (1UL << 1) 212 #define DEBUGCTLMSR_TR (1UL << 6) 213 #define DEBUGCTLMSR_BTS (1UL << 7) 214 #define DEBUGCTLMSR_BTINT (1UL << 8) 215 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 216 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 217 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 218 219 #define MSR_IA32_POWER_CTL 0x000001fc 220 221 #define MSR_IA32_MC0_CTL 0x00000400 222 #define MSR_IA32_MC0_STATUS 0x00000401 223 #define MSR_IA32_MC0_ADDR 0x00000402 224 #define MSR_IA32_MC0_MISC 0x00000403 225 226 /* C-state Residency Counters */ 227 #define MSR_PKG_C3_RESIDENCY 0x000003f8 228 #define MSR_PKG_C6_RESIDENCY 0x000003f9 229 #define MSR_PKG_C7_RESIDENCY 0x000003fa 230 #define MSR_CORE_C3_RESIDENCY 0x000003fc 231 #define MSR_CORE_C6_RESIDENCY 0x000003fd 232 #define MSR_CORE_C7_RESIDENCY 0x000003fe 233 #define MSR_PKG_C2_RESIDENCY 0x0000060d 234 #define MSR_PKG_C8_RESIDENCY 0x00000630 235 #define MSR_PKG_C9_RESIDENCY 0x00000631 236 #define MSR_PKG_C10_RESIDENCY 0x00000632 237 238 /* Run Time Average Power Limiting (RAPL) Interface */ 239 240 #define MSR_PKG_POWER_SKU_UNIT 0x00000606 241 242 #define MSR_C_STATE_LATENCY_CONTROL_0 0x60a 243 #define MSR_C_STATE_LATENCY_CONTROL_1 0x60b 244 #define MSR_C_STATE_LATENCY_CONTROL_2 0x60c 245 #define MSR_C_STATE_LATENCY_CONTROL_3 0x633 246 #define MSR_C_STATE_LATENCY_CONTROL_4 0x634 247 #define MSR_C_STATE_LATENCY_CONTROL_5 0x635 248 #define IRTL_VALID (1 << 15) 249 #define IRTL_1_NS (0 << 10) 250 #define IRTL_32_NS (1 << 10) 251 #define IRTL_1024_NS (2 << 10) 252 #define IRTL_32768_NS (3 << 10) 253 #define IRTL_1048576_NS (4 << 10) 254 #define IRTL_33554432_NS (5 << 10) 255 #define IRTL_RESPONSE_MASK (0x3ff) 256 257 #define MSR_PKG_POWER_LIMIT 0x00000610 258 /* long duration in low dword, short duration in high dword */ 259 #define PKG_POWER_LIMIT_MASK 0x7fff 260 #define PKG_POWER_LIMIT_EN (1 << 15) 261 #define PKG_POWER_LIMIT_CLAMP (1 << 16) 262 #define PKG_POWER_LIMIT_TIME_SHIFT 17 263 #define PKG_POWER_LIMIT_TIME_MASK 0x7f 264 /* 265 * For Mobile, RAPL default PL1 time window value set to 28 seconds. 266 * RAPL time window calculation defined as follows: 267 * Time Window = (float)((1+X/4)*(2*^Y), X Corresponds to [23:22], 268 * Y to [21:17] in MSR 0x610. 28 sec is equal to 0x6e. 269 */ 270 #define MB_POWER_LIMIT1_TIME_DEFAULT 0x6e 271 272 #define MSR_PKG_ENERGY_STATUS 0x00000611 273 #define MSR_PKG_PERF_STATUS 0x00000613 274 #define MSR_PKG_POWER_SKU 0x614 275 276 #define MSR_DRAM_POWER_LIMIT 0x00000618 277 #define MSR_DRAM_ENERGY_STATUS 0x00000619 278 #define MSR_DRAM_PERF_STATUS 0x0000061b 279 #define MSR_DRAM_POWER_INFO 0x0000061c 280 281 #define MSR_PP0_POWER_LIMIT 0x00000638 282 #define MSR_PP0_ENERGY_STATUS 0x00000639 283 #define MSR_PP0_POLICY 0x0000063a 284 #define MSR_PP0_PERF_STATUS 0x0000063b 285 286 #define MSR_PP1_POWER_LIMIT 0x00000640 287 #define MSR_PP1_ENERGY_STATUS 0x00000641 288 #define MSR_PP1_POLICY 0x00000642 289 #define MSR_CONFIG_TDP_NOMINAL 0x00000648 290 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064c 291 #define MSR_CORE_C1_RES 0x00000660 292 #define MSR_IACORE_RATIOS 0x0000066a 293 #define MSR_IACORE_TURBO_RATIOS 0x0000066c 294 #define MSR_IACORE_VIDS 0x0000066b 295 #define MSR_IACORE_TURBO_VIDS 0x0000066d 296 #define MSR_PKG_TURBO_CFG1 0x00000670 297 #define MSR_CPU_TURBO_WKLD_CFG1 0x00000671 298 #define MSR_CPU_TURBO_WKLD_CFG2 0x00000672 299 #define MSR_CPU_THERM_CFG1 0x00000673 300 #define MSR_CPU_THERM_CFG2 0x00000674 301 #define MSR_CPU_THERM_SENS_CFG 0x00000675 302 303 #define MSR_AMD64_MC0_MASK 0xc0010044 304 305 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 306 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 307 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 308 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 309 310 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 311 312 /* These are consecutive and not in the normal 4er MCE bank block */ 313 #define MSR_IA32_MC0_CTL2 0x00000280 314 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 315 316 #define MSR_P6_PERFCTR0 0x000000c1 317 #define MSR_P6_PERFCTR1 0x000000c2 318 #define MSR_P6_EVNTSEL0 0x00000186 319 #define MSR_P6_EVNTSEL1 0x00000187 320 321 #define MSR_KNC_PERFCTR0 0x00000020 322 #define MSR_KNC_PERFCTR1 0x00000021 323 #define MSR_KNC_EVNTSEL0 0x00000028 324 #define MSR_KNC_EVNTSEL1 0x00000029 325 326 /* Alternative perfctr range with full access. */ 327 #define MSR_IA32_PMC0 0x000004c1 328 329 /* AMD64 MSRs. Not complete. See the architecture manual for a more 330 complete list. */ 331 332 #define MSR_AMD64_PATCH_LEVEL 0x0000008b 333 #define MSR_AMD64_TSC_RATIO 0xc0000104 334 #define MSR_AMD64_NB_CFG 0xc001001f 335 #define MSR_AMD64_PATCH_LOADER 0xc0010020 336 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 337 #define MSR_AMD64_OSVW_STATUS 0xc0010141 338 #define MSR_AMD64_LS_CFG 0xc0011020 339 #define MSR_AMD64_DC_CFG 0xc0011022 340 #define MSR_AMD64_BU_CFG2 0xc001102a 341 #define MSR_AMD64_IBSFETCHCTL 0xc0011030 342 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 343 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 344 #define MSR_AMD64_IBSFETCH_REG_COUNT 3 345 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 346 #define MSR_AMD64_IBSOPCTL 0xc0011033 347 #define MSR_AMD64_IBSOPRIP 0xc0011034 348 #define MSR_AMD64_IBSOPDATA 0xc0011035 349 #define MSR_AMD64_IBSOPDATA2 0xc0011036 350 #define MSR_AMD64_IBSOPDATA3 0xc0011037 351 #define MSR_AMD64_IBSDCLINAD 0xc0011038 352 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 353 #define MSR_AMD64_IBSOP_REG_COUNT 7 354 #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 355 #define MSR_AMD64_IBSCTL 0xc001103a 356 #define MSR_AMD64_IBSBRTARGET 0xc001103b 357 #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 358 359 /* Fam 16h MSRs */ 360 #define MSR_F16H_L2I_PERF_CTL 0xc0010230 361 #define MSR_F16H_L2I_PERF_CTR 0xc0010231 362 363 /* Fam 15h MSRs */ 364 #define MSR_F15H_PERF_CTL 0xc0010200 365 #define MSR_F15H_PERF_CTR 0xc0010201 366 #define MSR_F15H_NB_PERF_CTL 0xc0010240 367 #define MSR_F15H_NB_PERF_CTR 0xc0010241 368 369 /* Fam 10h MSRs */ 370 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 371 #define FAM10H_MMIO_CONF_ENABLE (1<<0) 372 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 373 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 374 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 375 #define FAM10H_MMIO_CONF_BASE_SHIFT 20 376 #define MSR_FAM10H_NODE_ID 0xc001100c 377 378 /* K8 MSRs */ 379 #define MSR_K8_TOP_MEM1 0xc001001a 380 #define MSR_K8_TOP_MEM2 0xc001001d 381 #define MSR_K8_SYSCFG 0xc0010010 382 #define MSR_K8_INT_PENDING_MSG 0xc0010055 383 /* C1E active bits in int pending message */ 384 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 385 #define MSR_K8_TSEG_ADDR 0xc0010112 386 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 387 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 388 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 389 390 /* K7 MSRs */ 391 #define MSR_K7_EVNTSEL0 0xc0010000 392 #define MSR_K7_PERFCTR0 0xc0010004 393 #define MSR_K7_EVNTSEL1 0xc0010001 394 #define MSR_K7_PERFCTR1 0xc0010005 395 #define MSR_K7_EVNTSEL2 0xc0010002 396 #define MSR_K7_PERFCTR2 0xc0010006 397 #define MSR_K7_EVNTSEL3 0xc0010003 398 #define MSR_K7_PERFCTR3 0xc0010007 399 #define MSR_K7_CLK_CTL 0xc001001b 400 #define MSR_K7_HWCR 0xc0010015 401 #define MSR_K7_FID_VID_CTL 0xc0010041 402 #define MSR_K7_FID_VID_STATUS 0xc0010042 403 404 /* K6 MSRs */ 405 #define MSR_K6_WHCR 0xc0000082 406 #define MSR_K6_UWCCR 0xc0000085 407 #define MSR_K6_EPMR 0xc0000086 408 #define MSR_K6_PSOR 0xc0000087 409 #define MSR_K6_PFIR 0xc0000088 410 411 /* Centaur-Hauls/IDT defined MSRs. */ 412 #define MSR_IDT_FCR1 0x00000107 413 #define MSR_IDT_FCR2 0x00000108 414 #define MSR_IDT_FCR3 0x00000109 415 #define MSR_IDT_FCR4 0x0000010a 416 417 #define MSR_IDT_MCR0 0x00000110 418 #define MSR_IDT_MCR1 0x00000111 419 #define MSR_IDT_MCR2 0x00000112 420 #define MSR_IDT_MCR3 0x00000113 421 #define MSR_IDT_MCR4 0x00000114 422 #define MSR_IDT_MCR5 0x00000115 423 #define MSR_IDT_MCR6 0x00000116 424 #define MSR_IDT_MCR7 0x00000117 425 #define MSR_IDT_MCR_CTRL 0x00000120 426 427 /* VIA Cyrix defined MSRs*/ 428 #define MSR_VIA_FCR 0x00001107 429 #define MSR_VIA_LONGHAUL 0x0000110a 430 #define MSR_VIA_RNG 0x0000110b 431 #define MSR_VIA_BCR2 0x00001147 432 433 /* Transmeta defined MSRs */ 434 #define MSR_TMTA_LONGRUN_CTRL 0x80868010 435 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 436 #define MSR_TMTA_LRTI_READOUT 0x80868018 437 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 438 439 /* Intel defined MSRs. */ 440 #define MSR_IA32_P5_MC_ADDR 0x00000000 441 #define MSR_IA32_P5_MC_TYPE 0x00000001 442 #define MSR_IA32_TSC 0x00000010 443 #define MSR_IA32_PLATFORM_ID 0x00000017 444 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 445 #define MSR_EBC_FREQUENCY_ID 0x0000002c 446 #define MSR_SMI_COUNT 0x00000034 447 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 448 #define MSR_IA32_TSC_ADJUST 0x0000003b 449 450 #define FEATURE_CONTROL_LOCKED (1<<0) 451 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 452 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 453 454 #define MSR_IA32_APICBASE 0x0000001b 455 #define MSR_IA32_APICBASE_BSP (1<<8) 456 #define MSR_IA32_APICBASE_ENABLE (1<<11) 457 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 458 459 #define MSR_IA32_TSCDEADLINE 0x000006e0 460 461 #define MSR_IA32_UCODE_WRITE 0x00000079 462 #define MSR_IA32_UCODE_REV 0x0000008b 463 464 #define MSR_IA32_PERF_STATUS 0x00000198 465 #define MSR_IA32_PERF_CTL 0x00000199 466 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 467 #define MSR_AMD_PERF_STATUS 0xc0010063 468 #define MSR_AMD_PERF_CTL 0xc0010062 469 470 #define MSR_PMG_CST_CONFIG_CTL 0x000000e2 471 /* CST Range (R/W) IO port block size */ 472 #define PMG_IO_BASE_CST_RNG_BLK_SIZE 0x5 473 474 #define MSR_PMG_IO_CAPTURE_ADR 0x000000e4 475 #define MSR_IA32_MPERF 0x000000e7 476 #define MSR_IA32_APERF 0x000000e8 477 478 #define MSR_IA32_THERM_CONTROL 0x0000019a 479 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 480 481 #define THERM_INT_HIGH_ENABLE (1 << 0) 482 #define THERM_INT_LOW_ENABLE (1 << 1) 483 #define THERM_INT_PLN_ENABLE (1 << 24) 484 485 #define MSR_IA32_THERM_STATUS 0x0000019c 486 487 #define THERM_STATUS_PROCHOT (1 << 0) 488 #define THERM_STATUS_POWER_LIMIT (1 << 10) 489 490 #define MSR_THERM2_CTL 0x0000019d 491 492 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 493 494 #define MSR_IA32_TSC_DEADLINE 0x000006E0 495 496 /* P4/Xeon+ specific */ 497 #define MSR_IA32_MCG_EAX 0x00000180 498 #define MSR_IA32_MCG_EBX 0x00000181 499 #define MSR_IA32_MCG_ECX 0x00000182 500 #define MSR_IA32_MCG_EDX 0x00000183 501 #define MSR_IA32_MCG_ESI 0x00000184 502 #define MSR_IA32_MCG_EDI 0x00000185 503 #define MSR_IA32_MCG_EBP 0x00000186 504 #define MSR_IA32_MCG_ESP 0x00000187 505 #define MSR_IA32_MCG_EFLAGS 0x00000188 506 #define MSR_IA32_MCG_EIP 0x00000189 507 #define MSR_IA32_MCG_RESERVED 0x0000018a 508 509 /* Pentium IV performance counter MSRs */ 510 #define MSR_P4_BPU_PERFCTR0 0x00000300 511 #define MSR_P4_BPU_PERFCTR1 0x00000301 512 #define MSR_P4_BPU_PERFCTR2 0x00000302 513 #define MSR_P4_BPU_PERFCTR3 0x00000303 514 #define MSR_P4_MS_PERFCTR0 0x00000304 515 #define MSR_P4_MS_PERFCTR1 0x00000305 516 #define MSR_P4_MS_PERFCTR2 0x00000306 517 #define MSR_P4_MS_PERFCTR3 0x00000307 518 #define MSR_P4_FLAME_PERFCTR0 0x00000308 519 #define MSR_P4_FLAME_PERFCTR1 0x00000309 520 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 521 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 522 #define MSR_P4_IQ_PERFCTR0 0x0000030c 523 #define MSR_P4_IQ_PERFCTR1 0x0000030d 524 #define MSR_P4_IQ_PERFCTR2 0x0000030e 525 #define MSR_P4_IQ_PERFCTR3 0x0000030f 526 #define MSR_P4_IQ_PERFCTR4 0x00000310 527 #define MSR_P4_IQ_PERFCTR5 0x00000311 528 #define MSR_P4_BPU_CCCR0 0x00000360 529 #define MSR_P4_BPU_CCCR1 0x00000361 530 #define MSR_P4_BPU_CCCR2 0x00000362 531 #define MSR_P4_BPU_CCCR3 0x00000363 532 #define MSR_P4_MS_CCCR0 0x00000364 533 #define MSR_P4_MS_CCCR1 0x00000365 534 #define MSR_P4_MS_CCCR2 0x00000366 535 #define MSR_P4_MS_CCCR3 0x00000367 536 #define MSR_P4_FLAME_CCCR0 0x00000368 537 #define MSR_P4_FLAME_CCCR1 0x00000369 538 #define MSR_P4_FLAME_CCCR2 0x0000036a 539 #define MSR_P4_FLAME_CCCR3 0x0000036b 540 #define MSR_P4_IQ_CCCR0 0x0000036c 541 #define MSR_P4_IQ_CCCR1 0x0000036d 542 #define MSR_P4_IQ_CCCR2 0x0000036e 543 #define MSR_P4_IQ_CCCR3 0x0000036f 544 #define MSR_P4_IQ_CCCR4 0x00000370 545 #define MSR_P4_IQ_CCCR5 0x00000371 546 #define MSR_P4_ALF_ESCR0 0x000003ca 547 #define MSR_P4_ALF_ESCR1 0x000003cb 548 #define MSR_P4_BPU_ESCR0 0x000003b2 549 #define MSR_P4_BPU_ESCR1 0x000003b3 550 #define MSR_P4_BSU_ESCR0 0x000003a0 551 #define MSR_P4_BSU_ESCR1 0x000003a1 552 #define MSR_P4_CRU_ESCR0 0x000003b8 553 #define MSR_P4_CRU_ESCR1 0x000003b9 554 #define MSR_P4_CRU_ESCR2 0x000003cc 555 #define MSR_P4_CRU_ESCR3 0x000003cd 556 #define MSR_P4_CRU_ESCR4 0x000003e0 557 #define MSR_P4_CRU_ESCR5 0x000003e1 558 #define MSR_P4_DAC_ESCR0 0x000003a8 559 #define MSR_P4_DAC_ESCR1 0x000003a9 560 #define MSR_P4_FIRM_ESCR0 0x000003a4 561 #define MSR_P4_FIRM_ESCR1 0x000003a5 562 #define MSR_P4_FLAME_ESCR0 0x000003a6 563 #define MSR_P4_FLAME_ESCR1 0x000003a7 564 #define MSR_P4_FSB_ESCR0 0x000003a2 565 #define MSR_P4_FSB_ESCR1 0x000003a3 566 #define MSR_P4_IQ_ESCR0 0x000003ba 567 #define MSR_P4_IQ_ESCR1 0x000003bb 568 #define MSR_P4_IS_ESCR0 0x000003b4 569 #define MSR_P4_IS_ESCR1 0x000003b5 570 #define MSR_P4_ITLB_ESCR0 0x000003b6 571 #define MSR_P4_ITLB_ESCR1 0x000003b7 572 #define MSR_P4_IX_ESCR0 0x000003c8 573 #define MSR_P4_IX_ESCR1 0x000003c9 574 #define MSR_P4_MOB_ESCR0 0x000003aa 575 #define MSR_P4_MOB_ESCR1 0x000003ab 576 #define MSR_P4_MS_ESCR0 0x000003c0 577 #define MSR_P4_MS_ESCR1 0x000003c1 578 #define MSR_P4_PMH_ESCR0 0x000003ac 579 #define MSR_P4_PMH_ESCR1 0x000003ad 580 #define MSR_P4_RAT_ESCR0 0x000003bc 581 #define MSR_P4_RAT_ESCR1 0x000003bd 582 #define MSR_P4_SAAT_ESCR0 0x000003ae 583 #define MSR_P4_SAAT_ESCR1 0x000003af 584 #define MSR_P4_SSU_ESCR0 0x000003be 585 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 586 587 #define MSR_P4_TBPU_ESCR0 0x000003c2 588 #define MSR_P4_TBPU_ESCR1 0x000003c3 589 #define MSR_P4_TC_ESCR0 0x000003c4 590 #define MSR_P4_TC_ESCR1 0x000003c5 591 #define MSR_P4_U2L_ESCR0 0x000003b0 592 #define MSR_P4_U2L_ESCR1 0x000003b1 593 594 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 595 596 /* Intel Core-based CPU performance counters */ 597 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 598 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 599 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 600 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 601 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 602 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 603 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 604 605 /* Geode defined MSRs */ 606 #define MSR_GEODE_BUSCONT_CONF0 0x00001900 607 608 /* Intel VT MSRs */ 609 #define MSR_IA32_VMX_BASIC 0x00000480 610 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 611 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 612 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 613 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 614 #define MSR_IA32_VMX_MISC 0x00000485 615 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 616 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 617 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 618 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 619 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 620 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 621 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 622 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 623 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 624 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 625 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 626 #define MSR_IA32_VMX_VMFUNC 0x00000491 627 628 #define MSR_IA32_PQR_ASSOC 0xc8f 629 /* MSR bits 33:32 encode slot number 0-3 */ 630 #define MSR_IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1) 631 632 #define MSR_L2_QOS_MASK(reg) (0xd10 + (reg)) 633 634 /* VMX_BASIC bits and bitmasks */ 635 #define VMX_BASIC_VMCS_SIZE_SHIFT 32 636 #define VMX_BASIC_64 0x0001000000000000LLU 637 #define VMX_BASIC_MEM_TYPE_SHIFT 50 638 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 639 #define VMX_BASIC_MEM_TYPE_WB 6LLU 640 #define VMX_BASIC_INOUT 0x0040000000000000LLU 641 642 /* MSR_IA32_VMX_MISC bits */ 643 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 644 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 645 /* AMD-V MSRs */ 646 647 #define MSR_VM_CR 0xc0010114 648 #define MSR_VM_IGNNE 0xc0010115 649 #define MSR_VM_HSAVE_PA 0xc0010117 650 651 #endif /* _ASM_X86_MSR_INDEX_H */ 652