1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49 #include <linux/notifier.h>
50 #include <linux/refcount.h>
51 #include <linux/auxiliary_bus.h>
52
53 #include <linux/mlx5/device.h>
54 #include <linux/mlx5/doorbell.h>
55 #include <linux/mlx5/eq.h>
56 #include <linux/timecounter.h>
57 #include <linux/ptp_clock_kernel.h>
58 #include <net/devlink.h>
59
60 #define MLX5_ADEV_NAME "mlx5_core"
61
62 #define MLX5_IRQ_EQ_CTRL (U8_MAX)
63
64 enum {
65 MLX5_BOARD_ID_LEN = 64,
66 };
67
68 enum {
69 MLX5_CMD_WQ_MAX_NAME = 32,
70 };
71
72 enum {
73 CMD_OWNER_SW = 0x0,
74 CMD_OWNER_HW = 0x1,
75 CMD_STATUS_SUCCESS = 0,
76 };
77
78 enum mlx5_sqp_t {
79 MLX5_SQP_SMI = 0,
80 MLX5_SQP_GSI = 1,
81 MLX5_SQP_IEEE_1588 = 2,
82 MLX5_SQP_SNIFFER = 3,
83 MLX5_SQP_SYNC_UMR = 4,
84 };
85
86 enum {
87 MLX5_MAX_PORTS = 2,
88 };
89
90 enum {
91 MLX5_ATOMIC_MODE_OFFSET = 16,
92 MLX5_ATOMIC_MODE_IB_COMP = 1,
93 MLX5_ATOMIC_MODE_CX = 2,
94 MLX5_ATOMIC_MODE_8B = 3,
95 MLX5_ATOMIC_MODE_16B = 4,
96 MLX5_ATOMIC_MODE_32B = 5,
97 MLX5_ATOMIC_MODE_64B = 6,
98 MLX5_ATOMIC_MODE_128B = 7,
99 MLX5_ATOMIC_MODE_256B = 8,
100 };
101
102 enum {
103 MLX5_REG_QPTS = 0x4002,
104 MLX5_REG_QETCR = 0x4005,
105 MLX5_REG_QTCT = 0x400a,
106 MLX5_REG_QPDPM = 0x4013,
107 MLX5_REG_QCAM = 0x4019,
108 MLX5_REG_DCBX_PARAM = 0x4020,
109 MLX5_REG_DCBX_APP = 0x4021,
110 MLX5_REG_FPGA_CAP = 0x4022,
111 MLX5_REG_FPGA_CTRL = 0x4023,
112 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
113 MLX5_REG_CORE_DUMP = 0x402e,
114 MLX5_REG_PCAP = 0x5001,
115 MLX5_REG_PMTU = 0x5003,
116 MLX5_REG_PTYS = 0x5004,
117 MLX5_REG_PAOS = 0x5006,
118 MLX5_REG_PFCC = 0x5007,
119 MLX5_REG_PPCNT = 0x5008,
120 MLX5_REG_PPTB = 0x500b,
121 MLX5_REG_PBMC = 0x500c,
122 MLX5_REG_PMAOS = 0x5012,
123 MLX5_REG_PUDE = 0x5009,
124 MLX5_REG_PMPE = 0x5010,
125 MLX5_REG_PELC = 0x500e,
126 MLX5_REG_PVLC = 0x500f,
127 MLX5_REG_PCMR = 0x5041,
128 MLX5_REG_PDDR = 0x5031,
129 MLX5_REG_PMLP = 0x5002,
130 MLX5_REG_PPLM = 0x5023,
131 MLX5_REG_PCAM = 0x507f,
132 MLX5_REG_NODE_DESC = 0x6001,
133 MLX5_REG_HOST_ENDIANNESS = 0x7004,
134 MLX5_REG_MCIA = 0x9014,
135 MLX5_REG_MFRL = 0x9028,
136 MLX5_REG_MLCR = 0x902b,
137 MLX5_REG_MRTC = 0x902d,
138 MLX5_REG_MTRC_CAP = 0x9040,
139 MLX5_REG_MTRC_CONF = 0x9041,
140 MLX5_REG_MTRC_STDB = 0x9042,
141 MLX5_REG_MTRC_CTRL = 0x9043,
142 MLX5_REG_MPEIN = 0x9050,
143 MLX5_REG_MPCNT = 0x9051,
144 MLX5_REG_MTPPS = 0x9053,
145 MLX5_REG_MTPPSE = 0x9054,
146 MLX5_REG_MTUTC = 0x9055,
147 MLX5_REG_MPEGC = 0x9056,
148 MLX5_REG_MCQS = 0x9060,
149 MLX5_REG_MCQI = 0x9061,
150 MLX5_REG_MCC = 0x9062,
151 MLX5_REG_MCDA = 0x9063,
152 MLX5_REG_MCAM = 0x907f,
153 MLX5_REG_MIRC = 0x9162,
154 MLX5_REG_SBCAM = 0xB01F,
155 MLX5_REG_RESOURCE_DUMP = 0xC000,
156 MLX5_REG_DTOR = 0xC00E,
157 };
158
159 enum mlx5_qpts_trust_state {
160 MLX5_QPTS_TRUST_PCP = 1,
161 MLX5_QPTS_TRUST_DSCP = 2,
162 };
163
164 enum mlx5_dcbx_oper_mode {
165 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
166 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
167 };
168
169 enum {
170 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
171 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
172 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
173 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
174 };
175
176 enum mlx5_page_fault_resume_flags {
177 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
178 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
179 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
180 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
181 };
182
183 enum dbg_rsc_type {
184 MLX5_DBG_RSC_QP,
185 MLX5_DBG_RSC_EQ,
186 MLX5_DBG_RSC_CQ,
187 };
188
189 enum port_state_policy {
190 MLX5_POLICY_DOWN = 0,
191 MLX5_POLICY_UP = 1,
192 MLX5_POLICY_FOLLOW = 2,
193 MLX5_POLICY_INVALID = 0xffffffff
194 };
195
196 enum mlx5_coredev_type {
197 MLX5_COREDEV_PF,
198 MLX5_COREDEV_VF,
199 MLX5_COREDEV_SF,
200 };
201
202 struct mlx5_field_desc {
203 int i;
204 };
205
206 struct mlx5_rsc_debug {
207 struct mlx5_core_dev *dev;
208 void *object;
209 enum dbg_rsc_type type;
210 struct dentry *root;
211 struct mlx5_field_desc fields[];
212 };
213
214 enum mlx5_dev_event {
215 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
216 MLX5_DEV_EVENT_PORT_AFFINITY = 129,
217 };
218
219 enum mlx5_port_status {
220 MLX5_PORT_UP = 1,
221 MLX5_PORT_DOWN = 2,
222 };
223
224 enum mlx5_cmdif_state {
225 MLX5_CMDIF_STATE_UNINITIALIZED,
226 MLX5_CMDIF_STATE_UP,
227 MLX5_CMDIF_STATE_DOWN,
228 };
229
230 struct mlx5_cmd_first {
231 __be32 data[4];
232 };
233
234 struct mlx5_cmd_msg {
235 struct list_head list;
236 struct cmd_msg_cache *parent;
237 u32 len;
238 struct mlx5_cmd_first first;
239 struct mlx5_cmd_mailbox *next;
240 };
241
242 struct mlx5_cmd_debug {
243 struct dentry *dbg_root;
244 void *in_msg;
245 void *out_msg;
246 u8 status;
247 u16 inlen;
248 u16 outlen;
249 };
250
251 struct cmd_msg_cache {
252 /* protect block chain allocations
253 */
254 spinlock_t lock;
255 struct list_head head;
256 unsigned int max_inbox_size;
257 unsigned int num_ent;
258 };
259
260 enum {
261 MLX5_NUM_COMMAND_CACHES = 5,
262 };
263
264 struct mlx5_cmd_stats {
265 u64 sum;
266 u64 n;
267 struct dentry *root;
268 /* protect command average calculations */
269 spinlock_t lock;
270 };
271
272 struct mlx5_cmd {
273 struct mlx5_nb nb;
274
275 enum mlx5_cmdif_state state;
276 void *cmd_alloc_buf;
277 dma_addr_t alloc_dma;
278 int alloc_size;
279 void *cmd_buf;
280 dma_addr_t dma;
281 u16 cmdif_rev;
282 u8 log_sz;
283 u8 log_stride;
284 int max_reg_cmds;
285 int events;
286 u32 __iomem *vector;
287
288 /* protect command queue allocations
289 */
290 spinlock_t alloc_lock;
291
292 /* protect token allocations
293 */
294 spinlock_t token_lock;
295 u8 token;
296 unsigned long bitmask;
297 char wq_name[MLX5_CMD_WQ_MAX_NAME];
298 struct workqueue_struct *wq;
299 struct semaphore sem;
300 struct semaphore pages_sem;
301 int mode;
302 u16 allowed_opcode;
303 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
304 struct dma_pool *pool;
305 struct mlx5_cmd_debug dbg;
306 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
307 int checksum_disabled;
308 struct mlx5_cmd_stats *stats;
309 };
310
311 struct mlx5_cmd_mailbox {
312 void *buf;
313 dma_addr_t dma;
314 struct mlx5_cmd_mailbox *next;
315 };
316
317 struct mlx5_buf_list {
318 void *buf;
319 dma_addr_t map;
320 };
321
322 struct mlx5_frag_buf {
323 struct mlx5_buf_list *frags;
324 int npages;
325 int size;
326 u8 page_shift;
327 };
328
329 struct mlx5_frag_buf_ctrl {
330 struct mlx5_buf_list *frags;
331 u32 sz_m1;
332 u16 frag_sz_m1;
333 u16 strides_offset;
334 u8 log_sz;
335 u8 log_stride;
336 u8 log_frag_strides;
337 };
338
339 struct mlx5_core_psv {
340 u32 psv_idx;
341 struct psv_layout {
342 u32 pd;
343 u16 syndrome;
344 u16 reserved;
345 u16 bg;
346 u16 app_tag;
347 u32 ref_tag;
348 } psv;
349 };
350
351 struct mlx5_core_sig_ctx {
352 struct mlx5_core_psv psv_memory;
353 struct mlx5_core_psv psv_wire;
354 struct ib_sig_err err_item;
355 bool sig_status_checked;
356 bool sig_err_exists;
357 u32 sigerr_count;
358 };
359
360 #define MLX5_24BIT_MASK ((1 << 24) - 1)
361
362 enum mlx5_res_type {
363 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
364 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
365 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
366 MLX5_RES_SRQ = 3,
367 MLX5_RES_XSRQ = 4,
368 MLX5_RES_XRQ = 5,
369 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT,
370 };
371
372 struct mlx5_core_rsc_common {
373 enum mlx5_res_type res;
374 refcount_t refcount;
375 struct completion free;
376 };
377
378 struct mlx5_uars_page {
379 void __iomem *map;
380 bool wc;
381 u32 index;
382 struct list_head list;
383 unsigned int bfregs;
384 unsigned long *reg_bitmap; /* for non fast path bf regs */
385 unsigned long *fp_bitmap;
386 unsigned int reg_avail;
387 unsigned int fp_avail;
388 struct kref ref_count;
389 struct mlx5_core_dev *mdev;
390 };
391
392 struct mlx5_bfreg_head {
393 /* protect blue flame registers allocations */
394 struct mutex lock;
395 struct list_head list;
396 };
397
398 struct mlx5_bfreg_data {
399 struct mlx5_bfreg_head reg_head;
400 struct mlx5_bfreg_head wc_head;
401 };
402
403 struct mlx5_sq_bfreg {
404 void __iomem *map;
405 struct mlx5_uars_page *up;
406 bool wc;
407 u32 index;
408 unsigned int offset;
409 };
410
411 struct mlx5_core_health {
412 struct health_buffer __iomem *health;
413 __be32 __iomem *health_counter;
414 struct timer_list timer;
415 u32 prev;
416 int miss_counter;
417 u8 synd;
418 u32 fatal_error;
419 u32 crdump_size;
420 /* wq spinlock to synchronize draining */
421 spinlock_t wq_lock;
422 struct workqueue_struct *wq;
423 unsigned long flags;
424 struct work_struct fatal_report_work;
425 struct work_struct report_work;
426 struct devlink_health_reporter *fw_reporter;
427 struct devlink_health_reporter *fw_fatal_reporter;
428 struct delayed_work update_fw_log_ts_work;
429 };
430
431 struct mlx5_qp_table {
432 struct notifier_block nb;
433
434 /* protect radix tree
435 */
436 spinlock_t lock;
437 struct radix_tree_root tree;
438 };
439
440 struct mlx5_vf_context {
441 int enabled;
442 u64 port_guid;
443 u64 node_guid;
444 /* Valid bits are used to validate administrative guid only.
445 * Enabled after ndo_set_vf_guid
446 */
447 u8 port_guid_valid:1;
448 u8 node_guid_valid:1;
449 enum port_state_policy policy;
450 };
451
452 struct mlx5_core_sriov {
453 struct mlx5_vf_context *vfs_ctx;
454 int num_vfs;
455 u16 max_vfs;
456 };
457
458 struct mlx5_fc_pool {
459 struct mlx5_core_dev *dev;
460 struct mutex pool_lock; /* protects pool lists */
461 struct list_head fully_used;
462 struct list_head partially_used;
463 struct list_head unused;
464 int available_fcs;
465 int used_fcs;
466 int threshold;
467 };
468
469 struct mlx5_fc_stats {
470 spinlock_t counters_idr_lock; /* protects counters_idr */
471 struct idr counters_idr;
472 struct list_head counters;
473 struct llist_head addlist;
474 struct llist_head dellist;
475
476 struct workqueue_struct *wq;
477 struct delayed_work work;
478 unsigned long next_query;
479 unsigned long sampling_interval; /* jiffies */
480 u32 *bulk_query_out;
481 struct mlx5_fc_pool fc_pool;
482 };
483
484 struct mlx5_events;
485 struct mlx5_mpfs;
486 struct mlx5_eswitch;
487 struct mlx5_lag;
488 struct mlx5_devcom;
489 struct mlx5_fw_reset;
490 struct mlx5_eq_table;
491 struct mlx5_irq_table;
492 struct mlx5_vhca_state_notifier;
493 struct mlx5_sf_dev_table;
494 struct mlx5_sf_hw_table;
495 struct mlx5_sf_table;
496
497 struct mlx5_rate_limit {
498 u32 rate;
499 u32 max_burst_sz;
500 u16 typical_pkt_sz;
501 };
502
503 struct mlx5_rl_entry {
504 u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
505 u64 refcount;
506 u16 index;
507 u16 uid;
508 u8 dedicated : 1;
509 };
510
511 struct mlx5_rl_table {
512 /* protect rate limit table */
513 struct mutex rl_lock;
514 u16 max_size;
515 u32 max_rate;
516 u32 min_rate;
517 struct mlx5_rl_entry *rl_entry;
518 u64 refcount;
519 };
520
521 struct mlx5_core_roce {
522 struct mlx5_flow_table *ft;
523 struct mlx5_flow_group *fg;
524 struct mlx5_flow_handle *allow_rule;
525 };
526
527 enum {
528 MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
529 MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
530 /* Set during device detach to block any further devices
531 * creation/deletion on drivers rescan. Unset during device attach.
532 */
533 MLX5_PRIV_FLAGS_DETACH = 1 << 2,
534 };
535
536 struct mlx5_adev {
537 struct auxiliary_device adev;
538 struct mlx5_core_dev *mdev;
539 int idx;
540 };
541
542 struct mlx5_ft_pool;
543 struct mlx5_priv {
544 /* IRQ table valid only for real pci devices PF or VF */
545 struct mlx5_irq_table *irq_table;
546 struct mlx5_eq_table *eq_table;
547
548 /* pages stuff */
549 struct mlx5_nb pg_nb;
550 struct workqueue_struct *pg_wq;
551 struct xarray page_root_xa;
552 int fw_pages;
553 atomic_t reg_pages;
554 struct list_head free_list;
555 int vfs_pages;
556 int host_pf_pages;
557
558 struct mlx5_core_health health;
559 struct list_head traps;
560
561 /* start: qp staff */
562 struct dentry *qp_debugfs;
563 struct dentry *eq_debugfs;
564 struct dentry *cq_debugfs;
565 struct dentry *cmdif_debugfs;
566 /* end: qp staff */
567
568 /* start: alloc staff */
569 /* protect buffer allocation according to numa node */
570 struct mutex alloc_mutex;
571 int numa_node;
572
573 struct mutex pgdir_mutex;
574 struct list_head pgdir_list;
575 /* end: alloc staff */
576 struct dentry *dbg_root;
577
578 struct list_head ctx_list;
579 spinlock_t ctx_lock;
580 struct mlx5_adev **adev;
581 int adev_idx;
582 struct mlx5_events *events;
583
584 struct mlx5_flow_steering *steering;
585 struct mlx5_mpfs *mpfs;
586 struct mlx5_eswitch *eswitch;
587 struct mlx5_core_sriov sriov;
588 struct mlx5_lag *lag;
589 u32 flags;
590 struct mlx5_devcom *devcom;
591 struct mlx5_fw_reset *fw_reset;
592 struct mlx5_core_roce roce;
593 struct mlx5_fc_stats fc_stats;
594 struct mlx5_rl_table rl_table;
595 struct mlx5_ft_pool *ft_pool;
596
597 struct mlx5_bfreg_data bfregs;
598 struct mlx5_uars_page *uar;
599 #ifdef CONFIG_MLX5_SF
600 struct mlx5_vhca_state_notifier *vhca_state_notifier;
601 struct mlx5_sf_dev_table *sf_dev_table;
602 struct mlx5_core_dev *parent_mdev;
603 #endif
604 #ifdef CONFIG_MLX5_SF_MANAGER
605 struct mlx5_sf_hw_table *sf_hw_table;
606 struct mlx5_sf_table *sf_table;
607 #endif
608 };
609
610 enum mlx5_device_state {
611 MLX5_DEVICE_STATE_UP = 1,
612 MLX5_DEVICE_STATE_INTERNAL_ERROR,
613 };
614
615 enum mlx5_interface_state {
616 MLX5_INTERFACE_STATE_UP = BIT(0),
617 };
618
619 enum mlx5_pci_status {
620 MLX5_PCI_STATUS_DISABLED,
621 MLX5_PCI_STATUS_ENABLED,
622 };
623
624 enum mlx5_pagefault_type_flags {
625 MLX5_PFAULT_REQUESTOR = 1 << 0,
626 MLX5_PFAULT_WRITE = 1 << 1,
627 MLX5_PFAULT_RDMA = 1 << 2,
628 };
629
630 struct mlx5_td {
631 /* protects tirs list changes while tirs refresh */
632 struct mutex list_lock;
633 struct list_head tirs_list;
634 u32 tdn;
635 };
636
637 struct mlx5e_resources {
638 struct mlx5e_hw_objs {
639 u32 pdn;
640 struct mlx5_td td;
641 u32 mkey;
642 struct mlx5_sq_bfreg bfreg;
643 } hw_objs;
644 struct devlink_port dl_port;
645 struct net_device *uplink_netdev;
646 };
647
648 enum mlx5_sw_icm_type {
649 MLX5_SW_ICM_TYPE_STEERING,
650 MLX5_SW_ICM_TYPE_HEADER_MODIFY,
651 };
652
653 #define MLX5_MAX_RESERVED_GIDS 8
654
655 struct mlx5_rsvd_gids {
656 unsigned int start;
657 unsigned int count;
658 struct ida ida;
659 };
660
661 #define MAX_PIN_NUM 8
662 struct mlx5_pps {
663 u8 pin_caps[MAX_PIN_NUM];
664 struct work_struct out_work;
665 u64 start[MAX_PIN_NUM];
666 u8 enabled;
667 };
668
669 struct mlx5_timer {
670 struct cyclecounter cycles;
671 struct timecounter tc;
672 u32 nominal_c_mult;
673 unsigned long overflow_period;
674 struct delayed_work overflow_work;
675 };
676
677 struct mlx5_clock {
678 struct mlx5_nb pps_nb;
679 seqlock_t lock;
680 struct hwtstamp_config hwtstamp_config;
681 struct ptp_clock *ptp;
682 struct ptp_clock_info ptp_info;
683 struct mlx5_pps pps_info;
684 struct mlx5_timer timer;
685 };
686
687 struct mlx5_dm;
688 struct mlx5_fw_tracer;
689 struct mlx5_vxlan;
690 struct mlx5_geneve;
691 struct mlx5_hv_vhca;
692
693 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
694 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
695
696 enum {
697 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
698 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
699 };
700
701 enum {
702 MR_CACHE_LAST_STD_ENTRY = 20,
703 MLX5_IMR_MTT_CACHE_ENTRY,
704 MLX5_IMR_KSM_CACHE_ENTRY,
705 MAX_MR_CACHE_ENTRIES
706 };
707
708 struct mlx5_profile {
709 u64 mask;
710 u8 log_max_qp;
711 struct {
712 int size;
713 int limit;
714 } mr_cache[MAX_MR_CACHE_ENTRIES];
715 };
716
717 struct mlx5_hca_cap {
718 u32 cur[MLX5_UN_SZ_DW(hca_cap_union)];
719 u32 max[MLX5_UN_SZ_DW(hca_cap_union)];
720 };
721
722 struct mlx5_core_dev {
723 struct device *device;
724 enum mlx5_coredev_type coredev_type;
725 struct pci_dev *pdev;
726 /* sync pci state */
727 struct mutex pci_status_mutex;
728 enum mlx5_pci_status pci_status;
729 u8 rev_id;
730 char board_id[MLX5_BOARD_ID_LEN];
731 struct mlx5_cmd cmd;
732 struct {
733 struct mlx5_hca_cap *hca[MLX5_CAP_NUM];
734 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
735 u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
736 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
737 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
738 u8 embedded_cpu;
739 } caps;
740 struct mlx5_timeouts *timeouts;
741 u64 sys_image_guid;
742 phys_addr_t iseg_base;
743 struct mlx5_init_seg __iomem *iseg;
744 phys_addr_t bar_addr;
745 enum mlx5_device_state state;
746 /* sync interface state */
747 struct mutex intf_state_mutex;
748 unsigned long intf_state;
749 struct mlx5_priv priv;
750 struct mlx5_profile profile;
751 u32 issi;
752 struct mlx5e_resources mlx5e_res;
753 struct mlx5_dm *dm;
754 struct mlx5_vxlan *vxlan;
755 struct mlx5_geneve *geneve;
756 struct {
757 struct mlx5_rsvd_gids reserved_gids;
758 u32 roce_en;
759 } roce;
760 #ifdef CONFIG_MLX5_FPGA
761 struct mlx5_fpga_device *fpga;
762 #endif
763 #ifdef CONFIG_MLX5_ACCEL
764 const struct mlx5_accel_ipsec_ops *ipsec_ops;
765 #endif
766 struct mlx5_clock clock;
767 struct mlx5_ib_clock_info *clock_info;
768 struct mlx5_fw_tracer *tracer;
769 struct mlx5_rsc_dump *rsc_dump;
770 u32 vsc_addr;
771 struct mlx5_hv_vhca *hv_vhca;
772 };
773
774 struct mlx5_db {
775 __be32 *db;
776 union {
777 struct mlx5_db_pgdir *pgdir;
778 struct mlx5_ib_user_db_page *user_page;
779 } u;
780 dma_addr_t dma;
781 int index;
782 };
783
784 enum {
785 MLX5_COMP_EQ_SIZE = 1024,
786 };
787
788 enum {
789 MLX5_PTYS_IB = 1 << 0,
790 MLX5_PTYS_EN = 1 << 2,
791 };
792
793 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
794
795 enum {
796 MLX5_CMD_ENT_STATE_PENDING_COMP,
797 };
798
799 struct mlx5_cmd_work_ent {
800 unsigned long state;
801 struct mlx5_cmd_msg *in;
802 struct mlx5_cmd_msg *out;
803 void *uout;
804 int uout_size;
805 mlx5_cmd_cbk_t callback;
806 struct delayed_work cb_timeout_work;
807 void *context;
808 int idx;
809 struct completion handling;
810 struct completion done;
811 struct mlx5_cmd *cmd;
812 struct work_struct work;
813 struct mlx5_cmd_layout *lay;
814 int ret;
815 int page_queue;
816 u8 status;
817 u8 token;
818 u64 ts1;
819 u64 ts2;
820 u16 op;
821 bool polling;
822 /* Track the max comp handlers */
823 refcount_t refcnt;
824 };
825
826 struct mlx5_pas {
827 u64 pa;
828 u8 log_sz;
829 };
830
831 enum phy_port_state {
832 MLX5_AAA_111
833 };
834
835 struct mlx5_hca_vport_context {
836 u32 field_select;
837 bool sm_virt_aware;
838 bool has_smi;
839 bool has_raw;
840 enum port_state_policy policy;
841 enum phy_port_state phys_state;
842 enum ib_port_state vport_state;
843 u8 port_physical_state;
844 u64 sys_image_guid;
845 u64 port_guid;
846 u64 node_guid;
847 u32 cap_mask1;
848 u32 cap_mask1_perm;
849 u16 cap_mask2;
850 u16 cap_mask2_perm;
851 u16 lid;
852 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
853 u8 lmc;
854 u8 subnet_timeout;
855 u16 sm_lid;
856 u8 sm_sl;
857 u16 qkey_violation_counter;
858 u16 pkey_violation_counter;
859 bool grh_required;
860 };
861
mlx5_buf_offset(struct mlx5_frag_buf * buf,int offset)862 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset)
863 {
864 return buf->frags->buf + offset;
865 }
866
867 #define STRUCT_FIELD(header, field) \
868 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
869 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
870
pci2mlx5_core_dev(struct pci_dev * pdev)871 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
872 {
873 return pci_get_drvdata(pdev);
874 }
875
876 extern struct dentry *mlx5_debugfs_root;
877
fw_rev_maj(struct mlx5_core_dev * dev)878 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
879 {
880 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
881 }
882
fw_rev_min(struct mlx5_core_dev * dev)883 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
884 {
885 return ioread32be(&dev->iseg->fw_rev) >> 16;
886 }
887
fw_rev_sub(struct mlx5_core_dev * dev)888 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
889 {
890 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
891 }
892
mlx5_base_mkey(const u32 key)893 static inline u32 mlx5_base_mkey(const u32 key)
894 {
895 return key & 0xffffff00u;
896 }
897
wq_get_byte_sz(u8 log_sz,u8 log_stride)898 static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
899 {
900 return ((u32)1 << log_sz) << log_stride;
901 }
902
mlx5_init_fbc_offset(struct mlx5_buf_list * frags,u8 log_stride,u8 log_sz,u16 strides_offset,struct mlx5_frag_buf_ctrl * fbc)903 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
904 u8 log_stride, u8 log_sz,
905 u16 strides_offset,
906 struct mlx5_frag_buf_ctrl *fbc)
907 {
908 fbc->frags = frags;
909 fbc->log_stride = log_stride;
910 fbc->log_sz = log_sz;
911 fbc->sz_m1 = (1 << fbc->log_sz) - 1;
912 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
913 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1;
914 fbc->strides_offset = strides_offset;
915 }
916
mlx5_init_fbc(struct mlx5_buf_list * frags,u8 log_stride,u8 log_sz,struct mlx5_frag_buf_ctrl * fbc)917 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
918 u8 log_stride, u8 log_sz,
919 struct mlx5_frag_buf_ctrl *fbc)
920 {
921 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
922 }
923
mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl * fbc,u32 ix)924 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
925 u32 ix)
926 {
927 unsigned int frag;
928
929 ix += fbc->strides_offset;
930 frag = ix >> fbc->log_frag_strides;
931
932 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
933 }
934
935 static inline u32
mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl * fbc,u32 ix)936 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
937 {
938 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
939
940 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
941 }
942
943 enum {
944 CMD_ALLOWED_OPCODE_ALL,
945 };
946
947 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
948 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
949 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
950
951 struct mlx5_async_ctx {
952 struct mlx5_core_dev *dev;
953 atomic_t num_inflight;
954 struct wait_queue_head wait;
955 };
956
957 struct mlx5_async_work;
958
959 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
960
961 struct mlx5_async_work {
962 struct mlx5_async_ctx *ctx;
963 mlx5_async_cbk_t user_callback;
964 };
965
966 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
967 struct mlx5_async_ctx *ctx);
968 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
969 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
970 void *out, int out_size, mlx5_async_cbk_t callback,
971 struct mlx5_async_work *work);
972
973 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
974 int out_size);
975
976 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out) \
977 ({ \
978 mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out, \
979 MLX5_ST_SZ_BYTES(ifc_cmd##_out)); \
980 })
981
982 #define mlx5_cmd_exec_in(dev, ifc_cmd, in) \
983 ({ \
984 u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {}; \
985 mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out); \
986 })
987
988 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
989 void *out, int out_size);
990 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
991 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
992
993 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
994 void mlx5_health_flush(struct mlx5_core_dev *dev);
995 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
996 int mlx5_health_init(struct mlx5_core_dev *dev);
997 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
998 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
999 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1000 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1001 int mlx5_buf_alloc(struct mlx5_core_dev *dev,
1002 int size, struct mlx5_frag_buf *buf);
1003 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1004 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1005 struct mlx5_frag_buf *buf, int node);
1006 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1007 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1008 gfp_t flags, int npages);
1009 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1010 struct mlx5_cmd_mailbox *head);
1011 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
1012 int inlen);
1013 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
1014 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, u32 mkey, u32 *out,
1015 int outlen);
1016 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1017 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1018 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1019 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1020 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1021 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1022 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1023 s32 npages, bool ec_function);
1024 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1025 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1026 void mlx5_register_debugfs(void);
1027 void mlx5_unregister_debugfs(void);
1028
1029 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas);
1030 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1031 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1032 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn);
1033 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1034 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1035
1036 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1037 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1038 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1039 int size_in, void *data_out, int size_out,
1040 u16 reg_num, int arg, int write);
1041
1042 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1043 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1044 int node);
1045 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1046
1047 const char *mlx5_command_str(int command);
1048 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1049 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1050 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1051 int npsvs, u32 *sig_index);
1052 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1053 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1054 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1055 struct mlx5_odp_caps *odp_caps);
1056 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1057 u8 port_num, void *out, size_t sz);
1058
1059 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1060 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1061 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1062 struct mlx5_rate_limit *rl);
1063 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1064 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1065 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1066 bool dedicated_entry, u16 *index);
1067 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1068 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1069 struct mlx5_rate_limit *rl_1);
1070 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1071 bool map_wc, bool fast_path);
1072 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1073
1074 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev);
1075 struct cpumask *
1076 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector);
1077 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1078 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1079 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1080 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1081
mlx5_mkey_to_idx(u32 mkey)1082 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1083 {
1084 return mkey >> 8;
1085 }
1086
mlx5_idx_to_mkey(u32 mkey_idx)1087 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1088 {
1089 return mkey_idx << 8;
1090 }
1091
mlx5_mkey_variant(u32 mkey)1092 static inline u8 mlx5_mkey_variant(u32 mkey)
1093 {
1094 return mkey & 0xff;
1095 }
1096
1097 /* Async-atomic event notifier used by mlx5 core to forward FW
1098 * evetns received from event queue to mlx5 consumers.
1099 * Optimise event queue dipatching.
1100 */
1101 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1102 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1103
1104 /* Async-atomic event notifier used for forwarding
1105 * evetns from the event queue into the to mlx5 events dispatcher,
1106 * eswitch, clock and others.
1107 */
1108 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1109 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1110
1111 /* Blocking event notifier used to forward SW events, used for slow path */
1112 int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1113 int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1114 int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1115 void *data);
1116
1117 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1118
1119 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1120 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1121 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1122 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1123 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1124 bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
1125 bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
1126 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1127 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1128 struct net_device *slave);
1129 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1130 u64 *values,
1131 int num_counters,
1132 size_t *offsets);
1133 struct mlx5_core_dev *mlx5_lag_get_peer_mdev(struct mlx5_core_dev *dev);
1134 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1135 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1136 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1137 u64 length, u32 log_alignment, u16 uid,
1138 phys_addr_t *addr, u32 *obj_id);
1139 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1140 u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1141
1142 #ifdef CONFIG_MLX5_CORE_IPOIB
1143 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1144 struct ib_device *ibdev,
1145 const char *name,
1146 void (*setup)(struct net_device *));
1147 #endif /* CONFIG_MLX5_CORE_IPOIB */
1148 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1149 struct ib_device *device,
1150 struct rdma_netdev_alloc_params *params);
1151
1152 enum {
1153 MLX5_PCI_DEV_IS_VF = 1 << 0,
1154 };
1155
mlx5_core_is_pf(const struct mlx5_core_dev * dev)1156 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1157 {
1158 return dev->coredev_type == MLX5_COREDEV_PF;
1159 }
1160
mlx5_core_is_vf(const struct mlx5_core_dev * dev)1161 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1162 {
1163 return dev->coredev_type == MLX5_COREDEV_VF;
1164 }
1165
mlx5_core_is_ecpf(const struct mlx5_core_dev * dev)1166 static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1167 {
1168 return dev->caps.embedded_cpu;
1169 }
1170
1171 static inline bool
mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev * dev)1172 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1173 {
1174 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1175 }
1176
mlx5_ecpf_vport_exists(const struct mlx5_core_dev * dev)1177 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1178 {
1179 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1180 }
1181
mlx5_core_max_vfs(const struct mlx5_core_dev * dev)1182 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1183 {
1184 return dev->priv.sriov.max_vfs;
1185 }
1186
mlx5_get_gid_table_len(u16 param)1187 static inline int mlx5_get_gid_table_len(u16 param)
1188 {
1189 if (param > 4) {
1190 pr_warn("gid table length is zero\n");
1191 return 0;
1192 }
1193
1194 return 8 * (1 << param);
1195 }
1196
mlx5_rl_is_supported(struct mlx5_core_dev * dev)1197 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1198 {
1199 return !!(dev->priv.rl_table.max_size);
1200 }
1201
mlx5_core_is_mp_slave(struct mlx5_core_dev * dev)1202 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1203 {
1204 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1205 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1206 }
1207
mlx5_core_is_mp_master(struct mlx5_core_dev * dev)1208 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1209 {
1210 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1211 }
1212
mlx5_core_mp_enabled(struct mlx5_core_dev * dev)1213 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1214 {
1215 return mlx5_core_is_mp_slave(dev) ||
1216 mlx5_core_is_mp_master(dev);
1217 }
1218
mlx5_core_native_port_num(struct mlx5_core_dev * dev)1219 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1220 {
1221 if (!mlx5_core_mp_enabled(dev))
1222 return 1;
1223
1224 return MLX5_CAP_GEN(dev, native_port_num);
1225 }
1226
mlx5_get_dev_index(struct mlx5_core_dev * dev)1227 static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev)
1228 {
1229 int idx = MLX5_CAP_GEN(dev, native_port_num);
1230
1231 if (idx >= 1 && idx <= MLX5_MAX_PORTS)
1232 return idx - 1;
1233 else
1234 return PCI_FUNC(dev->pdev->devfn);
1235 }
1236
1237 enum {
1238 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1239 };
1240
mlx5_is_roce_init_enabled(struct mlx5_core_dev * dev)1241 static inline bool mlx5_is_roce_init_enabled(struct mlx5_core_dev *dev)
1242 {
1243 struct devlink *devlink = priv_to_devlink(dev);
1244 union devlink_param_value val;
1245 int err;
1246
1247 err = devlink_param_driverinit_value_get(devlink,
1248 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
1249 &val);
1250 return err ? MLX5_CAP_GEN(dev, roce) : val.vbool;
1251 }
1252
1253 #endif /* MLX5_DRIVER_H */
1254