1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2016 Carlo Caione <carlo@caione.org>
4  */
5 
6 #ifndef __MESON_GX_MMC_H__
7 #define __MESON_GX_MMC_H__
8 
9 #include <mmc.h>
10 #include <linux/bitops.h>
11 
12 enum meson_gx_mmc_compatible {
13 	MMC_COMPATIBLE_GX,
14 	MMC_COMPATIBLE_SM1,
15 };
16 
17 #define SDIO_PORT_A			0
18 #define SDIO_PORT_B			1
19 #define SDIO_PORT_C			2
20 
21 #define SD_EMMC_CLKSRC_24M		24000000	/* 24 MHz */
22 #define SD_EMMC_CLKSRC_DIV2		1000000000	/* 1 GHz */
23 
24 #define MESON_SD_EMMC_CLOCK		0x00
25 #define   CLK_MAX_DIV			63
26 #define   CLK_SRC_24M			(0 << 6)
27 #define   CLK_SRC_DIV2			(1 << 6)
28 #define   CLK_CO_PHASE_000		(0 << 8)
29 #define   CLK_CO_PHASE_090		(1 << 8)
30 #define   CLK_CO_PHASE_180		(2 << 8)
31 #define   CLK_CO_PHASE_270		(3 << 8)
32 #define   CLK_TX_PHASE_000		(0 << 10)
33 #define   CLK_TX_PHASE_090		(1 << 10)
34 #define   CLK_TX_PHASE_180		(2 << 10)
35 #define   CLK_TX_PHASE_270		(3 << 10)
36 #define   CLK_ALWAYS_ON			BIT(24)
37 
38 #define MESON_SD_EMMC_CFG		0x44
39 #define   CFG_BUS_WIDTH_MASK		GENMASK(1, 0)
40 #define   CFG_BUS_WIDTH_1		0
41 #define   CFG_BUS_WIDTH_4		1
42 #define   CFG_BUS_WIDTH_8		2
43 #define   CFG_BL_LEN_MASK		GENMASK(7, 4)
44 #define   CFG_BL_LEN_SHIFT		4
45 #define   CFG_BL_LEN_512		(9 << 4)
46 #define   CFG_RESP_TIMEOUT_MASK		GENMASK(11, 8)
47 #define   CFG_RESP_TIMEOUT_256		(8 << 8)
48 #define   CFG_RC_CC_MASK		GENMASK(15, 12)
49 #define   CFG_RC_CC_16			(4 << 12)
50 #define   CFG_SDCLK_ALWAYS_ON		BIT(18)
51 #define   CFG_AUTO_CLK			BIT(23)
52 
53 #define MESON_SD_EMMC_STATUS		0x48
54 #define   STATUS_MASK			GENMASK(15, 0)
55 #define   STATUS_ERR_MASK		GENMASK(12, 0)
56 #define   STATUS_RXD_ERR_MASK		GENMASK(7, 0)
57 #define   STATUS_TXD_ERR		BIT(8)
58 #define   STATUS_DESC_ERR		BIT(9)
59 #define   STATUS_RESP_ERR		BIT(10)
60 #define   STATUS_RESP_TIMEOUT		BIT(11)
61 #define   STATUS_DESC_TIMEOUT		BIT(12)
62 #define   STATUS_END_OF_CHAIN		BIT(13)
63 
64 #define MESON_SD_EMMC_IRQ_EN		0x4c
65 
66 #define MESON_SD_EMMC_CMD_CFG		0x50
67 #define   CMD_CFG_LENGTH_MASK		GENMASK(8, 0)
68 #define   CMD_CFG_BLOCK_MODE		BIT(9)
69 #define   CMD_CFG_R1B			BIT(10)
70 #define   CMD_CFG_END_OF_CHAIN		BIT(11)
71 #define   CMD_CFG_TIMEOUT_4S		(12 << 12)
72 #define   CMD_CFG_NO_RESP		BIT(16)
73 #define   CMD_CFG_DATA_IO		BIT(18)
74 #define   CMD_CFG_DATA_WR		BIT(19)
75 #define   CMD_CFG_RESP_NOCRC		BIT(20)
76 #define   CMD_CFG_RESP_128		BIT(21)
77 #define   CMD_CFG_CMD_INDEX_SHIFT	24
78 #define   CMD_CFG_OWNER			BIT(31)
79 
80 #define MESON_SD_EMMC_CMD_ARG		0x54
81 #define MESON_SD_EMMC_CMD_DAT		0x58
82 #define MESON_SD_EMMC_CMD_RSP		0x5c
83 #define MESON_SD_EMMC_CMD_RSP1		0x60
84 #define MESON_SD_EMMC_CMD_RSP2		0x64
85 #define MESON_SD_EMMC_CMD_RSP3		0x68
86 
87 struct meson_mmc_plat {
88 	struct mmc_config cfg;
89 	struct mmc mmc;
90 	void *regbase;
91 	void *w_buf;
92 };
93 
94 #endif
95