1 /* 2 * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef EMMC_REGISTERS_H 8 #define EMMC_REGISTERS_H 9 10 /* MMC channel select */ 11 #define MMC_CH0 (0U) /* SDHI2/MMC0 */ 12 #define MMC_CH1 (1U) /* SDHI3/MMC1 */ 13 14 #if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2M) || (RCAR_LSI == RZ_G2H) || (RCAR_LSI == RZ_G2N) 15 #define USE_MMC_CH (MMC_CH1) /* R-Car E3 or RZ/G2{H,M,N} */ 16 #else /* RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2{H,M,N} */ 17 #define USE_MMC_CH (MMC_CH0) /* R-Car H3/M3/M3N */ 18 #endif /* RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2{H,M,N} */ 19 20 #define BIT0 (0x00000001U) 21 #define BIT1 (0x00000002U) 22 #define BIT2 (0x00000004U) 23 #define BIT3 (0x00000008U) 24 #define BIT4 (0x00000010U) 25 #define BIT5 (0x00000020U) 26 #define BIT6 (0x00000040U) 27 #define BIT7 (0x00000080U) 28 #define BIT8 (0x00000100U) 29 #define BIT9 (0x00000200U) 30 #define BIT10 (0x00000400U) 31 #define BIT11 (0x00000800U) 32 #define BIT12 (0x00001000U) 33 #define BIT13 (0x00002000U) 34 #define BIT14 (0x00004000U) 35 #define BIT15 (0x00008000U) 36 #define BIT16 (0x00010000U) 37 #define BIT17 (0x00020000U) 38 #define BIT18 (0x00040000U) 39 #define BIT19 (0x00080000U) 40 #define BIT20 (0x00100000U) 41 #define BIT21 (0x00200000U) 42 #define BIT22 (0x00400000U) 43 #define BIT23 (0x00800000U) 44 #define BIT24 (0x01000000U) 45 #define BIT25 (0x02000000U) 46 #define BIT26 (0x04000000U) 47 #define BIT27 (0x08000000U) 48 #define BIT28 (0x10000000U) 49 #define BIT29 (0x20000000U) 50 #define BIT30 (0x40000000U) 51 #define BIT31 (0x80000000U) 52 53 #if USE_MMC_CH == MMC_CH0 54 #define CPG_SDxCKCR (CPG_SD2CKCR) /* SDHI2/MMC0 */ 55 #else /* USE_MMC_CH == MMC_CH0 */ 56 #define CPG_SDxCKCR (CPG_SD3CKCR) /* SDHI3/MMC1 */ 57 #endif /* USE_MMC_CH == MMC_CH0 */ 58 59 /* Boot Status register */ 60 #define MFISBTSTSR (0xE6260604U) 61 62 #define MFISBTSTSR_BOOT_PARTITION (0x00000010U) 63 64 /* eMMC registers */ 65 #define MMC0_SD_BASE (0xEE140000U) 66 #define MMC1_SD_BASE (0xEE160000U) 67 68 #if USE_MMC_CH == MMC_CH0 69 #define MMC_SD_BASE (MMC0_SD_BASE) 70 #else /* USE_MMC_CH == MMC_CH0 */ 71 #define MMC_SD_BASE (MMC1_SD_BASE) 72 #endif /* USE_MMC_CH == MMC_CH0 */ 73 74 #define SD_CMD (MMC_SD_BASE + 0x0000U) 75 #define SD_PORTSEL (MMC_SD_BASE + 0x0008U) 76 #define SD_ARG (MMC_SD_BASE + 0x0010U) 77 #define SD_ARG1 (MMC_SD_BASE + 0x0018U) 78 #define SD_STOP (MMC_SD_BASE + 0x0020U) 79 #define SD_SECCNT (MMC_SD_BASE + 0x0028U) 80 #define SD_RSP10 (MMC_SD_BASE + 0x0030U) 81 #define SD_RSP1 (MMC_SD_BASE + 0x0038U) 82 #define SD_RSP32 (MMC_SD_BASE + 0x0040U) 83 #define SD_RSP3 (MMC_SD_BASE + 0x0048U) 84 #define SD_RSP54 (MMC_SD_BASE + 0x0050U) 85 #define SD_RSP5 (MMC_SD_BASE + 0x0058U) 86 #define SD_RSP76 (MMC_SD_BASE + 0x0060U) 87 #define SD_RSP7 (MMC_SD_BASE + 0x0068U) 88 #define SD_INFO1 (MMC_SD_BASE + 0x0070U) 89 #define SD_INFO2 (MMC_SD_BASE + 0x0078U) 90 #define SD_INFO1_MASK (MMC_SD_BASE + 0x0080U) 91 #define SD_INFO2_MASK (MMC_SD_BASE + 0x0088U) 92 #define SD_CLK_CTRL (MMC_SD_BASE + 0x0090U) 93 #define SD_SIZE (MMC_SD_BASE + 0x0098U) 94 #define SD_OPTION (MMC_SD_BASE + 0x00A0U) 95 #define SD_ERR_STS1 (MMC_SD_BASE + 0x00B0U) 96 #define SD_ERR_STS2 (MMC_SD_BASE + 0x00B8U) 97 #define SD_BUF0 (MMC_SD_BASE + 0x00C0U) 98 #define SDIO_MODE (MMC_SD_BASE + 0x00D0U) 99 #define SDIO_INFO1 (MMC_SD_BASE + 0x00D8U) 100 #define SDIO_INFO1_MASK (MMC_SD_BASE + 0x00E0U) 101 #define CC_EXT_MODE (MMC_SD_BASE + 0x0360U) 102 #define SOFT_RST (MMC_SD_BASE + 0x0380U) 103 #define VERSION (MMC_SD_BASE + 0x0388U) 104 #define HOST_MODE (MMC_SD_BASE + 0x0390U) 105 #define DM_CM_DTRAN_MODE (MMC_SD_BASE + 0x0820U) 106 #define DM_CM_DTRAN_CTRL (MMC_SD_BASE + 0x0828U) 107 #define DM_CM_RST (MMC_SD_BASE + 0x0830U) 108 #define DM_CM_INFO1 (MMC_SD_BASE + 0x0840U) 109 #define DM_CM_INFO1_MASK (MMC_SD_BASE + 0x0848U) 110 #define DM_CM_INFO2 (MMC_SD_BASE + 0x0850U) 111 #define DM_CM_INFO2_MASK (MMC_SD_BASE + 0x0858U) 112 #define DM_DTRAN_ADDR (MMC_SD_BASE + 0x0880U) 113 114 /* SD_INFO1 Registers */ 115 #define SD_INFO1_HPIRES 0x00010000UL /* Response Reception Completion */ 116 #define SD_INFO1_INFO10 0x00000400UL /* Indicates the SDDAT3 state */ 117 #define SD_INFO1_INFO9 0x00000200UL /* SDDAT3 Card Insertion */ 118 #define SD_INFO1_INFO8 0x00000100UL /* SDDAT3 Card Removal */ 119 #define SD_INFO1_INFO7 0x00000080UL /* Write Protect */ 120 #define SD_INFO1_INFO5 0x00000020UL /* Indicates the ISDCD state */ 121 #define SD_INFO1_INFO4 0x00000010UL /* ISDCD Card Insertion */ 122 #define SD_INFO1_INFO3 0x00000008UL /* ISDCD Card Removal */ 123 #define SD_INFO1_INFO2 0x00000004UL /* Access end */ 124 #define SD_INFO1_INFO0 0x00000001UL /* Response end */ 125 126 /* SD_INFO2 Registers */ 127 #define SD_INFO2_ILA 0x00008000UL /* Illegal Access Error */ 128 #define SD_INFO2_CBSY 0x00004000UL /* Command Type Register Busy */ 129 #define SD_INFO2_SCLKDIVEN 0x00002000UL 130 #define SD_INFO2_BWE 0x00000200UL /* SD_BUF Write Enable */ 131 #define SD_INFO2_BRE 0x00000100UL /* SD_BUF Read Enable */ 132 #define SD_INFO2_DAT0 0x00000080UL /* SDDAT0 */ 133 #define SD_INFO2_ERR6 0x00000040UL /* Response Timeout */ 134 #define SD_INFO2_ERR5 0x00000020UL /* SD_BUF Illegal Read Access */ 135 #define SD_INFO2_ERR4 0x00000010UL /* SD_BUF Illegal Write Access */ 136 #define SD_INFO2_ERR3 0x00000008UL /* Data Timeout */ 137 #define SD_INFO2_ERR2 0x00000004UL /* END Error */ 138 #define SD_INFO2_ERR1 0x00000002UL /* CRC Error */ 139 #define SD_INFO2_ERR0 0x00000001UL /* CMD Error */ 140 #define SD_INFO2_ALL_ERR 0x0000807FUL 141 #define SD_INFO2_CLEAR 0x00000800UL /* BIT11 write value should always be 1. HWM_0003 */ 142 143 /* SOFT_RST */ 144 #define SOFT_RST_SDRST 0x00000001UL 145 146 /* SD_CLK_CTRL */ 147 #define SD_CLK_CTRL_SDCLKOFFEN 0x00000200UL 148 #define SD_CLK_CTRL_SCLKEN 0x00000100UL 149 #define SD_CLK_CTRL_CLKDIV_MASK 0x000000FFUL 150 #define SD_CLOCK_ENABLE 0x00000100UL 151 #define SD_CLOCK_DISABLE 0x00000000UL 152 #define SD_CLK_WRITE_MASK 0x000003FFUL 153 #define SD_CLK_CLKDIV_CLEAR_MASK 0xFFFFFF0FUL 154 155 /* SD_OPTION */ 156 #define SD_OPTION_TIMEOUT_CNT_MASK 0x000000F0UL 157 158 /* 159 * MMC Clock Frequency 160 * 200MHz * 1/x = output clock 161 */ 162 #define MMC_CLK_OFF 0UL /* Clock output is disabled */ 163 #define MMC_400KHZ 512UL /* 200MHz * 1/512 = 390 KHz */ 164 #define MMC_20MHZ 16UL /* 200MHz * 1/16 = 12.5 MHz Normal speed mode */ 165 #define MMC_26MHZ 8UL /* 200MHz * 1/8 = 25 MHz HS mode 26Mhz */ 166 #define MMC_52MHZ 4UL /* 200MHz * 1/4 = 50 MHz HS mode 52Mhz */ 167 #define MMC_100MHZ 2UL /* 200MHz * 1/2 = 100 MHz */ 168 #define MMC_200MHZ 1UL /* 200MHz * 1/1 = 200 MHz */ 169 170 #define MMC_FREQ_52MHZ 52000000UL 171 #define MMC_FREQ_26MHZ 26000000UL 172 #define MMC_FREQ_20MHZ 20000000UL 173 174 /* MMC Clock DIV */ 175 #define MMC_SD_CLK_START 0x00000100UL /* CLOCK On */ 176 #define MMC_SD_CLK_STOP (~0x00000100UL) /* CLOCK stop */ 177 #define MMC_SD_CLK_DIV1 0x000000FFUL /* 1/1 */ 178 #define MMC_SD_CLK_DIV2 0x00000000UL /* 1/2 */ 179 #define MMC_SD_CLK_DIV4 0x00000001UL /* 1/4 */ 180 #define MMC_SD_CLK_DIV8 0x00000002UL /* 1/8 */ 181 #define MMC_SD_CLK_DIV16 0x00000004UL /* 1/16 */ 182 #define MMC_SD_CLK_DIV32 0x00000008UL /* 1/32 */ 183 #define MMC_SD_CLK_DIV64 0x00000010UL /* 1/64 */ 184 #define MMC_SD_CLK_DIV128 0x00000020UL /* 1/128 */ 185 #define MMC_SD_CLK_DIV256 0x00000040UL /* 1/256 */ 186 #define MMC_SD_CLK_DIV512 0x00000080UL /* 1/512 */ 187 188 /* DM_CM_DTRAN_MODE */ 189 #define DM_CM_DTRAN_MODE_CH0 0x00000000UL /* CH0(downstream) */ 190 #define DM_CM_DTRAN_MODE_CH1 0x00010000UL /* CH1(upstream) */ 191 #define DM_CM_DTRAN_MODE_BIT_WIDTH 0x00000030UL 192 193 /* CC_EXT_MODE */ 194 #define CC_EXT_MODE_DMASDRW_ENABLE 0x00000002UL /* SD_BUF Read/Write DMA Transfer */ 195 #define CC_EXT_MODE_CLEAR 0x00001010UL /* BIT 12 & 4 always 1. */ 196 197 /* DM_CM_INFO_MASK */ 198 #define DM_CM_INFO_MASK_CLEAR 0xFFFCFFFEUL 199 #define DM_CM_INFO_CH0_ENABLE 0x00010001UL 200 #define DM_CM_INFO_CH1_ENABLE 0x00020001UL 201 202 /* DM_DTRAN_ADDR */ 203 #define DM_DTRAN_ADDR_WRITE_MASK 0xFFFFFFF8UL 204 205 /* DM_CM_DTRAN_CTRL */ 206 #define DM_CM_DTRAN_CTRL_START 0x00000001UL 207 208 /* SYSC Registers */ 209 #if USE_MMC_CH == MMC_CH0 210 #define CPG_MSTP_MMC (BIT12) /* SDHI2/MMC0 */ 211 #else /* USE_MMC_CH == MMC_CH0 */ 212 #define CPG_MSTP_MMC (BIT11) /* SDHI3/MMC1 */ 213 #endif /* USE_MMC_CH == MMC_CH0 */ 214 215 #endif /* EMMC_REGISTERS_H */ 216