1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __ASM_SH_PROCESSOR_H
3 #define __ASM_SH_PROCESSOR_H
4 
5 #include <asm/cpu-features.h>
6 #include <asm/segment.h>
7 #include <asm/cache.h>
8 
9 #ifndef __ASSEMBLY__
10 /*
11  *  CPU type and hardware bug flags. Kept separately for each CPU.
12  *
13  *  Each one of these also needs a CONFIG_CPU_SUBTYPE_xxx entry
14  *  in arch/sh/mm/Kconfig, as well as an entry in arch/sh/kernel/setup.c
15  *  for parsing the subtype in get_cpu_subtype().
16  */
17 enum cpu_type {
18 	/* SH-2 types */
19 	CPU_SH7619, CPU_J2,
20 
21 	/* SH-2A types */
22 	CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_SH7264, CPU_SH7269,
23 	CPU_MXG,
24 
25 	/* SH-3 types */
26 	CPU_SH7705, CPU_SH7706, CPU_SH7707,
27 	CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
28 	CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712,
29 	CPU_SH7720, CPU_SH7721, CPU_SH7729,
30 
31 	/* SH-4 types */
32 	CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
33 	CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
34 
35 	/* SH-4A types */
36 	CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
37 	CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SH7734, CPU_SHX3,
38 
39 	/* SH4AL-DSP types */
40 	CPU_SH7343, CPU_SH7722, CPU_SH7366, CPU_SH7372,
41 
42 	/* Unknown subtype */
43 	CPU_SH_NONE
44 };
45 
46 enum cpu_family {
47 	CPU_FAMILY_SH2,
48 	CPU_FAMILY_SH2A,
49 	CPU_FAMILY_SH3,
50 	CPU_FAMILY_SH4,
51 	CPU_FAMILY_SH4A,
52 	CPU_FAMILY_SH4AL_DSP,
53 	CPU_FAMILY_UNKNOWN,
54 };
55 
56 /*
57  * TLB information structure
58  *
59  * Defined for both I and D tlb, per-processor.
60  */
61 struct tlb_info {
62 	unsigned long long next;
63 	unsigned long long first;
64 	unsigned long long last;
65 
66 	unsigned int entries;
67 	unsigned int step;
68 
69 	unsigned long flags;
70 };
71 
72 struct sh_cpuinfo {
73 	unsigned int type, family;
74 	int cut_major, cut_minor;
75 	unsigned long loops_per_jiffy;
76 	unsigned long asid_cache;
77 
78 	struct cache_info icache;	/* Primary I-cache */
79 	struct cache_info dcache;	/* Primary D-cache */
80 	struct cache_info scache;	/* Secondary cache */
81 
82 	/* TLB info */
83 	struct tlb_info itlb;
84 	struct tlb_info dtlb;
85 
86 	unsigned int phys_bits;
87 	unsigned long flags;
88 } __attribute__ ((aligned(L1_CACHE_BYTES)));
89 
90 extern struct sh_cpuinfo cpu_data[];
91 #define boot_cpu_data cpu_data[0]
92 #define current_cpu_data cpu_data[smp_processor_id()]
93 #define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
94 
95 #define cpu_sleep()	__asm__ __volatile__ ("sleep" : : : "memory")
96 #define cpu_relax()	barrier()
97 
98 void default_idle(void);
99 void stop_this_cpu(void *);
100 
101 /* Forward decl */
102 struct seq_operations;
103 struct task_struct;
104 
105 extern struct pt_regs fake_swapper_regs;
106 
107 extern void cpu_init(void);
108 extern void cpu_probe(void);
109 
110 /* arch/sh/kernel/process.c */
111 extern unsigned int xstate_size;
112 extern void free_thread_xstate(struct task_struct *);
113 extern struct kmem_cache *task_xstate_cachep;
114 
115 /* arch/sh/mm/alignment.c */
116 extern int get_unalign_ctl(struct task_struct *, unsigned long addr);
117 extern int set_unalign_ctl(struct task_struct *, unsigned int val);
118 
119 #define GET_UNALIGN_CTL(tsk, addr)	get_unalign_ctl((tsk), (addr))
120 #define SET_UNALIGN_CTL(tsk, val)	set_unalign_ctl((tsk), (val))
121 
122 /* arch/sh/mm/init.c */
123 extern unsigned int mem_init_done;
124 
125 /* arch/sh/kernel/setup.c */
126 const char *get_cpu_subtype(struct sh_cpuinfo *c);
127 extern const struct seq_operations cpuinfo_op;
128 
129 /* thread_struct flags */
130 #define SH_THREAD_UAC_NOPRINT	(1 << 0)
131 #define SH_THREAD_UAC_SIGBUS	(1 << 1)
132 #define SH_THREAD_UAC_MASK	(SH_THREAD_UAC_NOPRINT | SH_THREAD_UAC_SIGBUS)
133 
134 /* processor boot mode configuration */
135 #define MODE_PIN0 (1 << 0)
136 #define MODE_PIN1 (1 << 1)
137 #define MODE_PIN2 (1 << 2)
138 #define MODE_PIN3 (1 << 3)
139 #define MODE_PIN4 (1 << 4)
140 #define MODE_PIN5 (1 << 5)
141 #define MODE_PIN6 (1 << 6)
142 #define MODE_PIN7 (1 << 7)
143 #define MODE_PIN8 (1 << 8)
144 #define MODE_PIN9 (1 << 9)
145 #define MODE_PIN10 (1 << 10)
146 #define MODE_PIN11 (1 << 11)
147 #define MODE_PIN12 (1 << 12)
148 #define MODE_PIN13 (1 << 13)
149 #define MODE_PIN14 (1 << 14)
150 #define MODE_PIN15 (1 << 15)
151 
152 int generic_mode_pins(void);
153 int test_mode_pin(int pin);
154 
155 #ifdef CONFIG_VSYSCALL
156 int vsyscall_init(void);
157 #else
158 #define vsyscall_init() do { } while (0)
159 #endif
160 
161 /*
162  * SH-2A has both 16 and 32-bit opcodes, do lame encoding checks.
163  */
164 #ifdef CONFIG_CPU_SH2A
165 extern unsigned int instruction_size(unsigned int insn);
166 #else
167 #define instruction_size(insn)	(2)
168 #endif
169 
170 #endif /* __ASSEMBLY__ */
171 
172 #include <asm/processor_32.h>
173 
174 #endif /* __ASM_SH_PROCESSOR_H */
175