1 /* 2 * Copyright (c) 2020, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MTK_DCM_UTILS_H 8 #define MTK_DCM_UTILS_H 9 10 #include <stdbool.h> 11 12 #include <mtk_dcm.h> 13 #include <platform_def.h> 14 15 /* Base */ 16 #define MP_CPUSYS_TOP_BASE (MCUCFG_BASE + 0x8000) 17 #define CPCCFG_REG_BASE (MCUCFG_BASE + 0xA800) 18 19 /* Register Definition */ 20 #define CPU_PLLDIV_CFG0 (MP_CPUSYS_TOP_BASE + 0x22a0) 21 #define CPU_PLLDIV_CFG1 (MP_CPUSYS_TOP_BASE + 0x22a4) 22 #define CPU_PLLDIV_CFG2 (MP_CPUSYS_TOP_BASE + 0x22a8) 23 #define CPU_PLLDIV_CFG3 (MP_CPUSYS_TOP_BASE + 0x22ac) 24 #define CPU_PLLDIV_CFG4 (MP_CPUSYS_TOP_BASE + 0x22b0) 25 #define BUS_PLLDIV_CFG (MP_CPUSYS_TOP_BASE + 0x22e0) 26 #define MCSI_DCM0 (MP_CPUSYS_TOP_BASE + 0x2440) 27 #define MP_ADB_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2500) 28 #define MP_ADB_DCM_CFG4 (MP_CPUSYS_TOP_BASE + 0x2510) 29 #define MP_MISC_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2518) 30 #define MCUSYS_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x25c0) 31 #define EMI_WFIFO (CPCCFG_REG_BASE + 0x100) 32 #define MP0_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x4880) 33 #define MP0_DCM_CFG7 (MP_CPUSYS_TOP_BASE + 0x489c) 34 35 /* MP_CPUSYS_TOP */ 36 bool dcm_mp_cpusys_top_adb_dcm_is_on(void); 37 void dcm_mp_cpusys_top_adb_dcm(bool on); 38 bool dcm_mp_cpusys_top_apb_dcm_is_on(void); 39 void dcm_mp_cpusys_top_apb_dcm(bool on); 40 bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void); 41 void dcm_mp_cpusys_top_bus_pll_div_dcm(bool on); 42 bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void); 43 void dcm_mp_cpusys_top_core_stall_dcm(bool on); 44 bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void); 45 void dcm_mp_cpusys_top_cpubiu_dcm(bool on); 46 bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void); 47 void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(bool on); 48 bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void); 49 void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(bool on); 50 bool dcm_mp_cpusys_top_cpu_pll_div_2_dcm_is_on(void); 51 void dcm_mp_cpusys_top_cpu_pll_div_2_dcm(bool on); 52 bool dcm_mp_cpusys_top_cpu_pll_div_3_dcm_is_on(void); 53 void dcm_mp_cpusys_top_cpu_pll_div_3_dcm(bool on); 54 bool dcm_mp_cpusys_top_cpu_pll_div_4_dcm_is_on(void); 55 void dcm_mp_cpusys_top_cpu_pll_div_4_dcm(bool on); 56 bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void); 57 void dcm_mp_cpusys_top_fcm_stall_dcm(bool on); 58 bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void); 59 void dcm_mp_cpusys_top_last_cor_idle_dcm(bool on); 60 bool dcm_mp_cpusys_top_misc_dcm_is_on(void); 61 void dcm_mp_cpusys_top_misc_dcm(bool on); 62 bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void); 63 void dcm_mp_cpusys_top_mp0_qdcm(bool on); 64 /* CPCCFG_REG */ 65 bool dcm_cpccfg_reg_emi_wfifo_is_on(void); 66 void dcm_cpccfg_reg_emi_wfifo(bool on); 67 68 #endif 69