1 /*
2  * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef BPMP_INTF_H
8 #define BPMP_INTF_H
9 
10 /**
11  * Flags used in IPC req
12  */
13 #define FLAG_DO_ACK			(U(1) << 0)
14 #define FLAG_RING_DOORBELL		(U(1) << 1)
15 
16 /* Bit 1 is designated for CCPlex in secure world */
17 #define HSP_MASTER_CCPLEX_BIT	(U(1) << 1)
18 /* Bit 19 is designated for BPMP in non-secure world */
19 #define HSP_MASTER_BPMP_BIT		(U(1) << 19)
20 /* Timeout to receive response from BPMP is 1 sec */
21 #define TIMEOUT_RESPONSE_FROM_BPMP_US	U(1000000) /* in microseconds */
22 
23 /**
24  * IVC protocol defines and command/response frame
25  */
26 
27 /**
28  * IVC specific defines
29  */
30 #define IVC_CMD_SZ_BYTES		U(128)
31 #define IVC_DATA_SZ_BYTES		U(120)
32 
33 /**
34  * Holds frame data for an IPC request
35  */
36 struct frame_data {
37 	/* Identification as to what kind of data is being transmitted */
38 	uint32_t mrq;
39 
40 	/* Flags for slave as to how to respond back */
41 	uint32_t flags;
42 
43 	/* Actual data being sent */
44 	uint8_t data[IVC_DATA_SZ_BYTES];
45 };
46 
47 /**
48  * Commands send to the BPMP firmware
49  */
50 
51 /**
52  * MRQ command codes
53  */
54 #define MRQ_RESET			U(20)
55 #define MRQ_CLK				U(22)
56 
57 /**
58  * Reset sub-commands
59  */
60 #define CMD_RESET_ASSERT		U(1)
61 #define CMD_RESET_DEASSERT		U(2)
62 #define CMD_RESET_MODULE		U(3)
63 
64 /**
65  * Used by the sender of an #MRQ_RESET message to request BPMP to
66  * assert or deassert a given reset line.
67  */
68 struct __attribute__((packed)) mrq_reset_request {
69 	/* reset action to perform (mrq_reset_commands) */
70 	uint32_t cmd;
71 	/* id of the reset to affected */
72 	uint32_t reset_id;
73 };
74 
75 /**
76  * MRQ_CLK sub-commands
77  *
78  */
79 enum {
80 	CMD_CLK_GET_RATE = U(1),
81 	CMD_CLK_SET_RATE = U(2),
82 	CMD_CLK_ROUND_RATE = U(3),
83 	CMD_CLK_GET_PARENT = U(4),
84 	CMD_CLK_SET_PARENT = U(5),
85 	CMD_CLK_IS_ENABLED = U(6),
86 	CMD_CLK_ENABLE = U(7),
87 	CMD_CLK_DISABLE = U(8),
88 	CMD_CLK_GET_ALL_INFO = U(14),
89 	CMD_CLK_GET_MAX_CLK_ID = U(15),
90 	CMD_CLK_MAX,
91 };
92 
93 /**
94  * Used by the sender of an #MRQ_CLK message to control clocks. The
95  * clk_request is split into several sub-commands. Some sub-commands
96  * require no additional data. Others have a sub-command specific
97  * payload
98  *
99  * |sub-command                 |payload                |
100  * |----------------------------|-----------------------|
101  * |CMD_CLK_GET_RATE            |-                      |
102  * |CMD_CLK_SET_RATE            |clk_set_rate           |
103  * |CMD_CLK_ROUND_RATE          |clk_round_rate         |
104  * |CMD_CLK_GET_PARENT          |-                      |
105  * |CMD_CLK_SET_PARENT          |clk_set_parent         |
106  * |CMD_CLK_IS_ENABLED          |-                      |
107  * |CMD_CLK_ENABLE              |-                      |
108  * |CMD_CLK_DISABLE             |-                      |
109  * |CMD_CLK_GET_ALL_INFO        |-                      |
110  * |CMD_CLK_GET_MAX_CLK_ID      |-                      |
111  *
112  */
113 struct mrq_clk_request {
114 	/**
115 	 * sub-command and clock id concatenated to 32-bit word.
116 	 * - bits[31..24] is the sub-cmd.
117 	 * - bits[23..0] is the clock id
118 	 */
119 	uint32_t cmd_and_id;
120 };
121 
122 /**
123  * Macro to prepare the MRQ_CLK sub-command
124  */
125 #define make_mrq_clk_cmd(cmd, id)	(((cmd) << 24) | (id & 0xFFFFFF))
126 
127 #endif /* BPMP_INTF_H */
128