1 /*
2  * Copyright (C) 2021 Marvell International Ltd.
3  *
4  * SPDX-License-Identifier:     BSD-3-Clause
5  * https://spdx.org/licenses
6  */
7 
8 #ifndef MSS_DEFS_H
9 #define MSS_DEFS_H
10 
11 #define MSS_DMA_SRCBR(base)		(base + 0xC0)
12 #define MSS_DMA_DSTBR(base)		(base + 0xC4)
13 #define MSS_DMA_CTRLR(base)		(base + 0xC8)
14 #define MSS_M3_RSTCR(base)		(base + 0xFC)
15 
16 #define MSS_DMA_CTRLR_SIZE_OFFSET	(0)
17 #define MSS_DMA_CTRLR_REQ_OFFSET	(15)
18 #define MSS_DMA_CTRLR_REQ_SET		(1)
19 #define MSS_DMA_CTRLR_ACK_OFFSET	(12)
20 #define MSS_DMA_CTRLR_ACK_MASK		(0x1)
21 #define MSS_DMA_CTRLR_ACK_READY		(1)
22 #define MSS_M3_RSTCR_RST_OFFSET		(0)
23 #define MSS_M3_RSTCR_RST_OFF		(1)
24 
25 #define MSS_FW_READY_MAGIC		0x46575144 /* FWRD */
26 
27 #define MSS_AP_REGS_OFFSET		0x00580000
28 #define MSS_CP_SRAM_OFFSET		0x00220000
29 #define MSS_CP_REGS_OFFSET		0x00280000
30 
31 void mss_start_cp_cm3(int cp);
32 
33 #endif /* MSS_DEFS_H */
34