1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> 5 */ 6 7 #ifndef __PINCTRL_MTK_COMMON_H 8 #define __PINCTRL_MTK_COMMON_H 9 10 #include <linux/pinctrl/pinctrl.h> 11 #include <linux/regmap.h> 12 #include <linux/pinctrl/pinconf-generic.h> 13 14 #include "mtk-eint.h" 15 16 #define NO_EINT_SUPPORT 255 17 #define MT_EDGE_SENSITIVE 0 18 #define MT_LEVEL_SENSITIVE 1 19 #define EINT_DBNC_SET_DBNC_BITS 4 20 #define EINT_DBNC_RST_BIT (0x1 << 1) 21 #define EINT_DBNC_SET_EN (0x1 << 0) 22 23 #define MTK_PINCTRL_NOT_SUPPORT (0xffff) 24 25 struct mtk_desc_function { 26 const char *name; 27 unsigned char muxval; 28 }; 29 30 struct mtk_desc_eint { 31 unsigned char eintmux; 32 unsigned char eintnum; 33 }; 34 35 struct mtk_desc_pin { 36 struct pinctrl_pin_desc pin; 37 const struct mtk_desc_eint eint; 38 const struct mtk_desc_function *functions; 39 }; 40 41 #define MTK_PIN(_pin, _pad, _chip, _eint, ...) \ 42 { \ 43 .pin = _pin, \ 44 .eint = _eint, \ 45 .functions = (struct mtk_desc_function[]){ \ 46 __VA_ARGS__, { } }, \ 47 } 48 49 #define MTK_EINT_FUNCTION(_eintmux, _eintnum) \ 50 { \ 51 .eintmux = _eintmux, \ 52 .eintnum = _eintnum, \ 53 } 54 55 #define MTK_FUNCTION(_val, _name) \ 56 { \ 57 .muxval = _val, \ 58 .name = _name, \ 59 } 60 61 #define SET_ADDR(x, y) (x + (y->devdata->port_align)) 62 #define CLR_ADDR(x, y) (x + (y->devdata->port_align << 1)) 63 64 struct mtk_pinctrl_group { 65 const char *name; 66 unsigned long config; 67 unsigned pin; 68 }; 69 70 /** 71 * struct mtk_drv_group_desc - Provide driving group data. 72 * @max_drv: The maximum current of this group. 73 * @min_drv: The minimum current of this group. 74 * @low_bit: The lowest bit of this group. 75 * @high_bit: The highest bit of this group. 76 * @step: The step current of this group. 77 */ 78 struct mtk_drv_group_desc { 79 unsigned char min_drv; 80 unsigned char max_drv; 81 unsigned char low_bit; 82 unsigned char high_bit; 83 unsigned char step; 84 }; 85 86 #define MTK_DRV_GRP(_min, _max, _low, _high, _step) \ 87 { \ 88 .min_drv = _min, \ 89 .max_drv = _max, \ 90 .low_bit = _low, \ 91 .high_bit = _high, \ 92 .step = _step, \ 93 } 94 95 /** 96 * struct mtk_pin_drv_grp - Provide each pin driving info. 97 * @pin: The pin number. 98 * @offset: The offset of driving register for this pin. 99 * @bit: The bit of driving register for this pin. 100 * @grp: The group for this pin belongs to. 101 */ 102 struct mtk_pin_drv_grp { 103 unsigned short pin; 104 unsigned short offset; 105 unsigned char bit; 106 unsigned char grp; 107 }; 108 109 #define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \ 110 { \ 111 .pin = _pin, \ 112 .offset = _offset, \ 113 .bit = _bit, \ 114 .grp = _grp, \ 115 } 116 117 /** 118 * struct mtk_pin_spec_pupd_set_samereg 119 * - For special pins' pull up/down setting which resides in same register 120 * @pin: The pin number. 121 * @offset: The offset of special pull up/down setting register. 122 * @pupd_bit: The pull up/down bit in this register. 123 * @r0_bit: The r0 bit of pull resistor. 124 * @r1_bit: The r1 bit of pull resistor. 125 */ 126 struct mtk_pin_spec_pupd_set_samereg { 127 unsigned short pin; 128 unsigned short offset; 129 unsigned char pupd_bit; 130 unsigned char r1_bit; 131 unsigned char r0_bit; 132 }; 133 134 #define MTK_PIN_PUPD_SPEC_SR(_pin, _offset, _pupd, _r1, _r0) \ 135 { \ 136 .pin = _pin, \ 137 .offset = _offset, \ 138 .pupd_bit = _pupd, \ 139 .r1_bit = _r1, \ 140 .r0_bit = _r0, \ 141 } 142 143 /** 144 * struct mtk_pin_ies_set - For special pins' ies and smt setting. 145 * @start: The start pin number of those special pins. 146 * @end: The end pin number of those special pins. 147 * @offset: The offset of special setting register. 148 * @bit: The bit of special setting register. 149 */ 150 struct mtk_pin_ies_smt_set { 151 unsigned short start; 152 unsigned short end; 153 unsigned short offset; 154 unsigned char bit; 155 }; 156 157 #define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \ 158 { \ 159 .start = _start, \ 160 .end = _end, \ 161 .bit = _bit, \ 162 .offset = _offset, \ 163 } 164 165 struct mtk_eint_offsets { 166 const char *name; 167 unsigned int stat; 168 unsigned int ack; 169 unsigned int mask; 170 unsigned int mask_set; 171 unsigned int mask_clr; 172 unsigned int sens; 173 unsigned int sens_set; 174 unsigned int sens_clr; 175 unsigned int soft; 176 unsigned int soft_set; 177 unsigned int soft_clr; 178 unsigned int pol; 179 unsigned int pol_set; 180 unsigned int pol_clr; 181 unsigned int dom_en; 182 unsigned int dbnc_ctrl; 183 unsigned int dbnc_set; 184 unsigned int dbnc_clr; 185 u8 port_mask; 186 u8 ports; 187 }; 188 189 /** 190 * struct mtk_pinctrl_devdata - Provide HW GPIO related data. 191 * @pins: An array describing all pins the pin controller affects. 192 * @npins: The number of entries in @pins. 193 * 194 * @grp_desc: The driving group info. 195 * @pin_drv_grp: The driving group for all pins. 196 * @spec_pull_set: Each SoC may have special pins for pull up/down setting, 197 * these pins' pull setting are very different, they have separate pull 198 * up/down bit, R0 and R1 resistor bit, so they need special pull setting. 199 * If special setting is success, this should return 0, otherwise it should 200 * return non-zero value. 201 * @spec_ies_smt_set: Some pins are irregular, their input enable and smt 202 * control register are discontinuous, but they are mapping together. That 203 * means when user set smt, input enable is set at the same time. So they 204 * also need special control. If special control is success, this should 205 * return 0, otherwise return non-zero value. 206 * @spec_pinmux_set: In some cases, there are two pinmux functions share 207 * the same value in the same segment of pinmux control register. If user 208 * want to use one of the two functions, they need an extra bit setting to 209 * select the right one. 210 * @spec_dir_set: In very few SoCs, direction control registers are not 211 * arranged continuously, they may be cut to parts. So they need special 212 * dir setting. 213 214 * @dir_offset: The direction register offset. 215 * @pullen_offset: The pull-up/pull-down enable register offset. 216 * @pinmux_offset: The pinmux register offset. 217 * 218 * @type1_start: Some chips have two base addresses for pull select register, 219 * that means some pins use the first address and others use the second. This 220 * member record the start of pin number to use the second address. 221 * @type1_end: The end of pin number to use the second address. 222 * 223 * @port_shf: The shift between two registers. 224 * @port_mask: The mask of register. 225 * @port_align: Provide clear register and set register step. 226 */ 227 struct mtk_pinctrl_devdata { 228 const struct mtk_desc_pin *pins; 229 unsigned int npins; 230 const struct mtk_drv_group_desc *grp_desc; 231 unsigned int n_grp_cls; 232 const struct mtk_pin_drv_grp *pin_drv_grp; 233 unsigned int n_pin_drv_grps; 234 int (*spec_pull_set)(struct regmap *reg, unsigned int pin, 235 unsigned char align, bool isup, unsigned int arg); 236 int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin, 237 unsigned char align, int value, enum pin_config_param arg); 238 void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin, 239 unsigned int mode); 240 void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin); 241 unsigned int dir_offset; 242 unsigned int ies_offset; 243 unsigned int smt_offset; 244 unsigned int pullen_offset; 245 unsigned int pullsel_offset; 246 unsigned int drv_offset; 247 unsigned int dout_offset; 248 unsigned int din_offset; 249 unsigned int pinmux_offset; 250 unsigned short type1_start; 251 unsigned short type1_end; 252 unsigned char port_shf; 253 unsigned char port_mask; 254 unsigned char port_align; 255 struct mtk_eint_hw eint_hw; 256 struct mtk_eint_regs *eint_regs; 257 unsigned int mode_mask; 258 unsigned int mode_per_reg; 259 unsigned int mode_shf; 260 }; 261 262 struct mtk_pinctrl { 263 struct regmap *regmap1; 264 struct regmap *regmap2; 265 struct pinctrl_desc pctl_desc; 266 struct device *dev; 267 struct gpio_chip *chip; 268 struct mtk_pinctrl_group *groups; 269 unsigned ngroups; 270 const char **grp_names; 271 struct pinctrl_dev *pctl_dev; 272 const struct mtk_pinctrl_devdata *devdata; 273 struct mtk_eint *eint; 274 }; 275 276 int mtk_pctrl_init(struct platform_device *pdev, 277 const struct mtk_pinctrl_devdata *data, 278 struct regmap *regmap); 279 280 int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, 281 const struct mtk_pin_spec_pupd_set_samereg *pupd_infos, 282 unsigned int info_num, unsigned int pin, 283 unsigned char align, bool isup, unsigned int r1r0); 284 285 int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, 286 const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num, 287 unsigned int pin, unsigned char align, int value); 288 289 extern const struct dev_pm_ops mtk_eint_pm_ops; 290 291 #endif /* __PINCTRL_MTK_COMMON_H */ 292