1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * (C) Copyright 2013
4 * David Feng <fenghua@phytium.com.cn>
5 */
6
7 #ifndef _ASM_ARMV8_MMU_H_
8 #define _ASM_ARMV8_MMU_H_
9
10 #include <hang.h>
11 #include <linux/const.h>
12
13 /*
14 * block/section address mask and size definitions.
15 */
16
17 /* PAGE_SHIFT determines the page size */
18 #undef PAGE_SIZE
19 #define PAGE_SHIFT 12
20 #define PAGE_SIZE (1 << PAGE_SHIFT)
21 #define PAGE_MASK (~(PAGE_SIZE - 1))
22
23 /***************************************************************/
24
25 /*
26 * Memory types
27 */
28 #define MT_DEVICE_NGNRNE 0
29 #define MT_DEVICE_NGNRE 1
30 #define MT_DEVICE_GRE 2
31 #define MT_NORMAL_NC 3
32 #define MT_NORMAL 4
33
34 #define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \
35 (0x04 << (MT_DEVICE_NGNRE * 8)) | \
36 (0x0c << (MT_DEVICE_GRE * 8)) | \
37 (0x44 << (MT_NORMAL_NC * 8)) | \
38 (UL(0xff) << (MT_NORMAL * 8)))
39
40 /*
41 * Hardware page table definitions.
42 *
43 */
44
45 #define PTE_TYPE_MASK (3 << 0)
46 #define PTE_TYPE_FAULT (0 << 0)
47 #define PTE_TYPE_TABLE (3 << 0)
48 #define PTE_TYPE_PAGE (3 << 0)
49 #define PTE_TYPE_BLOCK (1 << 0)
50 #define PTE_TYPE_VALID (1 << 0)
51
52 #define PTE_TABLE_PXN (1UL << 59)
53 #define PTE_TABLE_XN (1UL << 60)
54 #define PTE_TABLE_AP (1UL << 61)
55 #define PTE_TABLE_NS (1UL << 63)
56
57 /*
58 * Block
59 */
60 #define PTE_BLOCK_MEMTYPE(x) ((x) << 2)
61 #define PTE_BLOCK_NS (1 << 5)
62 #define PTE_BLOCK_NON_SHARE (0 << 8)
63 #define PTE_BLOCK_OUTER_SHARE (2 << 8)
64 #define PTE_BLOCK_INNER_SHARE (3 << 8)
65 #define PTE_BLOCK_AF (1 << 10)
66 #define PTE_BLOCK_NG (1 << 11)
67 #define PTE_BLOCK_PXN (UL(1) << 53)
68 #define PTE_BLOCK_UXN (UL(1) << 54)
69
70 /*
71 * AttrIndx[2:0]
72 */
73 #define PMD_ATTRINDX(t) ((t) << 2)
74 #define PMD_ATTRINDX_MASK (7 << 2)
75 #define PMD_ATTRMASK (PTE_BLOCK_PXN | \
76 PTE_BLOCK_UXN | \
77 PMD_ATTRINDX_MASK | \
78 PTE_TYPE_VALID)
79
80 /*
81 * TCR flags.
82 */
83 #define TCR_T0SZ(x) ((64 - (x)) << 0)
84 #define TCR_IRGN_NC (0 << 8)
85 #define TCR_IRGN_WBWA (1 << 8)
86 #define TCR_IRGN_WT (2 << 8)
87 #define TCR_IRGN_WBNWA (3 << 8)
88 #define TCR_IRGN_MASK (3 << 8)
89 #define TCR_ORGN_NC (0 << 10)
90 #define TCR_ORGN_WBWA (1 << 10)
91 #define TCR_ORGN_WT (2 << 10)
92 #define TCR_ORGN_WBNWA (3 << 10)
93 #define TCR_ORGN_MASK (3 << 10)
94 #define TCR_SHARED_NON (0 << 12)
95 #define TCR_SHARED_OUTER (2 << 12)
96 #define TCR_SHARED_INNER (3 << 12)
97 #define TCR_TG0_4K (0 << 14)
98 #define TCR_TG0_64K (1 << 14)
99 #define TCR_TG0_16K (2 << 14)
100 #define TCR_EPD1_DISABLE (1 << 23)
101
102 #define TCR_EL1_RSVD (1 << 31)
103 #define TCR_EL2_RSVD (1 << 31 | 1 << 23)
104 #define TCR_EL3_RSVD (1 << 31 | 1 << 23)
105
106 #ifndef __ASSEMBLY__
set_ttbr_tcr_mair(int el,u64 table,u64 tcr,u64 attr)107 static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
108 {
109 asm volatile("dsb sy");
110 if (el == 1) {
111 asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
112 asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
113 asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
114 } else if (el == 2) {
115 asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
116 asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
117 asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
118 } else if (el == 3) {
119 asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
120 asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
121 asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
122 } else {
123 hang();
124 }
125 asm volatile("isb");
126 }
127
128 struct mm_region {
129 u64 virt;
130 u64 phys;
131 u64 size;
132 u64 attrs;
133 };
134
135 extern struct mm_region *mem_map;
136 void setup_pgtables(void);
137 u64 get_tcr(int el, u64 *pips, u64 *pva_bits);
138 #endif
139
140 #endif /* _ASM_ARMV8_MMU_H_ */
141