1 /*
2  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <stdint.h>
8 
9 #define MU_ATR0_OFFSET1		0x0
10 #define MU_ARR0_OFFSET1		0x10
11 #define MU_ASR_OFFSET1		0x20
12 #define MU_ACR_OFFSET1		0x24
13 #define MU_TR_COUNT1		4
14 #define MU_RR_COUNT1		4
15 
16 #define MU_CR_GIEn_MASK1	(0xFu << 28)
17 #define MU_CR_RIEn_MASK1	(0xF << 24)
18 #define MU_CR_TIEn_MASK1	(0xF << 20)
19 #define MU_CR_GIRn_MASK1	(0xF << 16)
20 #define MU_CR_NMI_MASK1		(1 << 3)
21 #define MU_CR_Fn_MASK1		0x7
22 
23 #define MU_SR_TE0_MASK1		(1 << 23)
24 #define MU_SR_RF0_MASK1		(1 << 27)
25 #define MU_CR_RIE0_MASK1	(1 << 27)
26 #define MU_CR_GIE0_MASK1	(1U << 31)
27 
28 #define MU_TR_COUNT			4
29 #define MU_RR_COUNT			4
30 
31 void MU_Init(uint32_t base);
32 void MU_SendMessage(uint32_t base, uint32_t regIndex, uint32_t msg);
33 void MU_ReceiveMsg(uint32_t base, uint32_t regIndex, uint32_t *msg);
34 void MU_EnableGeneralInt(uint32_t base, uint32_t index);
35 void MU_EnableRxFullInt(uint32_t base, uint32_t index);
36 void MU_Resume(uint32_t base);
37