1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef IMX_REGS_H 8 #define IMX_REGS_H 9 10 /* Define the processor memory map */ 11 12 #define OCRAM_S_ALIAS_BASE 0x00000000 /* CM4 Alias Code */ 13 #define ROM_HIGH_BASE 0x00008000 /* ROM high 64k */ 14 #define ROM_HIGH_PROT_BASE 0x00017000 /* ROM high 64k protected */ 15 #define CAAM_BASE 0x00020000 /* CAAM block base address */ 16 #define OCRAM_S_BASE 0x00180000 /* OCRAM_S */ 17 #define ROM_LOW_BASE 0x007f8000 /* ROM low 64k */ 18 #define OCRAM_BASE 0x00900000 /* OCRAM base */ 19 #define CM4_ALIAS_CODE_BASE 0x04000000 /* CM4 alias code */ 20 #define TCM_BASE 0x1fff0000 /* TCM */ 21 #define BOOTROM_CP_BASE 0x20020000 /* Boot ROM (all 96KB) */ 22 #define CM4_ALIAS_SYSTEM_BASE 0x20100000 /* CM4 Alias system */ 23 #define EIM_BASE 0x28000000 /* EIM */ 24 25 /* BootROM absolute base address */ 26 #define BOOTROM_BASE 0x00000000 /* BootROM */ 27 28 /* Peripherals like GPIO live in the AIPS range */ 29 #define AIPS1_BASE 0x30000000 /* AIPS1 */ 30 #define AIPS2_BASE 0x30400000 /* AIPS2 */ 31 #define AIPS3_BASE 0x30800000 /* AIPS3 */ 32 #define AIPS4_BASE 0x30c00000 /* AIPS4 */ 33 34 /* ARM peripherals like GIC */ 35 #define ARM_PERIPHERAL_GIC_BASE 0x31000000 /* GIC */ 36 37 /* Configuration ports */ 38 #define GPV0_BASE 0x32000000 /* Main config port */ 39 #define GPV1_BASE 0x32100000 /* Wakeup config port */ 40 #define GPV2_BASE 0x32200000 /* Per_s config port */ 41 #define GPV3_BASE 0x32300000 /* Per_m config port */ 42 #define GPV4_BASE 0x32400000 /* Enet config port */ 43 #define GPV5_BASE 0x32500000 /* Display config port */ 44 #define GPV6_BASE 0x32600000 /* M4 conig port */ 45 46 /* MMAP peripherals - like APBH DMA */ 47 #define APBH_DMA_BASE 0x33000000 /* APBH DMA block */ 48 49 /* QSPI RX BUFFERS */ 50 #define QSPI_RX_BUFFER_BASE 0x34000000 /* QSPI RX buffers */ 51 52 /* QSPI1 FLASH */ 53 #define QSPI_FLASH_BASE 0x60000000 /* QSPI1 flash */ 54 55 /* AIPS1 block addresses */ 56 #define AIPSTZ_CONFIG_OFFSET 0x001f0000 57 #define CCM_BASE (AIPS1_BASE + 0x380000) 58 59 /* Define the maximum number of UART blocks on this SoC */ 60 #define MXC_UART1_BASE (AIPS3_BASE + 0x060000) 61 #define MXC_UART2_BASE (AIPS3_BASE + 0x070000) 62 #define MXC_UART3_BASE (AIPS3_BASE + 0x080000) 63 #define MXC_UART4_BASE (AIPS3_BASE + 0x260000) 64 #define MXC_UART5_BASE (AIPS3_BASE + 0x270000) 65 #define MXC_UART6_BASE (AIPS3_BASE + 0x280000) 66 #define MXC_UART7_BASE (AIPS3_BASE + 0x290000) 67 #define MXC_MAX_UART_NUM 0x07 68 69 /* Define the maximum number of USDHCI blocks on this SoC */ 70 #define MXC_MAX_USDHC_NUM 3 71 72 /* Define the number of CSU registers for this SoC */ 73 #define MXC_MAX_CSU_REGS 0x40 74 #define CSU_BASE (AIPS1_BASE + 0x3E0000) 75 76 /* IO Mux block base */ 77 #define MXC_IO_MUXC_BASE (AIPS1_BASE + 0x330000) 78 79 /* SNVS base */ 80 #define SNVS_BASE (AIPS1_BASE + 0x370000) 81 82 /* GP Timer base */ 83 #define GPT1_BASE_ADDR (AIPS1_BASE + 0x2d0000) 84 85 /* MMC base */ 86 #define USDHC1_BASE (AIPS1_BASE + 0xb40000) 87 #define USDHC2_BASE (AIPS1_BASE + 0xb50000) 88 #define USDHC3_BASE (AIPS1_BASE + 0xb60000) 89 90 /* Arm optional memory mapped counter module base address */ 91 #define SYS_CNTCTL_BASE (AIPS2_BASE + 0x2c0000) 92 93 /* Define CAAM AIPS offset */ 94 #define CAAM_AIPS_BASE (AIPS3_BASE + 0x100000) 95 #define CAAM_NUM_JOB_RINGS 0x03 96 #define CAAM_NUM_RTIC 0x04 97 #define CAAM_NUM_DECO 0x01 98 99 /* Define watchdog base addresses */ 100 #define WDOG1_BASE (AIPS1_BASE + 0x280000) 101 #define WDOG2_BASE (AIPS1_BASE + 0x290000) 102 #define WDOG3_BASE (AIPS1_BASE + 0x2A0000) 103 #define WDOG4_BASE (AIPS1_BASE + 0x280000) 104 105 /* Define the maximum number of WDOG blocks on this SoC */ 106 #define MXC_MAX_WDOG_NUM 0x04 107 108 #endif /* IMX_REGS_H */ 109