1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright 2018-2021 NXP 4 * 5 * Brief Define the CCB Registers to use in the CAAM descriptor 6 */ 7 #ifndef __CAAM_DESC_CCB_DEFINES_H__ 8 #define __CAAM_DESC_CCB_DEFINES_H__ 9 10 /* CCB CHA Control Register */ 11 #define CCTRL_ULOAD_PKHA_B BIT32(27) 12 #define CCTRL_ULOAD_PKHA_A BIT32(26) 13 14 /* CCB Clear Written Register */ 15 #define CLR_WR_IFIFO_NFIFO BIT32(31) 16 #define CLR_WR_RST_C2_CHA BIT32(28) 17 #define CLR_WR_RST_C2_DSZ BIT32(18) 18 19 /* CCB NFIFO */ 20 #define NFIFO_CLASS(cla) SHIFT_U32(NFIFO_CLASS_##cla & 0x3, 30) 21 #define NFIFO_CLASS_DECO 0x0 22 #define NFIFO_CLASS_C1 0x1 23 #define NFIFO_CLASS_BOTH 0x3 24 25 #define NFIFO_LC2 BIT32(29) 26 #define NFIFO_LC1 BIT32(28) 27 #define NFIFO_FC1 BIT32(26) 28 29 #define NFIFO_STYPE(src) SHIFT_U32(NFIFO_STYPE_##src & 0x3, 24) 30 #define NFIFO_STYPE_IFIFO 0x0 31 #define NFIFO_STYPE_PAD 0x2 32 33 #define NFIFO_DTYPE(data) SHIFT_U32(NFIFO_DTYPE_##data & 0xF, 20) 34 #define NFIFO_DTYPE_MSG 0xF 35 #define NFIFO_DTYPE_PKHA_N 0x8 36 #define NFIFO_DTYPE_PKHA_A 0xC 37 38 #define NFIFO_PTYPE(pad) SHIFT_U32(NFIFO_PTYPE_##pad & 0x7, 16) 39 #define NFIFO_PTYPE_ZERO 0x0 40 #define NFIFO_PTYPE_RND 0x3 41 42 #define NFIFO_DATA_LENGTH(len) SHIFT_U32((len) & 0xFFF, 0) 43 #define NFIFO_PAD_LENGTH(len) SHIFT_U32((len) & 0x7F, 0) 44 45 /* 46 * CCB NFIFO Entry to pad data with pad type 47 */ 48 #define NFIFO_PAD(cla, options, data, pad, len) \ 49 (NFIFO_CLASS(cla) | (options) | NFIFO_STYPE(PAD) | NFIFO_DTYPE(data) | \ 50 NFIFO_PTYPE(pad) | NFIFO_PAD_LENGTH(len)) 51 52 /* 53 * CCB NFIFO Entry to move data from src to data 54 */ 55 #define NFIFO_NOPAD(cla, options, src, data, len) \ 56 (NFIFO_CLASS(cla) | (options) | NFIFO_STYPE(src) | NFIFO_DTYPE(data) | \ 57 NFIFO_PTYPE(ZERO) | NFIFO_DATA_LENGTH(len)) 58 59 #endif /* __CAAM_DESC_CCB_DEFINES_H__ */ 60