1 /* 2 * Copyright 2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef SNVS_H 9 #define SNVS_H 10 11 12 #ifndef __ASSEMBLER__ 13 14 #include <endian.h> 15 #include <stdbool.h> 16 17 #include <lib/mmio.h> 18 19 struct snvs_regs { 20 uint32_t reserved1; 21 uint32_t hp_com; /* 0x04 SNVS_HP Command Register */ 22 uint32_t reserved2[3]; 23 uint32_t hp_stat; /* 0x14 SNVS_HP Status Register */ 24 }; 25 26 #ifdef NXP_SNVS_BE 27 #define snvs_read32(a) bswap32(mmio_read_32((uintptr_t)(a))) 28 #define snvs_write32(a, v) mmio_write_32((uintptr_t)(a), bswap32((v))) 29 #elif defined(NXP_SNVS_LE) 30 #define snvs_read32(a) mmio_read_32((uintptr_t)(a)) 31 #define snvs_write32(a, v) mmio_write_32((uintptr_t)(a), (v)) 32 #else 33 #error Please define CCSR SNVS register endianness 34 #endif 35 36 void snvs_init(uintptr_t nxp_snvs_addr); 37 uint32_t get_snvs_state(void); 38 void transition_snvs_non_secure(void); 39 void transition_snvs_soft_fail(void); 40 uint32_t transition_snvs_trusted(void); 41 uint32_t transition_snvs_secure(void); 42 43 uint32_t snvs_read_lp_gpr_bit(uint32_t offset, uint32_t bit_pos); 44 void snvs_write_lp_gpr_bit(uint32_t offset, uint32_t bit_pos, bool flag_val); 45 46 void snvs_disable_zeroize_lp_gpr(void); 47 48 #if defined(NXP_NV_SW_MAINT_LAST_EXEC_DATA) && defined(NXP_COINED_BB) 49 uint32_t snvs_read_app_data(void); 50 uint32_t snvs_read_app_data_bit(uint32_t bit_pos); 51 void snvs_clear_app_data(void); 52 void snvs_write_app_data_bit(uint32_t bit_pos); 53 #endif 54 55 #endif /* __ASSEMBLER__ */ 56 57 /* SSM_ST field in SNVS status reg */ 58 #define HPSTS_CHECK_SSM_ST 0x900 /* SNVS is in check state */ 59 #define HPSTS_NON_SECURE_SSM_ST 0xb00 /* SNVS is in non secure state */ 60 #define HPSTS_TRUST_SSM_ST 0xd00 /* SNVS is in trusted state */ 61 #define HPSTS_SECURE_SSM_ST 0xf00 /* SNVS is in secure state */ 62 #define HPSTS_SOFT_FAIL_SSM_ST 0x300 /* SNVS is in soft fail state */ 63 #define HPSTS_MASK_SSM_ST 0xf00 /* SSM_ST field mask in SNVS reg */ 64 65 /* SNVS register bits */ 66 #define HPCOM_SW_SV 0x100 /* Security Violation bit */ 67 #define HPCOM_SW_FSV 0x200 /* Fatal Security Violation bit */ 68 #define HPCOM_SSM_ST 0x1 /* SSM_ST field in SNVS command reg */ 69 #define HPCOM_SSM_ST_DIS 0x2 /* Disable Secure to Trusted State */ 70 #define HPCOM_SSM_SFNS_DIS 0x4 /* Disable Soft Fail to Non-Secure */ 71 72 #define NXP_LP_GPR0_OFFSET 0x90 73 #define NXP_LPCR_OFFSET 0x38 74 #define NXP_GPR_Z_DIS_BIT 24 75 76 #ifdef NXP_COINED_BB 77 78 #ifndef NXP_APP_DATA_LP_GPR_OFFSET 79 #define NXP_APP_DATA_LP_GPR_OFFSET NXP_LP_GPR0_OFFSET 80 #endif 81 82 #define NXP_LPGPR_ZEROTH_BIT 0 83 84 #endif /* NXP_COINED_BB */ 85 86 #endif /* SNVS_H */ 87