1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright 2017-2019 NXP 4 */ 5 6 #ifndef __IMX8M_H__ 7 #define __IMX8M_H__ 8 9 #include <registers/imx8m-crm.h> 10 11 #define GICD_BASE 0x38800000 12 #define GICR_BASE 0x38880000 13 #define UART1_BASE 0x30860000 14 #define UART2_BASE 0x30890000 15 #define UART3_BASE 0x30880000 16 #define UART4_BASE 0x30A60000 17 #define TZASC_BASE 0x32F80000 18 #define CAAM_BASE 0x30900000 19 #define CCM_BASE 0x30380000 20 #define CCM_SIZE 0x10000 21 #define ANATOP_BASE 0x30360000 22 #define IOMUXC_BASE 0x30330000 23 #define OCOTP_BASE 0x30350000 24 #define OCOTP_SIZE 0x10000 25 #define SNVS_BASE 0x30370000 26 27 #ifdef CFG_MX8MQ 28 #define DIGPROG_OFFSET 0x06c 29 #define OCOTP_SW_INFO_B1 0x40 30 #define OCOTP_SW_MAGIC_B1 0xFF0055AA 31 #endif 32 #if defined(CFG_MX8MM) || defined(CFG_MX8MN) || defined(CFG_MX8MP) 33 #define DIGPROG_OFFSET 0x800 34 #endif 35 36 #if defined(CFG_MX8MM) || defined(CFG_MX8MQ) 37 #define I2C1_BASE 0x30a20000 38 #define I2C2_BASE 0x30a30000 39 #define I2C3_BASE 0x30a40000 40 #define I2C4_BASE 0x30a50000 41 42 #define IOMUXC_I2C1_SCL_CFG_OFF 0x47C 43 #define IOMUXC_I2C1_SDA_CFG_OFF 0x480 44 #define IOMUXC_I2C1_SCL_MUX_OFF 0x214 45 #define IOMUXC_I2C1_SDA_MUX_OFF 0x218 46 #endif 47 48 #endif /* __IMX8M_H__ */ 49