1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell.
5 *
6 */
7
8 #ifndef MBOX_H
9 #define MBOX_H
10
11 #include <linux/etherdevice.h>
12 #include <linux/sizes.h>
13
14 #include "rvu_struct.h"
15 #include "common.h"
16
17 #define MBOX_SIZE SZ_64K
18
19 /* AF/PF: PF initiated, PF/VF VF initiated */
20 #define MBOX_DOWN_RX_START 0
21 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K)
22 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
23 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K)
24 /* AF/PF: AF initiated, PF/VF PF initiated */
25 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
26 #define MBOX_UP_RX_SIZE SZ_1K
27 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
28 #define MBOX_UP_TX_SIZE SZ_1K
29
30 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
31 # error "incorrect mailbox area sizes"
32 #endif
33
34 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
35
36 #define MBOX_RSP_TIMEOUT 3000 /* Time(ms) to wait for mbox response */
37
38 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */
39
40 /* Mailbox directions */
41 #define MBOX_DIR_AFPF 0 /* AF replies to PF */
42 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */
43 #define MBOX_DIR_PFVF 2 /* PF replies to VF */
44 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */
45 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */
46 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */
47 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */
48 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */
49
50 struct otx2_mbox_dev {
51 void *mbase; /* This dev's mbox region */
52 void *hwbase;
53 spinlock_t mbox_lock;
54 u16 msg_size; /* Total msg size to be sent */
55 u16 rsp_size; /* Total rsp size to be sure the reply is ok */
56 u16 num_msgs; /* No of msgs sent or waiting for response */
57 u16 msgs_acked; /* No of msgs for which response is received */
58 };
59
60 struct otx2_mbox {
61 struct pci_dev *pdev;
62 void *hwbase; /* Mbox region advertised by HW */
63 void *reg_base;/* CSR base for this dev */
64 u64 trigger; /* Trigger mbox notification */
65 u16 tr_shift; /* Mbox trigger shift */
66 u64 rx_start; /* Offset of Rx region in mbox memory */
67 u64 tx_start; /* Offset of Tx region in mbox memory */
68 u16 rx_size; /* Size of Rx region */
69 u16 tx_size; /* Size of Tx region */
70 u16 ndevs; /* The number of peers */
71 struct otx2_mbox_dev *dev;
72 };
73
74 /* Header which precedes all mbox messages */
75 struct mbox_hdr {
76 u64 msg_size; /* Total msgs size embedded */
77 u16 num_msgs; /* No of msgs embedded */
78 };
79
80 /* Header which precedes every msg and is also part of it */
81 struct mbox_msghdr {
82 u16 pcifunc; /* Who's sending this msg */
83 u16 id; /* Mbox message ID */
84 #define OTX2_MBOX_REQ_SIG (0xdead)
85 #define OTX2_MBOX_RSP_SIG (0xbeef)
86 u16 sig; /* Signature, for validating corrupted msgs */
87 #define OTX2_MBOX_VERSION (0x000a)
88 u16 ver; /* Version of msg's structure for this ID */
89 u16 next_msgoff; /* Offset of next msg within mailbox region */
90 int rc; /* Msg process'ed response code */
91 };
92
93 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
94 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
95 void otx2_mbox_destroy(struct otx2_mbox *mbox);
96 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase,
97 struct pci_dev *pdev, void __force *reg_base,
98 int direction, int ndevs);
99 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase,
100 struct pci_dev *pdev, void __force *reg_base,
101 int direction, int ndevs);
102 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
103 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
104 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid);
105 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
106 int size, int size_rsp);
107 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid,
108 struct mbox_msghdr *msg);
109 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid);
110 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid,
111 u16 pcifunc, u16 id);
112 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid);
113 const char *otx2_mbox_id2name(u16 id);
otx2_mbox_alloc_msg(struct otx2_mbox * mbox,int devid,int size)114 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox,
115 int devid, int size)
116 {
117 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
118 }
119
120 /* Mailbox message types */
121 #define MBOX_MSG_MASK 0xFFFF
122 #define MBOX_MSG_INVALID 0xFFFE
123 #define MBOX_MSG_MAX 0xFFFF
124
125 #define MBOX_MESSAGES \
126 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \
127 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
128 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \
129 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \
130 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \
131 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
132 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
133 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
134 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
135 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \
136 msg_rsp) \
137 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \
138 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \
139 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
140 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
141 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
142 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \
143 cgx_mac_addr_set_or_get) \
144 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \
145 cgx_mac_addr_set_or_get) \
146 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
147 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
148 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
149 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
150 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \
151 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
152 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
153 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
154 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
155 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
156 cgx_pause_frm_cfg) \
157 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
158 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \
159 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \
160 cgx_mac_addr_add_rsp) \
161 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \
162 msg_rsp) \
163 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \
164 cgx_max_dmac_entries_get_rsp) \
165 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
166 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\
167 cgx_set_link_mode_rsp) \
168 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \
169 M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req, \
170 cgx_features_info_msg) \
171 M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \
172 M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, msg_req, msg_rsp) \
173 M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \
174 msg_rsp) \
175 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \
176 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \
177 npa_lf_alloc_req, npa_lf_alloc_rsp) \
178 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
179 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \
180 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
181 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
182 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \
183 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
184 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \
185 msg_rsp) \
186 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \
187 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
188 cpt_rd_wr_reg_msg) \
189 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \
190 cpt_inline_ipsec_cfg_msg, msg_rsp) \
191 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \
192 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \
193 msg_rsp) \
194 M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \
195 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \
196 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \
197 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \
198 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
199 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\
200 npc_mcam_alloc_entry_rsp) \
201 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
202 npc_mcam_free_entry_req, msg_rsp) \
203 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
204 npc_mcam_write_entry_req, msg_rsp) \
205 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
206 npc_mcam_ena_dis_entry_req, msg_rsp) \
207 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
208 npc_mcam_ena_dis_entry_req, msg_rsp) \
209 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\
210 npc_mcam_shift_entry_rsp) \
211 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
212 npc_mcam_alloc_counter_req, \
213 npc_mcam_alloc_counter_rsp) \
214 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
215 npc_mcam_oper_counter_req, msg_rsp) \
216 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
217 npc_mcam_unmap_counter_req, msg_rsp) \
218 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
219 npc_mcam_oper_counter_req, msg_rsp) \
220 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
221 npc_mcam_oper_counter_req, \
222 npc_mcam_oper_counter_rsp) \
223 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \
224 npc_mcam_alloc_and_write_entry_req, \
225 npc_mcam_alloc_and_write_entry_rsp) \
226 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \
227 msg_req, npc_get_kex_cfg_rsp) \
228 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \
229 npc_install_flow_req, npc_install_flow_rsp) \
230 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \
231 npc_delete_flow_req, msg_rsp) \
232 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
233 npc_mcam_read_entry_req, \
234 npc_mcam_read_entry_rsp) \
235 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \
236 npc_set_pkind, msg_rsp) \
237 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \
238 msg_req, npc_mcam_read_base_rule_rsp) \
239 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \
240 npc_mcam_get_stats_req, \
241 npc_mcam_get_stats_rsp) \
242 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
243 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \
244 nix_lf_alloc_req, nix_lf_alloc_rsp) \
245 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
246 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \
247 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \
248 hwctx_disable_req, msg_rsp) \
249 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \
250 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \
251 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
252 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \
253 nix_txschq_config) \
254 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
255 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \
256 nix_vtag_config_rsp) \
257 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
258 nix_rss_flowkey_cfg, \
259 nix_rss_flowkey_cfg_rsp) \
260 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \
261 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
262 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
263 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
264 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
265 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
266 nix_mark_format_cfg, \
267 nix_mark_format_cfg_rsp) \
268 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
269 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \
270 nix_lso_format_cfg, \
271 nix_lso_format_cfg_rsp) \
272 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \
273 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \
274 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
275 nix_bp_cfg_rsp) \
276 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \
277 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \
278 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \
279 nix_inline_ipsec_cfg, msg_rsp) \
280 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \
281 nix_inline_ipsec_lf_cfg, msg_rsp) \
282 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \
283 nix_cn10k_aq_enq_rsp) \
284 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \
285 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \
286 nix_bandprof_alloc_rsp) \
287 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \
288 msg_rsp) \
289 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \
290 nix_bandprof_get_hwinfo_rsp)
291
292 /* Messages initiated by AF (range 0xC00 - 0xDFF) */
293 #define MBOX_UP_CGX_MESSAGES \
294 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp)
295
296 #define MBOX_UP_CPT_MESSAGES \
297 M(CPT_INST_LMTST, 0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp)
298
299 enum {
300 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
301 MBOX_MESSAGES
302 MBOX_UP_CGX_MESSAGES
303 MBOX_UP_CPT_MESSAGES
304 #undef M
305 };
306
307 /* Mailbox message formats */
308
309 #define RVU_DEFAULT_PF_FUNC 0xFFFF
310
311 /* Generic request msg used for those mbox messages which
312 * don't send any data in the request.
313 */
314 struct msg_req {
315 struct mbox_msghdr hdr;
316 };
317
318 /* Generic response msg used an ack or response for those mbox
319 * messages which don't have a specific rsp msg format.
320 */
321 struct msg_rsp {
322 struct mbox_msghdr hdr;
323 };
324
325 /* RVU mailbox error codes
326 * Range 256 - 300.
327 */
328 enum rvu_af_status {
329 RVU_INVALID_VF_ID = -256,
330 };
331
332 struct ready_msg_rsp {
333 struct mbox_msghdr hdr;
334 u16 sclk_freq; /* SCLK frequency (in MHz) */
335 u16 rclk_freq; /* RCLK frequency (in MHz) */
336 };
337
338 /* Structure for requesting resource provisioning.
339 * 'modify' flag to be used when either requesting more
340 * or to detach partial of a certain resource type.
341 * Rest of the fields specify how many of what type to
342 * be attached.
343 * To request LFs from two blocks of same type this mailbox
344 * can be sent twice as below:
345 * struct rsrc_attach *attach;
346 * .. Allocate memory for message ..
347 * attach->cptlfs = 3; <3 LFs from CPT0>
348 * .. Send message ..
349 * .. Allocate memory for message ..
350 * attach->modify = 1;
351 * attach->cpt_blkaddr = BLKADDR_CPT1;
352 * attach->cptlfs = 2; <2 LFs from CPT1>
353 * .. Send message ..
354 */
355 struct rsrc_attach {
356 struct mbox_msghdr hdr;
357 u8 modify:1;
358 u8 npalf:1;
359 u8 nixlf:1;
360 u16 sso;
361 u16 ssow;
362 u16 timlfs;
363 u16 cptlfs;
364 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
365 };
366
367 /* Structure for relinquishing resources.
368 * 'partial' flag to be used when relinquishing all resources
369 * but only of a certain type. If not set, all resources of all
370 * types provisioned to the RVU function will be detached.
371 */
372 struct rsrc_detach {
373 struct mbox_msghdr hdr;
374 u8 partial:1;
375 u8 npalf:1;
376 u8 nixlf:1;
377 u8 sso:1;
378 u8 ssow:1;
379 u8 timlfs:1;
380 u8 cptlfs:1;
381 };
382
383 /* Number of resources available to the caller.
384 * In reply to MBOX_MSG_FREE_RSRC_CNT.
385 */
386 struct free_rsrcs_rsp {
387 struct mbox_msghdr hdr;
388 u16 schq[NIX_TXSCH_LVL_CNT];
389 u16 sso;
390 u16 tim;
391 u16 ssow;
392 u16 cpt;
393 u8 npa;
394 u8 nix;
395 u16 schq_nix1[NIX_TXSCH_LVL_CNT];
396 u8 nix1;
397 u8 cpt1;
398 u8 ree0;
399 u8 ree1;
400 };
401
402 #define MSIX_VECTOR_INVALID 0xFFFF
403 #define MAX_RVU_BLKLF_CNT 256
404
405 struct msix_offset_rsp {
406 struct mbox_msghdr hdr;
407 u16 npa_msixoff;
408 u16 nix_msixoff;
409 u16 sso;
410 u16 ssow;
411 u16 timlfs;
412 u16 cptlfs;
413 u16 sso_msixoff[MAX_RVU_BLKLF_CNT];
414 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT];
415 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT];
416 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT];
417 u16 cpt1_lfs;
418 u16 ree0_lfs;
419 u16 ree1_lfs;
420 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
421 u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
422 u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];
423 };
424
425 struct get_hw_cap_rsp {
426 struct mbox_msghdr hdr;
427 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
428 u8 nix_shaping; /* Is shaping and coloring supported */
429 };
430
431 /* CGX mbox message formats */
432
433 struct cgx_stats_rsp {
434 struct mbox_msghdr hdr;
435 #define CGX_RX_STATS_COUNT 9
436 #define CGX_TX_STATS_COUNT 18
437 u64 rx_stats[CGX_RX_STATS_COUNT];
438 u64 tx_stats[CGX_TX_STATS_COUNT];
439 };
440
441 struct cgx_fec_stats_rsp {
442 struct mbox_msghdr hdr;
443 u64 fec_corr_blks;
444 u64 fec_uncorr_blks;
445 };
446 /* Structure for requesting the operation for
447 * setting/getting mac address in the CGX interface
448 */
449 struct cgx_mac_addr_set_or_get {
450 struct mbox_msghdr hdr;
451 u8 mac_addr[ETH_ALEN];
452 };
453
454 /* Structure for requesting the operation to
455 * add DMAC filter entry into CGX interface
456 */
457 struct cgx_mac_addr_add_req {
458 struct mbox_msghdr hdr;
459 u8 mac_addr[ETH_ALEN];
460 };
461
462 /* Structure for response against the operation to
463 * add DMAC filter entry into CGX interface
464 */
465 struct cgx_mac_addr_add_rsp {
466 struct mbox_msghdr hdr;
467 u8 index;
468 };
469
470 /* Structure for requesting the operation to
471 * delete DMAC filter entry from CGX interface
472 */
473 struct cgx_mac_addr_del_req {
474 struct mbox_msghdr hdr;
475 u8 index;
476 };
477
478 /* Structure for response against the operation to
479 * get maximum supported DMAC filter entries
480 */
481 struct cgx_max_dmac_entries_get_rsp {
482 struct mbox_msghdr hdr;
483 u8 max_dmac_filters;
484 };
485
486 struct cgx_link_user_info {
487 uint64_t link_up:1;
488 uint64_t full_duplex:1;
489 uint64_t lmac_type_id:4;
490 uint64_t speed:20; /* speed in Mbps */
491 uint64_t an:1; /* AN supported or not */
492 uint64_t fec:2; /* FEC type if enabled else 0 */
493 #define LMACTYPE_STR_LEN 16
494 char lmac_type[LMACTYPE_STR_LEN];
495 };
496
497 struct cgx_link_info_msg {
498 struct mbox_msghdr hdr;
499 struct cgx_link_user_info link_info;
500 };
501
502 struct cgx_pause_frm_cfg {
503 struct mbox_msghdr hdr;
504 u8 set;
505 /* set = 1 if the request is to config pause frames */
506 /* set = 0 if the request is to fetch pause frames config */
507 u8 rx_pause;
508 u8 tx_pause;
509 };
510
511 enum fec_type {
512 OTX2_FEC_NONE,
513 OTX2_FEC_BASER,
514 OTX2_FEC_RS,
515 OTX2_FEC_STATS_CNT = 2,
516 OTX2_FEC_OFF,
517 };
518
519 struct fec_mode {
520 struct mbox_msghdr hdr;
521 int fec;
522 };
523
524 struct sfp_eeprom_s {
525 #define SFP_EEPROM_SIZE 256
526 u16 sff_id;
527 u8 buf[SFP_EEPROM_SIZE];
528 u64 reserved;
529 };
530
531 struct phy_s {
532 struct {
533 u64 can_change_mod_type:1;
534 u64 mod_type:1;
535 u64 has_fec_stats:1;
536 } misc;
537 struct fec_stats_s {
538 u32 rsfec_corr_cws;
539 u32 rsfec_uncorr_cws;
540 u32 brfec_corr_blks;
541 u32 brfec_uncorr_blks;
542 } fec_stats;
543 };
544
545 struct cgx_lmac_fwdata_s {
546 u16 rw_valid;
547 u64 supported_fec;
548 u64 supported_an;
549 u64 supported_link_modes;
550 /* only applicable if AN is supported */
551 u64 advertised_fec;
552 u64 advertised_link_modes;
553 /* Only applicable if SFP/QSFP slot is present */
554 struct sfp_eeprom_s sfp_eeprom;
555 struct phy_s phy;
556 #define LMAC_FWDATA_RESERVED_MEM 1021
557 u64 reserved[LMAC_FWDATA_RESERVED_MEM];
558 };
559
560 struct cgx_fw_data {
561 struct mbox_msghdr hdr;
562 struct cgx_lmac_fwdata_s fwdata;
563 };
564
565 struct cgx_set_link_mode_args {
566 u32 speed;
567 u8 duplex;
568 u8 an;
569 u8 ports;
570 u64 mode;
571 };
572
573 struct cgx_set_link_mode_req {
574 #define AUTONEG_UNKNOWN 0xff
575 struct mbox_msghdr hdr;
576 struct cgx_set_link_mode_args args;
577 };
578
579 struct cgx_set_link_mode_rsp {
580 struct mbox_msghdr hdr;
581 int status;
582 };
583
584 struct cgx_mac_addr_update_req {
585 struct mbox_msghdr hdr;
586 u8 mac_addr[ETH_ALEN];
587 u8 index;
588 };
589
590 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */
591 #define RVU_LMAC_FEAT_HIGIG2 BIT_ULL(1)
592 /* flow control from physical link higig2 messages */
593 #define RVU_LMAC_FEAT_PTP BIT_ULL(2) /* precison time protocol */
594 #define RVU_LMAC_FEAT_DMACF BIT_ULL(3) /* DMAC FILTER */
595 #define RVU_MAC_VERSION BIT_ULL(4)
596 #define RVU_MAC_CGX BIT_ULL(5)
597 #define RVU_MAC_RPM BIT_ULL(6)
598
599 struct cgx_features_info_msg {
600 struct mbox_msghdr hdr;
601 u64 lmac_features;
602 };
603
604 struct rpm_stats_rsp {
605 struct mbox_msghdr hdr;
606 #define RPM_RX_STATS_COUNT 43
607 #define RPM_TX_STATS_COUNT 34
608 u64 rx_stats[RPM_RX_STATS_COUNT];
609 u64 tx_stats[RPM_TX_STATS_COUNT];
610 };
611
612 struct npc_set_pkind {
613 struct mbox_msghdr hdr;
614 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0)
615 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63)
616 u64 mode;
617 #define PKIND_TX BIT_ULL(0)
618 #define PKIND_RX BIT_ULL(1)
619 u8 dir;
620 u8 pkind; /* valid only in case custom flag */
621 u8 var_len_off; /* Offset of custom header length field.
622 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND
623 */
624 u8 var_len_off_mask; /* Mask for length with in offset */
625 u8 shift_dir; /* shift direction to get length of the header at var_len_off */
626 };
627
628 /* NPA mbox message formats */
629
630 /* NPA mailbox error codes
631 * Range 301 - 400.
632 */
633 enum npa_af_status {
634 NPA_AF_ERR_PARAM = -301,
635 NPA_AF_ERR_AQ_FULL = -302,
636 NPA_AF_ERR_AQ_ENQUEUE = -303,
637 NPA_AF_ERR_AF_LF_INVALID = -304,
638 NPA_AF_ERR_AF_LF_ALLOC = -305,
639 NPA_AF_ERR_LF_RESET = -306,
640 };
641
642 /* For NPA LF context alloc and init */
643 struct npa_lf_alloc_req {
644 struct mbox_msghdr hdr;
645 int node;
646 int aura_sz; /* No of auras */
647 u32 nr_pools; /* No of pools */
648 u64 way_mask;
649 };
650
651 struct npa_lf_alloc_rsp {
652 struct mbox_msghdr hdr;
653 u32 stack_pg_ptrs; /* No of ptrs per stack page */
654 u32 stack_pg_bytes; /* Size of stack page */
655 u16 qints; /* NPA_AF_CONST::QINTS */
656 u8 cache_lines; /*BATCH ALLOC DMA */
657 };
658
659 /* NPA AQ enqueue msg */
660 struct npa_aq_enq_req {
661 struct mbox_msghdr hdr;
662 u32 aura_id;
663 u8 ctype;
664 u8 op;
665 union {
666 /* Valid when op == WRITE/INIT and ctype == AURA.
667 * LF fills the pool_id in aura.pool_addr. AF will translate
668 * the pool_id to pool context pointer.
669 */
670 struct npa_aura_s aura;
671 /* Valid when op == WRITE/INIT and ctype == POOL */
672 struct npa_pool_s pool;
673 };
674 /* Mask data when op == WRITE (1=write, 0=don't write) */
675 union {
676 /* Valid when op == WRITE and ctype == AURA */
677 struct npa_aura_s aura_mask;
678 /* Valid when op == WRITE and ctype == POOL */
679 struct npa_pool_s pool_mask;
680 };
681 };
682
683 struct npa_aq_enq_rsp {
684 struct mbox_msghdr hdr;
685 union {
686 /* Valid when op == READ and ctype == AURA */
687 struct npa_aura_s aura;
688 /* Valid when op == READ and ctype == POOL */
689 struct npa_pool_s pool;
690 };
691 };
692
693 /* Disable all contexts of type 'ctype' */
694 struct hwctx_disable_req {
695 struct mbox_msghdr hdr;
696 u8 ctype;
697 };
698
699 /* NIX mbox message formats */
700
701 /* NIX mailbox error codes
702 * Range 401 - 500.
703 */
704 enum nix_af_status {
705 NIX_AF_ERR_PARAM = -401,
706 NIX_AF_ERR_AQ_FULL = -402,
707 NIX_AF_ERR_AQ_ENQUEUE = -403,
708 NIX_AF_ERR_AF_LF_INVALID = -404,
709 NIX_AF_ERR_AF_LF_ALLOC = -405,
710 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
711 NIX_AF_ERR_TLX_INVALID = -407,
712 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
713 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
714 NIX_AF_ERR_FRS_INVALID = -410,
715 NIX_AF_ERR_RX_LINK_INVALID = -411,
716 NIX_AF_INVAL_TXSCHQ_CFG = -412,
717 NIX_AF_SMQ_FLUSH_FAILED = -413,
718 NIX_AF_ERR_LF_RESET = -414,
719 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
720 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
721 NIX_AF_ERR_MARK_CFG_FAIL = -417,
722 NIX_AF_ERR_LSO_CFG_FAIL = -418,
723 NIX_AF_INVAL_NPA_PF_FUNC = -419,
724 NIX_AF_INVAL_SSO_PF_FUNC = -420,
725 NIX_AF_ERR_TX_VTAG_NOSPC = -421,
726 NIX_AF_ERR_RX_VTAG_INUSE = -422,
727 NIX_AF_ERR_PTP_CONFIG_FAIL = -423,
728 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424,
729 NIX_AF_ERR_INVALID_NIXBLK = -425,
730 NIX_AF_ERR_INVALID_BANDPROF = -426,
731 NIX_AF_ERR_IPOLICER_NOTSUPP = -427,
732 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428,
733 NIX_AF_ERR_CQ_CTX_WRITE_ERR = -429,
734 NIX_AF_ERR_AQ_CTX_RETRY_WRITE = -430,
735 };
736
737 /* For NIX RX vtag action */
738 enum nix_rx_vtag0_type {
739 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */
740 NIX_AF_LFX_RX_VTAG_TYPE1,
741 NIX_AF_LFX_RX_VTAG_TYPE2,
742 NIX_AF_LFX_RX_VTAG_TYPE3,
743 NIX_AF_LFX_RX_VTAG_TYPE4,
744 NIX_AF_LFX_RX_VTAG_TYPE5,
745 NIX_AF_LFX_RX_VTAG_TYPE6,
746 NIX_AF_LFX_RX_VTAG_TYPE7,
747 };
748
749 /* For NIX LF context alloc and init */
750 struct nix_lf_alloc_req {
751 struct mbox_msghdr hdr;
752 int node;
753 u32 rq_cnt; /* No of receive queues */
754 u32 sq_cnt; /* No of send queues */
755 u32 cq_cnt; /* No of completion queues */
756 u8 xqe_sz;
757 u16 rss_sz;
758 u8 rss_grps;
759 u16 npa_func;
760 u16 sso_func;
761 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
762 u64 way_mask;
763 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
764 #define NIX_LF_LBK_BLK_SEL BIT_ULL(1)
765 u64 flags;
766 };
767
768 struct nix_lf_alloc_rsp {
769 struct mbox_msghdr hdr;
770 u16 sqb_size;
771 u16 rx_chan_base;
772 u16 tx_chan_base;
773 u8 rx_chan_cnt; /* total number of RX channels */
774 u8 tx_chan_cnt; /* total number of TX channels */
775 u8 lso_tsov4_idx;
776 u8 lso_tsov6_idx;
777 u8 mac_addr[ETH_ALEN];
778 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
779 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
780 u16 cints; /* NIX_AF_CONST2::CINTS */
781 u16 qints; /* NIX_AF_CONST2::QINTS */
782 u8 cgx_links; /* No. of CGX links present in HW */
783 u8 lbk_links; /* No. of LBK links present in HW */
784 u8 sdp_links; /* No. of SDP links present in HW */
785 u8 tx_link; /* Transmit channel link number */
786 };
787
788 struct nix_lf_free_req {
789 struct mbox_msghdr hdr;
790 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0)
791 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1)
792 u64 flags;
793 };
794
795 /* CN10K NIX AQ enqueue msg */
796 struct nix_cn10k_aq_enq_req {
797 struct mbox_msghdr hdr;
798 u32 qidx;
799 u8 ctype;
800 u8 op;
801 union {
802 struct nix_cn10k_rq_ctx_s rq;
803 struct nix_cn10k_sq_ctx_s sq;
804 struct nix_cq_ctx_s cq;
805 struct nix_rsse_s rss;
806 struct nix_rx_mce_s mce;
807 struct nix_bandprof_s prof;
808 };
809 union {
810 struct nix_cn10k_rq_ctx_s rq_mask;
811 struct nix_cn10k_sq_ctx_s sq_mask;
812 struct nix_cq_ctx_s cq_mask;
813 struct nix_rsse_s rss_mask;
814 struct nix_rx_mce_s mce_mask;
815 struct nix_bandprof_s prof_mask;
816 };
817 };
818
819 struct nix_cn10k_aq_enq_rsp {
820 struct mbox_msghdr hdr;
821 union {
822 struct nix_cn10k_rq_ctx_s rq;
823 struct nix_cn10k_sq_ctx_s sq;
824 struct nix_cq_ctx_s cq;
825 struct nix_rsse_s rss;
826 struct nix_rx_mce_s mce;
827 struct nix_bandprof_s prof;
828 };
829 };
830
831 /* NIX AQ enqueue msg */
832 struct nix_aq_enq_req {
833 struct mbox_msghdr hdr;
834 u32 qidx;
835 u8 ctype;
836 u8 op;
837 union {
838 struct nix_rq_ctx_s rq;
839 struct nix_sq_ctx_s sq;
840 struct nix_cq_ctx_s cq;
841 struct nix_rsse_s rss;
842 struct nix_rx_mce_s mce;
843 u64 prof;
844 };
845 union {
846 struct nix_rq_ctx_s rq_mask;
847 struct nix_sq_ctx_s sq_mask;
848 struct nix_cq_ctx_s cq_mask;
849 struct nix_rsse_s rss_mask;
850 struct nix_rx_mce_s mce_mask;
851 u64 prof_mask;
852 };
853 };
854
855 struct nix_aq_enq_rsp {
856 struct mbox_msghdr hdr;
857 union {
858 struct nix_rq_ctx_s rq;
859 struct nix_sq_ctx_s sq;
860 struct nix_cq_ctx_s cq;
861 struct nix_rsse_s rss;
862 struct nix_rx_mce_s mce;
863 struct nix_bandprof_s prof;
864 };
865 };
866
867 /* Tx scheduler/shaper mailbox messages */
868
869 #define MAX_TXSCHQ_PER_FUNC 128
870
871 struct nix_txsch_alloc_req {
872 struct mbox_msghdr hdr;
873 /* Scheduler queue count request at each level */
874 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */
875 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */
876 };
877
878 struct nix_txsch_alloc_rsp {
879 struct mbox_msghdr hdr;
880 /* Scheduler queue count allocated at each level */
881 u16 schq_contig[NIX_TXSCH_LVL_CNT];
882 u16 schq[NIX_TXSCH_LVL_CNT];
883 /* Scheduler queue list allocated at each level */
884 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
885 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
886 u8 aggr_level; /* Traffic aggregation scheduler level */
887 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */
888 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
889 };
890
891 struct nix_txsch_free_req {
892 struct mbox_msghdr hdr;
893 #define TXSCHQ_FREE_ALL BIT_ULL(0)
894 u16 flags;
895 /* Scheduler queue level to be freed */
896 u16 schq_lvl;
897 /* List of scheduler queues to be freed */
898 u16 schq;
899 };
900
901 struct nix_txschq_config {
902 struct mbox_msghdr hdr;
903 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
904 u8 read;
905 #define TXSCHQ_IDX_SHIFT 16
906 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
907 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
908 u8 num_regs;
909 #define MAX_REGS_PER_MBOX_MSG 20
910 u64 reg[MAX_REGS_PER_MBOX_MSG];
911 u64 regval[MAX_REGS_PER_MBOX_MSG];
912 /* All 0's => overwrite with new value */
913 u64 regval_mask[MAX_REGS_PER_MBOX_MSG];
914 };
915
916 struct nix_vtag_config {
917 struct mbox_msghdr hdr;
918 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
919 u8 vtag_size;
920 /* cfg_type is '0' for tx vlan cfg
921 * cfg_type is '1' for rx vlan cfg
922 */
923 u8 cfg_type;
924 union {
925 /* valid when cfg_type is '0' */
926 struct {
927 u64 vtag0;
928 u64 vtag1;
929
930 /* cfg_vtag0 & cfg_vtag1 fields are valid
931 * when free_vtag0 & free_vtag1 are '0's.
932 */
933 /* cfg_vtag0 = 1 to configure vtag0 */
934 u8 cfg_vtag0 :1;
935 /* cfg_vtag1 = 1 to configure vtag1 */
936 u8 cfg_vtag1 :1;
937
938 /* vtag0_idx & vtag1_idx are only valid when
939 * both cfg_vtag0 & cfg_vtag1 are '0's,
940 * these fields are used along with free_vtag0
941 * & free_vtag1 to free the nix lf's tx_vlan
942 * configuration.
943 *
944 * Denotes the indices of tx_vtag def registers
945 * that needs to be cleared and freed.
946 */
947 int vtag0_idx;
948 int vtag1_idx;
949
950 /* free_vtag0 & free_vtag1 fields are valid
951 * when cfg_vtag0 & cfg_vtag1 are '0's.
952 */
953 /* free_vtag0 = 1 clears vtag0 configuration
954 * vtag0_idx denotes the index to be cleared.
955 */
956 u8 free_vtag0 :1;
957 /* free_vtag1 = 1 clears vtag1 configuration
958 * vtag1_idx denotes the index to be cleared.
959 */
960 u8 free_vtag1 :1;
961 } tx;
962
963 /* valid when cfg_type is '1' */
964 struct {
965 /* rx vtag type index, valid values are in 0..7 range */
966 u8 vtag_type;
967 /* rx vtag strip */
968 u8 strip_vtag :1;
969 /* rx vtag capture */
970 u8 capture_vtag :1;
971 } rx;
972 };
973 };
974
975 struct nix_vtag_config_rsp {
976 struct mbox_msghdr hdr;
977 int vtag0_idx;
978 int vtag1_idx;
979 /* Indices of tx_vtag def registers used to configure
980 * tx vtag0 & vtag1 headers, these indices are valid
981 * when nix_vtag_config mbox requested for vtag0 and/
982 * or vtag1 configuration.
983 */
984 };
985
986 struct nix_rss_flowkey_cfg {
987 struct mbox_msghdr hdr;
988 int mcam_index; /* MCAM entry index to modify */
989 #define NIX_FLOW_KEY_TYPE_PORT BIT(0)
990 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1)
991 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2)
992 #define NIX_FLOW_KEY_TYPE_TCP BIT(3)
993 #define NIX_FLOW_KEY_TYPE_UDP BIT(4)
994 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5)
995 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6)
996 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7)
997 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8)
998 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9)
999 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10)
1000 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11)
1001 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
1002 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
1003 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14)
1004 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15)
1005 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16)
1006 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
1007 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20)
1008 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21)
1009 #define NIX_FLOW_KEY_TYPE_AH BIT(22)
1010 #define NIX_FLOW_KEY_TYPE_ESP BIT(23)
1011 u32 flowkey_cfg; /* Flowkey types selected */
1012 u8 group; /* RSS context or group */
1013 };
1014
1015 struct nix_rss_flowkey_cfg_rsp {
1016 struct mbox_msghdr hdr;
1017 u8 alg_idx; /* Selected algo index */
1018 };
1019
1020 struct nix_set_mac_addr {
1021 struct mbox_msghdr hdr;
1022 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */
1023 };
1024
1025 struct nix_get_mac_addr_rsp {
1026 struct mbox_msghdr hdr;
1027 u8 mac_addr[ETH_ALEN];
1028 };
1029
1030 struct nix_mark_format_cfg {
1031 struct mbox_msghdr hdr;
1032 u8 offset;
1033 u8 y_mask;
1034 u8 y_val;
1035 u8 r_mask;
1036 u8 r_val;
1037 };
1038
1039 struct nix_mark_format_cfg_rsp {
1040 struct mbox_msghdr hdr;
1041 u8 mark_format_idx;
1042 };
1043
1044 struct nix_rx_mode {
1045 struct mbox_msghdr hdr;
1046 #define NIX_RX_MODE_UCAST BIT(0)
1047 #define NIX_RX_MODE_PROMISC BIT(1)
1048 #define NIX_RX_MODE_ALLMULTI BIT(2)
1049 #define NIX_RX_MODE_USE_MCE BIT(3)
1050 u16 mode;
1051 };
1052
1053 struct nix_rx_cfg {
1054 struct mbox_msghdr hdr;
1055 #define NIX_RX_OL3_VERIFY BIT(0)
1056 #define NIX_RX_OL4_VERIFY BIT(1)
1057 u8 len_verify; /* Outer L3/L4 len check */
1058 #define NIX_RX_CSUM_OL4_VERIFY BIT(0)
1059 u8 csum_verify; /* Outer L4 checksum verification */
1060 };
1061
1062 struct nix_frs_cfg {
1063 struct mbox_msghdr hdr;
1064 u8 update_smq; /* Update SMQ's min/max lens */
1065 u8 update_minlen; /* Set minlen also */
1066 u8 sdp_link; /* Set SDP RX link */
1067 u16 maxlen;
1068 u16 minlen;
1069 };
1070
1071 struct nix_lso_format_cfg {
1072 struct mbox_msghdr hdr;
1073 u64 field_mask;
1074 #define NIX_LSO_FIELD_MAX 8
1075 u64 fields[NIX_LSO_FIELD_MAX];
1076 };
1077
1078 struct nix_lso_format_cfg_rsp {
1079 struct mbox_msghdr hdr;
1080 u8 lso_format_idx;
1081 };
1082
1083 struct nix_bp_cfg_req {
1084 struct mbox_msghdr hdr;
1085 u16 chan_base; /* Starting channel number */
1086 u8 chan_cnt; /* Number of channels */
1087 u8 bpid_per_chan;
1088 /* bpid_per_chan = 0 assigns single bp id for range of channels */
1089 /* bpid_per_chan = 1 assigns separate bp id for each channel */
1090 };
1091
1092 /* PF can be mapped to either CGX or LBK interface,
1093 * so maximum 64 channels are possible.
1094 */
1095 #define NIX_MAX_BPID_CHAN 64
1096 struct nix_bp_cfg_rsp {
1097 struct mbox_msghdr hdr;
1098 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */
1099 u8 chan_cnt; /* Number of channel for which bpids are assigned */
1100 };
1101
1102 /* Global NIX inline IPSec configuration */
1103 struct nix_inline_ipsec_cfg {
1104 struct mbox_msghdr hdr;
1105 u32 cpt_credit;
1106 struct {
1107 u8 egrp;
1108 u8 opcode;
1109 u16 param1;
1110 u16 param2;
1111 } gen_cfg;
1112 struct {
1113 u16 cpt_pf_func;
1114 u8 cpt_slot;
1115 } inst_qsel;
1116 u8 enable;
1117 };
1118
1119 /* Per NIX LF inline IPSec configuration */
1120 struct nix_inline_ipsec_lf_cfg {
1121 struct mbox_msghdr hdr;
1122 u64 sa_base_addr;
1123 struct {
1124 u32 tag_const;
1125 u16 lenm1_max;
1126 u8 sa_pow2_size;
1127 u8 tt;
1128 } ipsec_cfg0;
1129 struct {
1130 u32 sa_idx_max;
1131 u8 sa_idx_w;
1132 } ipsec_cfg1;
1133 u8 enable;
1134 };
1135
1136 struct nix_hw_info {
1137 struct mbox_msghdr hdr;
1138 u16 rsvs16;
1139 u16 max_mtu;
1140 u16 min_mtu;
1141 u32 rpm_dwrr_mtu;
1142 u32 sdp_dwrr_mtu;
1143 u64 rsvd[16]; /* Add reserved fields for future expansion */
1144 };
1145
1146 struct nix_bandprof_alloc_req {
1147 struct mbox_msghdr hdr;
1148 /* Count of profiles needed per layer */
1149 u16 prof_count[BAND_PROF_NUM_LAYERS];
1150 };
1151
1152 struct nix_bandprof_alloc_rsp {
1153 struct mbox_msghdr hdr;
1154 u16 prof_count[BAND_PROF_NUM_LAYERS];
1155
1156 /* There is no need to allocate morethan 1 bandwidth profile
1157 * per RQ of a PF_FUNC's NIXLF. So limit the maximum
1158 * profiles to 64 per PF_FUNC.
1159 */
1160 #define MAX_BANDPROF_PER_PFFUNC 64
1161 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1162 };
1163
1164 struct nix_bandprof_free_req {
1165 struct mbox_msghdr hdr;
1166 u8 free_all;
1167 u16 prof_count[BAND_PROF_NUM_LAYERS];
1168 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1169 };
1170
1171 struct nix_bandprof_get_hwinfo_rsp {
1172 struct mbox_msghdr hdr;
1173 u16 prof_count[BAND_PROF_NUM_LAYERS];
1174 u32 policer_timeunit;
1175 };
1176
1177 /* NPC mbox message structs */
1178
1179 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
1180 #define NPC_MCAM_INVALID_MAP 0xFFFF
1181
1182 /* NPC mailbox error codes
1183 * Range 701 - 800.
1184 */
1185 enum npc_af_status {
1186 NPC_MCAM_INVALID_REQ = -701,
1187 NPC_MCAM_ALLOC_DENIED = -702,
1188 NPC_MCAM_ALLOC_FAILED = -703,
1189 NPC_MCAM_PERM_DENIED = -704,
1190 NPC_FLOW_INTF_INVALID = -707,
1191 NPC_FLOW_CHAN_INVALID = -708,
1192 NPC_FLOW_NO_NIXLF = -709,
1193 NPC_FLOW_NOT_SUPPORTED = -710,
1194 NPC_FLOW_VF_PERM_DENIED = -711,
1195 NPC_FLOW_VF_NOT_INIT = -712,
1196 NPC_FLOW_VF_OVERLAP = -713,
1197 };
1198
1199 struct npc_mcam_alloc_entry_req {
1200 struct mbox_msghdr hdr;
1201 #define NPC_MAX_NONCONTIG_ENTRIES 256
1202 u8 contig; /* Contiguous entries ? */
1203 #define NPC_MCAM_ANY_PRIO 0
1204 #define NPC_MCAM_LOWER_PRIO 1
1205 #define NPC_MCAM_HIGHER_PRIO 2
1206 u8 priority; /* Lower or higher w.r.t ref_entry */
1207 u16 ref_entry;
1208 u16 count; /* Number of entries requested */
1209 };
1210
1211 struct npc_mcam_alloc_entry_rsp {
1212 struct mbox_msghdr hdr;
1213 u16 entry; /* Entry allocated or start index if contiguous.
1214 * Invalid incase of non-contiguous.
1215 */
1216 u16 count; /* Number of entries allocated */
1217 u16 free_count; /* Number of entries available */
1218 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1219 };
1220
1221 struct npc_mcam_free_entry_req {
1222 struct mbox_msghdr hdr;
1223 u16 entry; /* Entry index to be freed */
1224 u8 all; /* If all entries allocated to this PFVF to be freed */
1225 };
1226
1227 struct mcam_entry {
1228 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */
1229 u64 kw[NPC_MAX_KWS_IN_KEY];
1230 u64 kw_mask[NPC_MAX_KWS_IN_KEY];
1231 u64 action;
1232 u64 vtag_action;
1233 };
1234
1235 struct npc_mcam_write_entry_req {
1236 struct mbox_msghdr hdr;
1237 struct mcam_entry entry_data;
1238 u16 entry; /* MCAM entry to write this match key */
1239 u16 cntr; /* Counter for this MCAM entry */
1240 u8 intf; /* Rx or Tx interface */
1241 u8 enable_entry;/* Enable this MCAM entry ? */
1242 u8 set_cntr; /* Set counter for this entry ? */
1243 };
1244
1245 /* Enable/Disable a given entry */
1246 struct npc_mcam_ena_dis_entry_req {
1247 struct mbox_msghdr hdr;
1248 u16 entry;
1249 };
1250
1251 struct npc_mcam_shift_entry_req {
1252 struct mbox_msghdr hdr;
1253 #define NPC_MCAM_MAX_SHIFTS 64
1254 u16 curr_entry[NPC_MCAM_MAX_SHIFTS];
1255 u16 new_entry[NPC_MCAM_MAX_SHIFTS];
1256 u16 shift_count; /* Number of entries to shift */
1257 };
1258
1259 struct npc_mcam_shift_entry_rsp {
1260 struct mbox_msghdr hdr;
1261 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */
1262 };
1263
1264 struct npc_mcam_alloc_counter_req {
1265 struct mbox_msghdr hdr;
1266 u8 contig; /* Contiguous counters ? */
1267 #define NPC_MAX_NONCONTIG_COUNTERS 64
1268 u16 count; /* Number of counters requested */
1269 };
1270
1271 struct npc_mcam_alloc_counter_rsp {
1272 struct mbox_msghdr hdr;
1273 u16 cntr; /* Counter allocated or start index if contiguous.
1274 * Invalid incase of non-contiguous.
1275 */
1276 u16 count; /* Number of counters allocated */
1277 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1278 };
1279
1280 struct npc_mcam_oper_counter_req {
1281 struct mbox_msghdr hdr;
1282 u16 cntr; /* Free a counter or clear/fetch it's stats */
1283 };
1284
1285 struct npc_mcam_oper_counter_rsp {
1286 struct mbox_msghdr hdr;
1287 u64 stat; /* valid only while fetching counter's stats */
1288 };
1289
1290 struct npc_mcam_unmap_counter_req {
1291 struct mbox_msghdr hdr;
1292 u16 cntr;
1293 u16 entry; /* Entry and counter to be unmapped */
1294 u8 all; /* Unmap all entries using this counter ? */
1295 };
1296
1297 struct npc_mcam_alloc_and_write_entry_req {
1298 struct mbox_msghdr hdr;
1299 struct mcam_entry entry_data;
1300 u16 ref_entry;
1301 u8 priority; /* Lower or higher w.r.t ref_entry */
1302 u8 intf; /* Rx or Tx interface */
1303 u8 enable_entry;/* Enable this MCAM entry ? */
1304 u8 alloc_cntr; /* Allocate counter and map ? */
1305 };
1306
1307 struct npc_mcam_alloc_and_write_entry_rsp {
1308 struct mbox_msghdr hdr;
1309 u16 entry;
1310 u16 cntr;
1311 };
1312
1313 struct npc_get_kex_cfg_rsp {
1314 struct mbox_msghdr hdr;
1315 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
1316 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
1317 #define NPC_MAX_INTF 2
1318 #define NPC_MAX_LID 8
1319 #define NPC_MAX_LT 16
1320 #define NPC_MAX_LD 2
1321 #define NPC_MAX_LFL 16
1322 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1323 u64 kex_ld_flags[NPC_MAX_LD];
1324 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1325 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
1326 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1327 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1328 #define MKEX_NAME_LEN 128
1329 u8 mkex_pfl_name[MKEX_NAME_LEN];
1330 };
1331
1332 struct flow_msg {
1333 unsigned char dmac[6];
1334 unsigned char smac[6];
1335 __be16 etype;
1336 __be16 vlan_etype;
1337 __be16 vlan_tci;
1338 union {
1339 __be32 ip4src;
1340 __be32 ip6src[4];
1341 };
1342 union {
1343 __be32 ip4dst;
1344 __be32 ip6dst[4];
1345 };
1346 u8 tos;
1347 u8 ip_ver;
1348 u8 ip_proto;
1349 u8 tc;
1350 __be16 sport;
1351 __be16 dport;
1352 };
1353
1354 struct npc_install_flow_req {
1355 struct mbox_msghdr hdr;
1356 struct flow_msg packet;
1357 struct flow_msg mask;
1358 u64 features;
1359 u16 entry;
1360 u16 channel;
1361 u16 chan_mask;
1362 u8 intf;
1363 u8 set_cntr; /* If counter is available set counter for this entry ? */
1364 u8 default_rule;
1365 u8 append; /* overwrite(0) or append(1) flow to default rule? */
1366 u16 vf;
1367 /* action */
1368 u32 index;
1369 u16 match_id;
1370 u8 flow_key_alg;
1371 u8 op;
1372 /* vtag rx action */
1373 u8 vtag0_type;
1374 u8 vtag0_valid;
1375 u8 vtag1_type;
1376 u8 vtag1_valid;
1377 /* vtag tx action */
1378 u16 vtag0_def;
1379 u8 vtag0_op;
1380 u16 vtag1_def;
1381 u8 vtag1_op;
1382 };
1383
1384 struct npc_install_flow_rsp {
1385 struct mbox_msghdr hdr;
1386 int counter; /* negative if no counter else counter number */
1387 };
1388
1389 struct npc_delete_flow_req {
1390 struct mbox_msghdr hdr;
1391 u16 entry;
1392 u16 start;/*Disable range of entries */
1393 u16 end;
1394 u8 all; /* PF + VFs */
1395 };
1396
1397 struct npc_mcam_read_entry_req {
1398 struct mbox_msghdr hdr;
1399 u16 entry; /* MCAM entry to read */
1400 };
1401
1402 struct npc_mcam_read_entry_rsp {
1403 struct mbox_msghdr hdr;
1404 struct mcam_entry entry_data;
1405 u8 intf;
1406 u8 enable;
1407 };
1408
1409 struct npc_mcam_read_base_rule_rsp {
1410 struct mbox_msghdr hdr;
1411 struct mcam_entry entry;
1412 };
1413
1414 struct npc_mcam_get_stats_req {
1415 struct mbox_msghdr hdr;
1416 u16 entry; /* mcam entry */
1417 };
1418
1419 struct npc_mcam_get_stats_rsp {
1420 struct mbox_msghdr hdr;
1421 u64 stat; /* counter stats */
1422 u8 stat_ena; /* enabled */
1423 };
1424
1425 enum ptp_op {
1426 PTP_OP_ADJFINE = 0,
1427 PTP_OP_GET_CLOCK = 1,
1428 PTP_OP_GET_TSTMP = 2,
1429 PTP_OP_SET_THRESH = 3,
1430 };
1431
1432 struct ptp_req {
1433 struct mbox_msghdr hdr;
1434 u8 op;
1435 s64 scaled_ppm;
1436 u64 thresh;
1437 };
1438
1439 struct ptp_rsp {
1440 struct mbox_msghdr hdr;
1441 u64 clk;
1442 };
1443
1444 struct set_vf_perm {
1445 struct mbox_msghdr hdr;
1446 u16 vf;
1447 #define RESET_VF_PERM BIT_ULL(0)
1448 #define VF_TRUSTED BIT_ULL(1)
1449 u64 flags;
1450 };
1451
1452 struct lmtst_tbl_setup_req {
1453 struct mbox_msghdr hdr;
1454 u64 dis_sched_early_comp :1;
1455 u64 sch_ena :1;
1456 u64 dis_line_pref :1;
1457 u64 ssow_pf_func :13;
1458 u16 base_pcifunc;
1459 u8 use_local_lmt_region;
1460 u64 lmt_iova;
1461 u64 rsvd[4];
1462 };
1463
1464 /* CPT mailbox error codes
1465 * Range 901 - 1000.
1466 */
1467 enum cpt_af_status {
1468 CPT_AF_ERR_PARAM = -901,
1469 CPT_AF_ERR_GRP_INVALID = -902,
1470 CPT_AF_ERR_LF_INVALID = -903,
1471 CPT_AF_ERR_ACCESS_DENIED = -904,
1472 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905,
1473 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906,
1474 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907,
1475 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908
1476 };
1477
1478 /* CPT mbox message formats */
1479 struct cpt_rd_wr_reg_msg {
1480 struct mbox_msghdr hdr;
1481 u64 reg_offset;
1482 u64 *ret_val;
1483 u64 val;
1484 u8 is_write;
1485 int blkaddr;
1486 };
1487
1488 struct cpt_lf_alloc_req_msg {
1489 struct mbox_msghdr hdr;
1490 u16 nix_pf_func;
1491 u16 sso_pf_func;
1492 u16 eng_grpmsk;
1493 int blkaddr;
1494 };
1495
1496 #define CPT_INLINE_INBOUND 0
1497 #define CPT_INLINE_OUTBOUND 1
1498
1499 /* Mailbox message request format for CPT IPsec
1500 * inline inbound and outbound configuration.
1501 */
1502 struct cpt_inline_ipsec_cfg_msg {
1503 struct mbox_msghdr hdr;
1504 u8 enable;
1505 u8 slot;
1506 u8 dir;
1507 u8 sso_pf_func_ovrd;
1508 u16 sso_pf_func; /* inbound path SSO_PF_FUNC */
1509 u16 nix_pf_func; /* outbound path NIX_PF_FUNC */
1510 };
1511
1512 /* Mailbox message request and response format for CPT stats. */
1513 struct cpt_sts_req {
1514 struct mbox_msghdr hdr;
1515 u8 blkaddr;
1516 };
1517
1518 struct cpt_sts_rsp {
1519 struct mbox_msghdr hdr;
1520 u64 inst_req_pc;
1521 u64 inst_lat_pc;
1522 u64 rd_req_pc;
1523 u64 rd_lat_pc;
1524 u64 rd_uc_pc;
1525 u64 active_cycles_pc;
1526 u64 ctx_mis_pc;
1527 u64 ctx_hit_pc;
1528 u64 ctx_aop_pc;
1529 u64 ctx_aop_lat_pc;
1530 u64 ctx_ifetch_pc;
1531 u64 ctx_ifetch_lat_pc;
1532 u64 ctx_ffetch_pc;
1533 u64 ctx_ffetch_lat_pc;
1534 u64 ctx_wback_pc;
1535 u64 ctx_wback_lat_pc;
1536 u64 ctx_psh_pc;
1537 u64 ctx_psh_lat_pc;
1538 u64 ctx_err;
1539 u64 ctx_enc_id;
1540 u64 ctx_flush_timer;
1541 u64 rxc_time;
1542 u64 rxc_time_cfg;
1543 u64 rxc_active_sts;
1544 u64 rxc_zombie_sts;
1545 u64 busy_sts_ae;
1546 u64 free_sts_ae;
1547 u64 busy_sts_se;
1548 u64 free_sts_se;
1549 u64 busy_sts_ie;
1550 u64 free_sts_ie;
1551 u64 exe_err_info;
1552 u64 cptclk_cnt;
1553 u64 diag;
1554 u64 rxc_dfrg;
1555 u64 x2p_link_cfg0;
1556 u64 x2p_link_cfg1;
1557 };
1558
1559 /* Mailbox message request format to configure reassembly timeout. */
1560 struct cpt_rxc_time_cfg_req {
1561 struct mbox_msghdr hdr;
1562 int blkaddr;
1563 u32 step;
1564 u16 zombie_thres;
1565 u16 zombie_limit;
1566 u16 active_thres;
1567 u16 active_limit;
1568 };
1569
1570 /* Mailbox message request format to request for CPT_INST_S lmtst. */
1571 struct cpt_inst_lmtst_req {
1572 struct mbox_msghdr hdr;
1573 u64 inst[8];
1574 u64 rsvd;
1575 };
1576
1577 struct sdp_node_info {
1578 /* Node to which this PF belons to */
1579 u8 node_id;
1580 u8 max_vfs;
1581 u8 num_pf_rings;
1582 u8 pf_srn;
1583 #define SDP_MAX_VFS 128
1584 u8 vf_rings[SDP_MAX_VFS];
1585 };
1586
1587 struct sdp_chan_info_msg {
1588 struct mbox_msghdr hdr;
1589 struct sdp_node_info info;
1590 };
1591
1592 struct sdp_get_chan_info_msg {
1593 struct mbox_msghdr hdr;
1594 u16 chan_base;
1595 u16 num_chan;
1596 };
1597
1598 /* CGX mailbox error codes
1599 * Range 1101 - 1200.
1600 */
1601 enum cgx_af_status {
1602 LMAC_AF_ERR_INVALID_PARAM = -1101,
1603 LMAC_AF_ERR_PF_NOT_MAPPED = -1102,
1604 LMAC_AF_ERR_PERM_DENIED = -1103,
1605 };
1606
1607 #endif /* MBOX_H */
1608