1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2015-2016 Intel Corp. 4 * Copyright 2019 Google LLC 5 * 6 * Modified from coreboot gpio_defs.h 7 */ 8 9 #ifndef _ASM_INTEL_PINCTRL_DEFS_H_ 10 #define _ASM_INTEL_PINCTRL_DEFS_H_ 11 12 /* This file is included by device trees, so avoid BIT() macros */ 13 14 #define PAD_CFG0_TX_STATE_BIT 0 15 #define PAD_CFG0_TX_STATE (1 << PAD_CFG0_TX_STATE_BIT) 16 #define PAD_CFG0_RX_STATE_BIT 1 17 #define PAD_CFG0_RX_STATE (1 << PAD_CFG0_RX_STATE_BIT) 18 #define PAD_CFG0_TX_DISABLE (1 << 8) 19 #define PAD_CFG0_RX_DISABLE (1 << 9) 20 21 #define PAD_CFG0_MODE_SHIFT 10 22 #define PAD_CFG0_MODE_MASK (7 << PAD_CFG0_MODE_SHIFT) 23 #define PAD_CFG0_MODE_GPIO (0 << PAD_CFG0_MODE_SHIFT) 24 #define PAD_CFG0_MODE_NF1 (1 << PAD_CFG0_MODE_SHIFT) 25 #define PAD_CFG0_MODE_NF2 (2 << PAD_CFG0_MODE_SHIFT) 26 #define PAD_CFG0_MODE_NF3 (3 << PAD_CFG0_MODE_SHIFT) 27 #define PAD_CFG0_MODE_NF4 (4 << PAD_CFG0_MODE_SHIFT) 28 #define PAD_CFG0_MODE_NF5 (5 << PAD_CFG0_MODE_SHIFT) 29 #define PAD_CFG0_MODE_NF6 (6 << PAD_CFG0_MODE_SHIFT) 30 31 #define PAD_CFG0_ROUTE_MASK (0xf << 17) 32 #define PAD_CFG0_ROUTE_NMI (1 << 17) 33 #define PAD_CFG0_ROUTE_SMI (1 << 18) 34 #define PAD_CFG0_ROUTE_SCI (1 << 19) 35 #define PAD_CFG0_ROUTE_IOAPIC (1 << 20) 36 #define PAD_CFG0_RXTENCFG_MASK (3 << 21) 37 #define PAD_CFG0_RXINV_MASK (1 << 23) 38 #define PAD_CFG0_RX_POL_INVERT (1 << 23) 39 #define PAD_CFG0_RX_POL_NONE (0 << 23) 40 #define PAD_CFG0_PREGFRXSEL (1 << 24) 41 #define PAD_CFG0_TRIG_MASK (3 << 25) 42 #define PAD_CFG0_TRIG_LEVEL (0 << 25) 43 #define PAD_CFG0_TRIG_EDGE_SINGLE (1 << 25) /* controlled by RX_INVERT*/ 44 #define PAD_CFG0_TRIG_OFF (2 << 25) 45 #define PAD_CFG0_TRIG_EDGE_BOTH (3 << 25) 46 #define PAD_CFG0_RXRAW1_MASK (1 << 28) 47 #define PAD_CFG0_RXPADSTSEL_MASK (1 << 29) 48 #define PAD_CFG0_RESET_MASK (3 << 30) 49 #define PAD_CFG0_LOGICAL_RESET_PWROK (0U << 30) 50 #define PAD_CFG0_LOGICAL_RESET_DEEP (1U << 30) 51 #define PAD_CFG0_LOGICAL_RESET_PLTRST (2U << 30) 52 #define PAD_CFG0_LOGICAL_RESET_RSMRST (3U << 30) 53 54 /* 55 * Use the fourth bit in IntSel field to indicate gpio ownership. This field is 56 * RO and hence not used during gpio configuration. 57 */ 58 #define PAD_CFG1_GPIO_DRIVER (0x1 << 4) 59 #define PAD_CFG1_IRQ_MASK (0xff << 0) 60 #define PAD_CFG1_IOSTERM_MASK (0x3 << 8) 61 #define PAD_CFG1_IOSTERM_SAME (0x0 << 8) 62 #define PAD_CFG1_IOSTERM_DISPUPD (0x1 << 8) 63 #define PAD_CFG1_IOSTERM_ENPD (0x2 << 8) 64 #define PAD_CFG1_IOSTERM_ENPU (0x3 << 8) 65 #define PAD_CFG1_PULL_MASK (0xf << 10) 66 #define PAD_CFG1_PULL_NONE (0x0 << 10) 67 #define PAD_CFG1_PULL_DN_5K (0x2 << 10) 68 #define PAD_CFG1_PULL_DN_20K (0x4 << 10) 69 #define PAD_CFG1_PULL_UP_1K (0x9 << 10) 70 #define PAD_CFG1_PULL_UP_5K (0xa << 10) 71 #define PAD_CFG1_PULL_UP_2K (0xb << 10) 72 #define PAD_CFG1_PULL_UP_20K (0xc << 10) 73 #define PAD_CFG1_PULL_UP_667 (0xd << 10) 74 #define PAD_CFG1_PULL_NATIVE (0xf << 10) 75 76 /* Tx enabled driving last value driven, Rx enabled */ 77 #define PAD_CFG1_IOSSTATE_TX_LAST_RXE (0x0 << 14) 78 /* 79 * Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller 80 * internally 81 */ 82 #define PAD_CFG1_IOSSTATE_TX0_RX_DCR_X0 (0x1 << 14) 83 /* 84 * Tx enabled driving 0, Rx disabled and Rx driving 1 back to its controller 85 * internally 86 */ 87 #define PAD_CFG1_IOSSTATE_TX0_RX_DCR_X1 (0x2 << 14) 88 /* 89 * Tx enabled driving 1, Rx disabled and Rx driving 0 back to its controller 90 * internally 91 */ 92 #define PAD_CFG1_IOSSTATE_TX1_RX_DCR_X0 (0x3 << 14) 93 /* 94 * Tx enabled driving 1, Rx disabled and Rx driving 1 back to its controller 95 * internally 96 */ 97 #define PAD_CFG1_IOSSTATE_TX1_RX_DCR_X1 (0x4 << 14) 98 /* Tx enabled driving 0, Rx enabled */ 99 #define PAD_CFG1_IOSSTATE_TX0_RXE (0x5 << 14) 100 /* Tx enabled driving 1, Rx enabled */ 101 #define PAD_CFG1_IOSSTATE_TX1_RXE (0x6 << 14) 102 /* Hi-Z, Rx driving 0 back to its controller internally */ 103 #define PAD_CFG1_IOSSTATE_HIZCRX0 (0x7 << 14) 104 /* Hi-Z, Rx driving 1 back to its controller internally */ 105 #define PAD_CFG1_IOSSTATE_HIZCRX1 (0x8 << 14) 106 /* Tx disabled, Rx enabled */ 107 #define PAD_CFG1_IOSSTATE_TXD_RXE (0x9 << 14) 108 #define PAD_CFG1_IOSSTATE_IGNORE (0xf << 14) /* Ignore Iostandby */ 109 /* mask to extract Iostandby bits */ 110 #define PAD_CFG1_IOSSTATE_MASK (0xf << 14) 111 #define PAD_CFG1_IOSSTATE_SHIFT 14 /* set Iostandby bits [17:14] */ 112 113 #define PAD_CFG2_DEBEN 1 114 /* Debounce Duration = (2 ^ PAD_CFG2_DEBOUNCE_x_RTC) * RTC clock duration */ 115 #define PAD_CFG2_DEBOUNCE_8_RTC (0x3 << 1) 116 #define PAD_CFG2_DEBOUNCE_16_RTC (0x4 << 1) 117 #define PAD_CFG2_DEBOUNCE_32_RTC (0x5 << 1) 118 #define PAD_CFG2_DEBOUNCE_64_RTC (0x6 << 1) 119 #define PAD_CFG2_DEBOUNCE_128_RTC (0x7 << 1) 120 #define PAD_CFG2_DEBOUNCE_256_RTC (0x8 << 1) 121 #define PAD_CFG2_DEBOUNCE_512_RTC (0x9 << 1) 122 #define PAD_CFG2_DEBOUNCE_1K_RTC (0xa << 1) 123 #define PAD_CFG2_DEBOUNCE_2K_RTC (0xb << 1) 124 #define PAD_CFG2_DEBOUNCE_4K_RTC (0xc << 1) 125 #define PAD_CFG2_DEBOUNCE_8K_RTC (0xd << 1) 126 #define PAD_CFG2_DEBOUNCE_16K_RTC (0xe << 1) 127 #define PAD_CFG2_DEBOUNCE_32K_RTC (0xf << 1) 128 #define PAD_CFG2_DEBOUNCE_MASK 0x1f 129 130 /* voltage tolerance 0=3.3V default 1=1.8V tolerant */ 131 #if IS_ENABLED(INTEL_PINCTRL_IOSTANDBY) 132 #define PAD_CFG1_TOL_MASK (0x1 << 25) 133 #define PAD_CFG1_TOL_1V8 (0x1 << 25) 134 #endif 135 136 #define PAD_FUNC(value) PAD_CFG0_MODE_##value 137 #define PAD_RESET(value) PAD_CFG0_LOGICAL_RESET_##value 138 #define PAD_PULL(value) PAD_CFG1_PULL_##value 139 140 #define PAD_IOSSTATE(value) PAD_CFG1_IOSSTATE_##value 141 #define PAD_IOSTERM(value) PAD_CFG1_IOSTERM_##value 142 143 #define PAD_IRQ_CFG(route, trig, inv) \ 144 (PAD_CFG0_ROUTE_##route | \ 145 PAD_CFG0_TRIG_##trig | \ 146 PAD_CFG0_RX_POL_##inv) 147 148 #if IS_ENABLED(INTEL_PINCTRL_DUAL_ROUTE_SUPPORT) 149 #define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv) \ 150 (PAD_CFG0_ROUTE_##route1 | \ 151 PAD_CFG0_ROUTE_##route2 | \ 152 PAD_CFG0_TRIG_##trig | \ 153 PAD_CFG0_RX_POL_##inv) 154 #endif /* CONFIG_INTEL_PINCTRL_DUAL_ROUTE_SUPPORT */ 155 156 #define _PAD_CFG_STRUCT(__pad, __config0, __config1) \ 157 __pad(__config0) (__config1) 158 159 /* Native function configuration */ 160 #define PAD_CFG_NF(pad, pull, rst, func) \ 161 _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ 162 PAD_IOSSTATE(TX_LAST_RXE)) 163 164 #if IS_ENABLED(CONFIG_INTEL_GPIO_PADCFG_PADTOL) 165 /* 166 * Native 1.8V tolerant pad, only applies to some pads like I2C/I2S. Not 167 * applicable to all SOCs. Refer EDS. 168 */ 169 #define PAD_CFG_NF_1V8(pad, pull, rst, func) \ 170 _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) |\ 171 PAD_IOSSTATE(TX_LAST_RXE) | PAD_CFG1_TOL_1V8) 172 #endif 173 174 /* Native function configuration for standby state */ 175 #define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \ 176 _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ 177 PAD_IOSSTATE(iosstate)) 178 179 /* 180 * Native function configuration for standby state, also configuring iostandby 181 * as masked 182 */ 183 #define PAD_CFG_NF_IOSTANDBY_IGNORE(pad, pull, rst, func) \ 184 _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ 185 PAD_IOSSTATE(IGNORE)) 186 187 /* 188 * Native function configuration for standby state, also configuring iosstate 189 * and iosterm 190 */ 191 #define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \ 192 _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ 193 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) 194 195 /* General purpose output, no pullup/down */ 196 #define PAD_CFG_GPO(pad, val, rst) \ 197 _PAD_CFG_STRUCT(pad, \ 198 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ 199 PAD_PULL(NONE) | PAD_IOSSTATE(TX_LAST_RXE)) 200 201 /* General purpose output, with termination specified */ 202 #define PAD_CFG_TERM_GPO(pad, val, pull, rst) \ 203 _PAD_CFG_STRUCT(pad, \ 204 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ 205 PAD_PULL(pull) | PAD_IOSSTATE(TX_LAST_RXE)) 206 207 /* General purpose output, no pullup/down */ 208 #define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \ 209 _PAD_CFG_STRUCT(pad, \ 210 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ 211 PAD_PULL(pull) | PAD_IOSSTATE(TX_LAST_RXE) | \ 212 PAD_CFG1_GPIO_DRIVER) 213 214 /* General purpose output */ 215 #define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \ 216 _PAD_CFG_STRUCT(pad, \ 217 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ 218 PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm)) 219 220 /* General purpose input */ 221 #define PAD_CFG_GPI(pad, pull, rst) \ 222 _PAD_CFG_STRUCT(pad, \ 223 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ 224 PAD_PULL(pull) | PAD_IOSSTATE(TXD_RXE)) 225 226 /* General purpose input. The following macro sets the 227 * Host Software Pad Ownership to GPIO Driver mode. 228 */ 229 #define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ 230 _PAD_CFG_STRUCT(pad, \ 231 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ 232 PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TXD_RXE)) 233 234 #define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \ 235 _PAD_CFG_STRUCT(pad, \ 236 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 237 PAD_CFG0_RX_DISABLE, \ 238 PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | \ 239 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) 240 241 #define PAD_CFG_GPIO_HI_Z(pad, pull, rst, iosstate, iosterm) \ 242 _PAD_CFG_STRUCT(pad, \ 243 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 244 PAD_CFG0_RX_DISABLE, PAD_PULL(pull) | \ 245 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) 246 247 /* GPIO Interrupt */ 248 #define PAD_CFG_GPI_INT(pad, pull, rst, trig) \ 249 _PAD_CFG_STRUCT(pad, \ 250 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 251 PAD_CFG0_TRIG_##trig | PAD_CFG0_RX_POL_NONE, \ 252 PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TXD_RXE)) 253 254 /* 255 * No Connect configuration for unused pad. 256 * Both TX and RX are disabled. RX disabling is done to avoid unnecessary 257 * setting of GPI_STS. 258 */ 259 #define PAD_NC(pad, pull) \ 260 _PAD_CFG_STRUCT(pad, \ 261 PAD_FUNC(GPIO) | PAD_RESET(DEEP) | \ 262 PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE, \ 263 PAD_PULL(pull) | PAD_IOSSTATE(TXD_RXE)) 264 265 /* General purpose input, routed to APIC */ 266 #define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \ 267 _PAD_CFG_STRUCT(pad, \ 268 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 269 PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ 270 PAD_IOSSTATE(TXD_RXE)) 271 272 /* General purpose input, routed to APIC - with IOStandby Config*/ 273 #define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ 274 _PAD_CFG_STRUCT(pad, \ 275 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 276 PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ 277 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) 278 279 /* 280 * The following APIC macros assume the APIC will handle the filtering 281 * on its own end. One just needs to pass an active high message into the 282 * ITSS. 283 */ 284 #define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \ 285 PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, INVERT) 286 287 #define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \ 288 PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE) 289 290 #define PAD_CFG_GPI_APIC_EDGE_LOW(pad, pull, rst) \ 291 PAD_CFG_GPI_APIC(pad, pull, rst, EDGE_SINGLE, INVERT) 292 293 /* General purpose input, routed to SMI */ 294 #define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \ 295 _PAD_CFG_STRUCT(pad, \ 296 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 297 PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ 298 PAD_IOSSTATE(TXD_RXE)) 299 300 /* General purpose input, routed to SMI */ 301 #define PAD_CFG_GPI_SMI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ 302 _PAD_CFG_STRUCT(pad, \ 303 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 304 PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ 305 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) 306 307 #define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \ 308 PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT) 309 310 #define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \ 311 PAD_CFG_GPI_SMI(pad, pull, rst, trig, NONE) 312 313 /* General purpose input, routed to SCI */ 314 #define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \ 315 _PAD_CFG_STRUCT(pad, \ 316 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 317 PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ 318 PAD_IOSSTATE(TXD_RXE)) 319 320 /* General purpose input, routed to SCI */ 321 #define PAD_CFG_GPI_SCI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ 322 _PAD_CFG_STRUCT(pad, \ 323 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 324 PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ 325 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) 326 327 #define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \ 328 PAD_CFG_GPI_SCI(pad, pull, rst, trig, INVERT) 329 330 #define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \ 331 PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE) 332 333 #define PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, inv, dur) \ 334 _PAD_CFG_STRUCT_3(pad, \ 335 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 336 PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ 337 PAD_IOSSTATE(TXD_RXE), PAD_CFG2_DEBEN | PAD_CFG2_##dur) 338 339 #define PAD_CFG_GPI_SCI_LOW_DEBEN(pad, pull, rst, trig, dur) \ 340 PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, INVERT, dur) 341 342 #define PAD_CFG_GPI_SCI_HIGH_DEBEN(pad, pull, rst, trig, dur) \ 343 PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, NONE, dur) 344 345 /* General purpose input, routed to NMI */ 346 #define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \ 347 _PAD_CFG_STRUCT(pad, \ 348 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 349 PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \ 350 PAD_IOSSTATE(TXD_RXE)) 351 352 #if IS_ENABLED(INTEL_PINCTRL_DUAL_ROUTE_SUPPORT) 353 /* GPI, GPIO Driver, SCI interrupt */ 354 #define PAD_CFG_GPI_GPIO_DRIVER_SCI(pad, pull, rst, trig, inv) \ 355 _PAD_CFG_STRUCT(pad, \ 356 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 357 PAD_IRQ_CFG(SCI, trig, inv), \ 358 PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TXD_RXE)) 359 360 #define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \ 361 _PAD_CFG_STRUCT(pad, \ 362 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 363 PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \ 364 PAD_PULL(pull) | PAD_IOSSTATE(TXD_RXE)) 365 366 #define PAD_CFG_GPI_IRQ_WAKE(pad, pull, rst, trig, inv) \ 367 PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, IOAPIC, SCI) 368 369 #endif /* CONFIG_INTEL_PINCTRL_DUAL_ROUTE_SUPPORT */ 370 371 #endif /* _ASM_INTEL_PINCTRL_DEFS_H_ */ 372