1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * pci.h
4 *
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 *
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
13 *
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
16 *
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
22 */
23 #ifndef LINUX_PCI_H
24 #define LINUX_PCI_H
25
26
27 #include <linux/mod_devicetable.h>
28
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
39 #include <linux/io.h>
40 #include <linux/resource_ext.h>
41 #include <uapi/linux/pci.h>
42
43 #include <linux/pci_ids.h>
44
45 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
46 PCI_STATUS_SIG_SYSTEM_ERROR | \
47 PCI_STATUS_REC_MASTER_ABORT | \
48 PCI_STATUS_REC_TARGET_ABORT | \
49 PCI_STATUS_SIG_TARGET_ABORT | \
50 PCI_STATUS_PARITY)
51
52 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */
53 #define PCI_NUM_RESET_METHODS 7
54
55 #define PCI_RESET_PROBE true
56 #define PCI_RESET_DO_RESET false
57
58 /*
59 * The PCI interface treats multi-function devices as independent
60 * devices. The slot/function address of each device is encoded
61 * in a single byte as follows:
62 *
63 * 7:3 = slot
64 * 2:0 = function
65 *
66 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
67 * In the interest of not exposing interfaces to user-space unnecessarily,
68 * the following kernel-only defines are being added here.
69 */
70 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
71 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
72 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
73
74 /* pci_slot represents a physical slot */
75 struct pci_slot {
76 struct pci_bus *bus; /* Bus this slot is on */
77 struct list_head list; /* Node in list of slots */
78 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
79 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
80 struct kobject kobj;
81 };
82
pci_slot_name(const struct pci_slot * slot)83 static inline const char *pci_slot_name(const struct pci_slot *slot)
84 {
85 return kobject_name(&slot->kobj);
86 }
87
88 /* File state for mmap()s on /proc/bus/pci/X/Y */
89 enum pci_mmap_state {
90 pci_mmap_io,
91 pci_mmap_mem
92 };
93
94 /* For PCI devices, the region numbers are assigned this way: */
95 enum {
96 /* #0-5: standard PCI resources */
97 PCI_STD_RESOURCES,
98 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
99
100 /* #6: expansion ROM resource */
101 PCI_ROM_RESOURCE,
102
103 /* Device-specific resources */
104 #ifdef CONFIG_PCI_IOV
105 PCI_IOV_RESOURCES,
106 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
107 #endif
108
109 /* PCI-to-PCI (P2P) bridge windows */
110 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
111 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
112 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
113
114 /* CardBus bridge windows */
115 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
116 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
117 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
118 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
119
120 /* Total number of bridge resources for P2P and CardBus */
121 #define PCI_BRIDGE_RESOURCE_NUM 4
122
123 /* Resources assigned to buses behind the bridge */
124 PCI_BRIDGE_RESOURCES,
125 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
126 PCI_BRIDGE_RESOURCE_NUM - 1,
127
128 /* Total resources associated with a PCI device */
129 PCI_NUM_RESOURCES,
130
131 /* Preserve this for compatibility */
132 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
133 };
134
135 /**
136 * enum pci_interrupt_pin - PCI INTx interrupt values
137 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
138 * @PCI_INTERRUPT_INTA: PCI INTA pin
139 * @PCI_INTERRUPT_INTB: PCI INTB pin
140 * @PCI_INTERRUPT_INTC: PCI INTC pin
141 * @PCI_INTERRUPT_INTD: PCI INTD pin
142 *
143 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
144 * PCI_INTERRUPT_PIN register.
145 */
146 enum pci_interrupt_pin {
147 PCI_INTERRUPT_UNKNOWN,
148 PCI_INTERRUPT_INTA,
149 PCI_INTERRUPT_INTB,
150 PCI_INTERRUPT_INTC,
151 PCI_INTERRUPT_INTD,
152 };
153
154 /* The number of legacy PCI INTx interrupts */
155 #define PCI_NUM_INTX 4
156
157 /*
158 * pci_power_t values must match the bits in the Capabilities PME_Support
159 * and Control/Status PowerState fields in the Power Management capability.
160 */
161 typedef int __bitwise pci_power_t;
162
163 #define PCI_D0 ((pci_power_t __force) 0)
164 #define PCI_D1 ((pci_power_t __force) 1)
165 #define PCI_D2 ((pci_power_t __force) 2)
166 #define PCI_D3hot ((pci_power_t __force) 3)
167 #define PCI_D3cold ((pci_power_t __force) 4)
168 #define PCI_UNKNOWN ((pci_power_t __force) 5)
169 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
170
171 /* Remember to update this when the list above changes! */
172 extern const char *pci_power_names[];
173
pci_power_name(pci_power_t state)174 static inline const char *pci_power_name(pci_power_t state)
175 {
176 return pci_power_names[1 + (__force int) state];
177 }
178
179 /**
180 * typedef pci_channel_state_t
181 *
182 * The pci_channel state describes connectivity between the CPU and
183 * the PCI device. If some PCI bus between here and the PCI device
184 * has crashed or locked up, this info is reflected here.
185 */
186 typedef unsigned int __bitwise pci_channel_state_t;
187
188 enum {
189 /* I/O channel is in normal state */
190 pci_channel_io_normal = (__force pci_channel_state_t) 1,
191
192 /* I/O to channel is blocked */
193 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
194
195 /* PCI card is dead */
196 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
197 };
198
199 typedef unsigned int __bitwise pcie_reset_state_t;
200
201 enum pcie_reset_state {
202 /* Reset is NOT asserted (Use to deassert reset) */
203 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
204
205 /* Use #PERST to reset PCIe device */
206 pcie_warm_reset = (__force pcie_reset_state_t) 2,
207
208 /* Use PCIe Hot Reset to reset device */
209 pcie_hot_reset = (__force pcie_reset_state_t) 3
210 };
211
212 typedef unsigned short __bitwise pci_dev_flags_t;
213 enum pci_dev_flags {
214 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
215 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
216 /* Device configuration is irrevocably lost if disabled into D3 */
217 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
218 /* Provide indication device is assigned by a Virtual Machine Manager */
219 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
220 /* Flag for quirk use to store if quirk-specific ACS is enabled */
221 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
222 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
223 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
224 /* Do not use bus resets for device */
225 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
226 /* Do not use PM reset even if device advertises NoSoftRst- */
227 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
228 /* Get VPD from function 0 VPD */
229 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
230 /* A non-root bridge where translation occurs, stop alias search here */
231 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
232 /* Do not use FLR even if device advertises PCI_AF_CAP */
233 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
234 /* Don't use Relaxed Ordering for TLPs directed at this device */
235 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
236 /* Device does honor MSI masking despite saying otherwise */
237 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
238 };
239
240 enum pci_irq_reroute_variant {
241 INTEL_IRQ_REROUTE_VARIANT = 1,
242 MAX_IRQ_REROUTE_VARIANTS = 3
243 };
244
245 typedef unsigned short __bitwise pci_bus_flags_t;
246 enum pci_bus_flags {
247 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
248 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
249 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
250 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
251 };
252
253 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
254 enum pcie_link_width {
255 PCIE_LNK_WIDTH_RESRV = 0x00,
256 PCIE_LNK_X1 = 0x01,
257 PCIE_LNK_X2 = 0x02,
258 PCIE_LNK_X4 = 0x04,
259 PCIE_LNK_X8 = 0x08,
260 PCIE_LNK_X12 = 0x0c,
261 PCIE_LNK_X16 = 0x10,
262 PCIE_LNK_X32 = 0x20,
263 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
264 };
265
266 /* See matching string table in pci_speed_string() */
267 enum pci_bus_speed {
268 PCI_SPEED_33MHz = 0x00,
269 PCI_SPEED_66MHz = 0x01,
270 PCI_SPEED_66MHz_PCIX = 0x02,
271 PCI_SPEED_100MHz_PCIX = 0x03,
272 PCI_SPEED_133MHz_PCIX = 0x04,
273 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
274 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
275 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
276 PCI_SPEED_66MHz_PCIX_266 = 0x09,
277 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
278 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
279 AGP_UNKNOWN = 0x0c,
280 AGP_1X = 0x0d,
281 AGP_2X = 0x0e,
282 AGP_4X = 0x0f,
283 AGP_8X = 0x10,
284 PCI_SPEED_66MHz_PCIX_533 = 0x11,
285 PCI_SPEED_100MHz_PCIX_533 = 0x12,
286 PCI_SPEED_133MHz_PCIX_533 = 0x13,
287 PCIE_SPEED_2_5GT = 0x14,
288 PCIE_SPEED_5_0GT = 0x15,
289 PCIE_SPEED_8_0GT = 0x16,
290 PCIE_SPEED_16_0GT = 0x17,
291 PCIE_SPEED_32_0GT = 0x18,
292 PCIE_SPEED_64_0GT = 0x19,
293 PCI_SPEED_UNKNOWN = 0xff,
294 };
295
296 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
297 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
298
299 struct pci_vpd {
300 struct mutex lock;
301 unsigned int len;
302 u8 cap;
303 };
304
305 struct irq_affinity;
306 struct pcie_link_state;
307 struct pci_sriov;
308 struct pci_p2pdma;
309 struct rcec_ea;
310
311 /* The pci_dev structure describes PCI devices */
312 struct pci_dev {
313 struct list_head bus_list; /* Node in per-bus list */
314 struct pci_bus *bus; /* Bus this device is on */
315 struct pci_bus *subordinate; /* Bus this device bridges to */
316
317 void *sysdata; /* Hook for sys-specific extension */
318 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
319 struct pci_slot *slot; /* Physical slot this device is in */
320
321 unsigned int devfn; /* Encoded device & function index */
322 unsigned short vendor;
323 unsigned short device;
324 unsigned short subsystem_vendor;
325 unsigned short subsystem_device;
326 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
327 u8 revision; /* PCI revision, low byte of class word */
328 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
329 #ifdef CONFIG_PCIEAER
330 u16 aer_cap; /* AER capability offset */
331 struct aer_stats *aer_stats; /* AER stats for this device */
332 #endif
333 #ifdef CONFIG_PCIEPORTBUS
334 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
335 struct pci_dev *rcec; /* Associated RCEC device */
336 #endif
337 u32 devcap; /* PCIe Device Capabilities */
338 u8 pcie_cap; /* PCIe capability offset */
339 u8 msi_cap; /* MSI capability offset */
340 u8 msix_cap; /* MSI-X capability offset */
341 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
342 u8 rom_base_reg; /* Config register controlling ROM */
343 u8 pin; /* Interrupt pin this device uses */
344 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
345 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
346
347 struct pci_driver *driver; /* Driver bound to this device */
348 u64 dma_mask; /* Mask of the bits of bus address this
349 device implements. Normally this is
350 0xffffffff. You only need to change
351 this if your device has broken DMA
352 or supports 64-bit transfers. */
353
354 struct device_dma_parameters dma_parms;
355
356 pci_power_t current_state; /* Current operating state. In ACPI,
357 this is D0-D3, D0 being fully
358 functional, and D3 being off. */
359 unsigned int imm_ready:1; /* Supports Immediate Readiness */
360 u8 pm_cap; /* PM capability offset */
361 unsigned int pme_support:5; /* Bitmask of states from which PME#
362 can be generated */
363 unsigned int pme_poll:1; /* Poll device's PME status bit */
364 unsigned int d1_support:1; /* Low power state D1 is supported */
365 unsigned int d2_support:1; /* Low power state D2 is supported */
366 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
367 unsigned int no_d3cold:1; /* D3cold is forbidden */
368 unsigned int bridge_d3:1; /* Allow D3 for bridge */
369 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
370 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
371 decoding during BAR sizing */
372 unsigned int wakeup_prepared:1;
373 unsigned int runtime_d3cold:1; /* Whether go through runtime
374 D3cold, not set for devices
375 powered on/off by the
376 corresponding bridge */
377 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
378 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
379 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
380 controlled exclusively by
381 user sysfs */
382 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
383 bit manually */
384 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
385 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
386
387 #ifdef CONFIG_PCIEASPM
388 struct pcie_link_state *link_state; /* ASPM link state */
389 unsigned int ltr_path:1; /* Latency Tolerance Reporting
390 supported from root to here */
391 u16 l1ss; /* L1SS Capability pointer */
392 #endif
393 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */
394 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
395
396 pci_channel_state_t error_state; /* Current connectivity state */
397 struct device dev; /* Generic device interface */
398
399 int cfg_size; /* Size of config space */
400
401 /*
402 * Instead of touching interrupt line and base address registers
403 * directly, use the values stored here. They might be different!
404 */
405 unsigned int irq;
406 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
407
408 bool match_driver; /* Skip attaching driver */
409
410 unsigned int transparent:1; /* Subtractive decode bridge */
411 unsigned int io_window:1; /* Bridge has I/O window */
412 unsigned int pref_window:1; /* Bridge has pref mem window */
413 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
414 unsigned int multifunction:1; /* Multi-function device */
415
416 unsigned int is_busmaster:1; /* Is busmaster */
417 unsigned int no_msi:1; /* May not use MSI */
418 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
419 unsigned int block_cfg_access:1; /* Config space access blocked */
420 unsigned int broken_parity_status:1; /* Generates false positive parity */
421 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
422 unsigned int msi_enabled:1;
423 unsigned int msix_enabled:1;
424 unsigned int ari_enabled:1; /* ARI forwarding */
425 unsigned int ats_enabled:1; /* Address Translation Svc */
426 unsigned int pasid_enabled:1; /* Process Address Space ID */
427 unsigned int pri_enabled:1; /* Page Request Interface */
428 unsigned int is_managed:1;
429 unsigned int needs_freset:1; /* Requires fundamental reset */
430 unsigned int state_saved:1;
431 unsigned int is_physfn:1;
432 unsigned int is_virtfn:1;
433 unsigned int is_hotplug_bridge:1;
434 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
435 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
436 /*
437 * Devices marked being untrusted are the ones that can potentially
438 * execute DMA attacks and similar. They are typically connected
439 * through external ports such as Thunderbolt but not limited to
440 * that. When an IOMMU is enabled they should be getting full
441 * mappings to make sure they cannot access arbitrary memory.
442 */
443 unsigned int untrusted:1;
444 /*
445 * Info from the platform, e.g., ACPI or device tree, may mark a
446 * device as "external-facing". An external-facing device is
447 * itself internal but devices downstream from it are external.
448 */
449 unsigned int external_facing:1;
450 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
451 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
452 unsigned int irq_managed:1;
453 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
454 unsigned int is_probed:1; /* Device probing in progress */
455 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
456 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
457 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
458 pci_dev_flags_t dev_flags;
459 atomic_t enable_cnt; /* pci_enable_device has been called */
460
461 u32 saved_config_space[16]; /* Config space saved at suspend time */
462 struct hlist_head saved_cap_space;
463 int rom_attr_enabled; /* Display of ROM attribute enabled? */
464 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
465 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
466
467 #ifdef CONFIG_HOTPLUG_PCI_PCIE
468 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
469 #endif
470 #ifdef CONFIG_PCIE_PTM
471 unsigned int ptm_root:1;
472 unsigned int ptm_enabled:1;
473 u8 ptm_granularity;
474 #endif
475 #ifdef CONFIG_PCI_MSI
476 const struct attribute_group **msi_irq_groups;
477 #endif
478 struct pci_vpd vpd;
479 #ifdef CONFIG_PCIE_DPC
480 u16 dpc_cap;
481 unsigned int dpc_rp_extensions:1;
482 u8 dpc_rp_log_size;
483 #endif
484 #ifdef CONFIG_PCI_ATS
485 union {
486 struct pci_sriov *sriov; /* PF: SR-IOV info */
487 struct pci_dev *physfn; /* VF: related PF */
488 };
489 u16 ats_cap; /* ATS Capability offset */
490 u8 ats_stu; /* ATS Smallest Translation Unit */
491 #endif
492 #ifdef CONFIG_PCI_PRI
493 u16 pri_cap; /* PRI Capability offset */
494 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
495 unsigned int pasid_required:1; /* PRG Response PASID Required */
496 #endif
497 #ifdef CONFIG_PCI_PASID
498 u16 pasid_cap; /* PASID Capability offset */
499 u16 pasid_features;
500 #endif
501 #ifdef CONFIG_PCI_P2PDMA
502 struct pci_p2pdma __rcu *p2pdma;
503 #endif
504 u16 acs_cap; /* ACS Capability offset */
505 phys_addr_t rom; /* Physical address if not from BAR */
506 size_t romlen; /* Length if not from BAR */
507 char *driver_override; /* Driver name to force a match */
508
509 unsigned long priv_flags; /* Private flags for the PCI driver */
510
511 /* These methods index pci_reset_fn_methods[] */
512 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */
513 };
514
pci_physfn(struct pci_dev * dev)515 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
516 {
517 #ifdef CONFIG_PCI_IOV
518 if (dev->is_virtfn)
519 dev = dev->physfn;
520 #endif
521 return dev;
522 }
523
524 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
525
526 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
527 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
528
pci_channel_offline(struct pci_dev * pdev)529 static inline int pci_channel_offline(struct pci_dev *pdev)
530 {
531 return (pdev->error_state != pci_channel_io_normal);
532 }
533
534 /*
535 * Currently in ACPI spec, for each PCI host bridge, PCI Segment
536 * Group number is limited to a 16-bit value, therefore (int)-1 is
537 * not a valid PCI domain number, and can be used as a sentinel
538 * value indicating ->domain_nr is not set by the driver (and
539 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with
540 * pci_bus_find_domain_nr()).
541 */
542 #define PCI_DOMAIN_NR_NOT_SET (-1)
543
544 struct pci_host_bridge {
545 struct device dev;
546 struct pci_bus *bus; /* Root bus */
547 struct pci_ops *ops;
548 struct pci_ops *child_ops;
549 void *sysdata;
550 int busnr;
551 int domain_nr;
552 struct list_head windows; /* resource_entry */
553 struct list_head dma_ranges; /* dma ranges resource list */
554 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
555 int (*map_irq)(const struct pci_dev *, u8, u8);
556 void (*release_fn)(struct pci_host_bridge *);
557 void *release_data;
558 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
559 unsigned int no_ext_tags:1; /* No Extended Tags */
560 unsigned int native_aer:1; /* OS may use PCIe AER */
561 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
562 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
563 unsigned int native_pme:1; /* OS may use PCIe PME */
564 unsigned int native_ltr:1; /* OS may use PCIe LTR */
565 unsigned int native_dpc:1; /* OS may use PCIe DPC */
566 unsigned int preserve_config:1; /* Preserve FW resource setup */
567 unsigned int size_windows:1; /* Enable root bus sizing */
568 unsigned int msi_domain:1; /* Bridge wants MSI domain */
569
570 /* Resource alignment requirements */
571 resource_size_t (*align_resource)(struct pci_dev *dev,
572 const struct resource *res,
573 resource_size_t start,
574 resource_size_t size,
575 resource_size_t align);
576 unsigned long private[] ____cacheline_aligned;
577 };
578
579 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
580
pci_host_bridge_priv(struct pci_host_bridge * bridge)581 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
582 {
583 return (void *)bridge->private;
584 }
585
pci_host_bridge_from_priv(void * priv)586 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
587 {
588 return container_of(priv, struct pci_host_bridge, private);
589 }
590
591 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
592 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
593 size_t priv);
594 void pci_free_host_bridge(struct pci_host_bridge *bridge);
595 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
596
597 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
598 void (*release_fn)(struct pci_host_bridge *),
599 void *release_data);
600
601 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
602
603 /*
604 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
605 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
606 * buses below host bridges or subtractive decode bridges) go in the list.
607 * Use pci_bus_for_each_resource() to iterate through all the resources.
608 */
609
610 /*
611 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
612 * and there's no way to program the bridge with the details of the window.
613 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
614 * decode bit set, because they are explicit and can be programmed with _SRS.
615 */
616 #define PCI_SUBTRACTIVE_DECODE 0x1
617
618 struct pci_bus_resource {
619 struct list_head list;
620 struct resource *res;
621 unsigned int flags;
622 };
623
624 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
625
626 struct pci_bus {
627 struct list_head node; /* Node in list of buses */
628 struct pci_bus *parent; /* Parent bus this bridge is on */
629 struct list_head children; /* List of child buses */
630 struct list_head devices; /* List of devices on this bus */
631 struct pci_dev *self; /* Bridge device as seen by parent */
632 struct list_head slots; /* List of slots on this bus;
633 protected by pci_slot_mutex */
634 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
635 struct list_head resources; /* Address space routed to this bus */
636 struct resource busn_res; /* Bus numbers routed to this bus */
637
638 struct pci_ops *ops; /* Configuration access functions */
639 void *sysdata; /* Hook for sys-specific extension */
640 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
641
642 unsigned char number; /* Bus number */
643 unsigned char primary; /* Number of primary bridge */
644 unsigned char max_bus_speed; /* enum pci_bus_speed */
645 unsigned char cur_bus_speed; /* enum pci_bus_speed */
646 #ifdef CONFIG_PCI_DOMAINS_GENERIC
647 int domain_nr;
648 #endif
649
650 char name[48];
651
652 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
653 pci_bus_flags_t bus_flags; /* Inherited by child buses */
654 struct device *bridge;
655 struct device dev;
656 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
657 struct bin_attribute *legacy_mem; /* Legacy mem */
658 unsigned int is_added:1;
659 };
660
661 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
662
pci_dev_id(struct pci_dev * dev)663 static inline u16 pci_dev_id(struct pci_dev *dev)
664 {
665 return PCI_DEVID(dev->bus->number, dev->devfn);
666 }
667
668 /*
669 * Returns true if the PCI bus is root (behind host-PCI bridge),
670 * false otherwise
671 *
672 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
673 * This is incorrect because "virtual" buses added for SR-IOV (via
674 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
675 */
pci_is_root_bus(struct pci_bus * pbus)676 static inline bool pci_is_root_bus(struct pci_bus *pbus)
677 {
678 return !(pbus->parent);
679 }
680
681 /**
682 * pci_is_bridge - check if the PCI device is a bridge
683 * @dev: PCI device
684 *
685 * Return true if the PCI device is bridge whether it has subordinate
686 * or not.
687 */
pci_is_bridge(struct pci_dev * dev)688 static inline bool pci_is_bridge(struct pci_dev *dev)
689 {
690 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
691 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
692 }
693
694 #define for_each_pci_bridge(dev, bus) \
695 list_for_each_entry(dev, &bus->devices, bus_list) \
696 if (!pci_is_bridge(dev)) {} else
697
pci_upstream_bridge(struct pci_dev * dev)698 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
699 {
700 dev = pci_physfn(dev);
701 if (pci_is_root_bus(dev->bus))
702 return NULL;
703
704 return dev->bus->self;
705 }
706
707 #ifdef CONFIG_PCI_MSI
pci_dev_msi_enabled(struct pci_dev * pci_dev)708 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
709 {
710 return pci_dev->msi_enabled || pci_dev->msix_enabled;
711 }
712 #else
pci_dev_msi_enabled(struct pci_dev * pci_dev)713 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
714 #endif
715
716 /* Error values that may be returned by PCI functions */
717 #define PCIBIOS_SUCCESSFUL 0x00
718 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
719 #define PCIBIOS_BAD_VENDOR_ID 0x83
720 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
721 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
722 #define PCIBIOS_SET_FAILED 0x88
723 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
724
725 /* Translate above to generic errno for passing back through non-PCI code */
pcibios_err_to_errno(int err)726 static inline int pcibios_err_to_errno(int err)
727 {
728 if (err <= PCIBIOS_SUCCESSFUL)
729 return err; /* Assume already errno */
730
731 switch (err) {
732 case PCIBIOS_FUNC_NOT_SUPPORTED:
733 return -ENOENT;
734 case PCIBIOS_BAD_VENDOR_ID:
735 return -ENOTTY;
736 case PCIBIOS_DEVICE_NOT_FOUND:
737 return -ENODEV;
738 case PCIBIOS_BAD_REGISTER_NUMBER:
739 return -EFAULT;
740 case PCIBIOS_SET_FAILED:
741 return -EIO;
742 case PCIBIOS_BUFFER_TOO_SMALL:
743 return -ENOSPC;
744 }
745
746 return -ERANGE;
747 }
748
749 /* Low-level architecture-dependent routines */
750
751 struct pci_ops {
752 int (*add_bus)(struct pci_bus *bus);
753 void (*remove_bus)(struct pci_bus *bus);
754 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
755 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
756 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
757 };
758
759 /*
760 * ACPI needs to be able to access PCI config space before we've done a
761 * PCI bus scan and created pci_bus structures.
762 */
763 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
764 int reg, int len, u32 *val);
765 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
766 int reg, int len, u32 val);
767
768 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
769 typedef u64 pci_bus_addr_t;
770 #else
771 typedef u32 pci_bus_addr_t;
772 #endif
773
774 struct pci_bus_region {
775 pci_bus_addr_t start;
776 pci_bus_addr_t end;
777 };
778
779 struct pci_dynids {
780 spinlock_t lock; /* Protects list, index */
781 struct list_head list; /* For IDs added at runtime */
782 };
783
784
785 /*
786 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
787 * a set of callbacks in struct pci_error_handlers, that device driver
788 * will be notified of PCI bus errors, and will be driven to recovery
789 * when an error occurs.
790 */
791
792 typedef unsigned int __bitwise pci_ers_result_t;
793
794 enum pci_ers_result {
795 /* No result/none/not supported in device driver */
796 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
797
798 /* Device driver can recover without slot reset */
799 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
800
801 /* Device driver wants slot to be reset */
802 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
803
804 /* Device has completely failed, is unrecoverable */
805 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
806
807 /* Device driver is fully recovered and operational */
808 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
809
810 /* No AER capabilities registered for the driver */
811 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
812 };
813
814 /* PCI bus error event callbacks */
815 struct pci_error_handlers {
816 /* PCI bus error detected on this device */
817 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
818 pci_channel_state_t error);
819
820 /* MMIO has been re-enabled, but not DMA */
821 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
822
823 /* PCI slot has been reset */
824 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
825
826 /* PCI function reset prepare or completed */
827 void (*reset_prepare)(struct pci_dev *dev);
828 void (*reset_done)(struct pci_dev *dev);
829
830 /* Device driver may resume normal operations */
831 void (*resume)(struct pci_dev *dev);
832 };
833
834
835 struct module;
836
837 /**
838 * struct pci_driver - PCI driver structure
839 * @node: List of driver structures.
840 * @name: Driver name.
841 * @id_table: Pointer to table of device IDs the driver is
842 * interested in. Most drivers should export this
843 * table using MODULE_DEVICE_TABLE(pci,...).
844 * @probe: This probing function gets called (during execution
845 * of pci_register_driver() for already existing
846 * devices or later if a new device gets inserted) for
847 * all PCI devices which match the ID table and are not
848 * "owned" by the other drivers yet. This function gets
849 * passed a "struct pci_dev \*" for each device whose
850 * entry in the ID table matches the device. The probe
851 * function returns zero when the driver chooses to
852 * take "ownership" of the device or an error code
853 * (negative number) otherwise.
854 * The probe function always gets called from process
855 * context, so it can sleep.
856 * @remove: The remove() function gets called whenever a device
857 * being handled by this driver is removed (either during
858 * deregistration of the driver or when it's manually
859 * pulled out of a hot-pluggable slot).
860 * The remove function always gets called from process
861 * context, so it can sleep.
862 * @suspend: Put device into low power state.
863 * @resume: Wake device from low power state.
864 * (Please see Documentation/power/pci.rst for descriptions
865 * of PCI Power Management and the related functions.)
866 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
867 * Intended to stop any idling DMA operations.
868 * Useful for enabling wake-on-lan (NIC) or changing
869 * the power state of a device before reboot.
870 * e.g. drivers/net/e100.c.
871 * @sriov_configure: Optional driver callback to allow configuration of
872 * number of VFs to enable via sysfs "sriov_numvfs" file.
873 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X
874 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count".
875 * This will change MSI-X Table Size in the VF Message Control
876 * registers.
877 * @sriov_get_vf_total_msix: PF driver callback to get the total number of
878 * MSI-X vectors available for distribution to the VFs.
879 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
880 * @groups: Sysfs attribute groups.
881 * @dev_groups: Attributes attached to the device that will be
882 * created once it is bound to the driver.
883 * @driver: Driver model structure.
884 * @dynids: List of dynamically added device IDs.
885 */
886 struct pci_driver {
887 struct list_head node;
888 const char *name;
889 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
890 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
891 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
892 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
893 int (*resume)(struct pci_dev *dev); /* Device woken up */
894 void (*shutdown)(struct pci_dev *dev);
895 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
896 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */
897 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf);
898 const struct pci_error_handlers *err_handler;
899 const struct attribute_group **groups;
900 const struct attribute_group **dev_groups;
901 struct device_driver driver;
902 struct pci_dynids dynids;
903 };
904
to_pci_driver(struct device_driver * drv)905 static inline struct pci_driver *to_pci_driver(struct device_driver *drv)
906 {
907 return drv ? container_of(drv, struct pci_driver, driver) : NULL;
908 }
909
910 /**
911 * PCI_DEVICE - macro used to describe a specific PCI device
912 * @vend: the 16 bit PCI Vendor ID
913 * @dev: the 16 bit PCI Device ID
914 *
915 * This macro is used to create a struct pci_device_id that matches a
916 * specific device. The subvendor and subdevice fields will be set to
917 * PCI_ANY_ID.
918 */
919 #define PCI_DEVICE(vend,dev) \
920 .vendor = (vend), .device = (dev), \
921 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
922
923 /**
924 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with
925 * override_only flags.
926 * @vend: the 16 bit PCI Vendor ID
927 * @dev: the 16 bit PCI Device ID
928 * @driver_override: the 32 bit PCI Device override_only
929 *
930 * This macro is used to create a struct pci_device_id that matches only a
931 * driver_override device. The subvendor and subdevice fields will be set to
932 * PCI_ANY_ID.
933 */
934 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \
935 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \
936 .subdevice = PCI_ANY_ID, .override_only = (driver_override)
937
938 /**
939 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO
940 * "driver_override" PCI device.
941 * @vend: the 16 bit PCI Vendor ID
942 * @dev: the 16 bit PCI Device ID
943 *
944 * This macro is used to create a struct pci_device_id that matches a
945 * specific device. The subvendor and subdevice fields will be set to
946 * PCI_ANY_ID and the driver_override will be set to
947 * PCI_ID_F_VFIO_DRIVER_OVERRIDE.
948 */
949 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \
950 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE)
951
952 /**
953 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
954 * @vend: the 16 bit PCI Vendor ID
955 * @dev: the 16 bit PCI Device ID
956 * @subvend: the 16 bit PCI Subvendor ID
957 * @subdev: the 16 bit PCI Subdevice ID
958 *
959 * This macro is used to create a struct pci_device_id that matches a
960 * specific device with subsystem information.
961 */
962 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
963 .vendor = (vend), .device = (dev), \
964 .subvendor = (subvend), .subdevice = (subdev)
965
966 /**
967 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
968 * @dev_class: the class, subclass, prog-if triple for this device
969 * @dev_class_mask: the class mask for this device
970 *
971 * This macro is used to create a struct pci_device_id that matches a
972 * specific PCI class. The vendor, device, subvendor, and subdevice
973 * fields will be set to PCI_ANY_ID.
974 */
975 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
976 .class = (dev_class), .class_mask = (dev_class_mask), \
977 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
978 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
979
980 /**
981 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
982 * @vend: the vendor name
983 * @dev: the 16 bit PCI Device ID
984 *
985 * This macro is used to create a struct pci_device_id that matches a
986 * specific PCI device. The subvendor, and subdevice fields will be set
987 * to PCI_ANY_ID. The macro allows the next field to follow as the device
988 * private data.
989 */
990 #define PCI_VDEVICE(vend, dev) \
991 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
992 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
993
994 /**
995 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
996 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
997 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
998 * @data: the driver data to be filled
999 *
1000 * This macro is used to create a struct pci_device_id that matches a
1001 * specific PCI device. The subvendor, and subdevice fields will be set
1002 * to PCI_ANY_ID.
1003 */
1004 #define PCI_DEVICE_DATA(vend, dev, data) \
1005 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
1006 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
1007 .driver_data = (kernel_ulong_t)(data)
1008
1009 enum {
1010 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
1011 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
1012 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
1013 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
1014 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
1015 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
1016 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
1017 };
1018
1019 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1020 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1021 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1022 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1023
1024 /* These external functions are only available when PCI support is enabled */
1025 #ifdef CONFIG_PCI
1026
1027 extern unsigned int pci_flags;
1028
pci_set_flags(int flags)1029 static inline void pci_set_flags(int flags) { pci_flags = flags; }
pci_add_flags(int flags)1030 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
pci_clear_flags(int flags)1031 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
pci_has_flag(int flag)1032 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
1033
1034 void pcie_bus_configure_settings(struct pci_bus *bus);
1035
1036 enum pcie_bus_config_types {
1037 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
1038 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
1039 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
1040 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
1041 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
1042 };
1043
1044 extern enum pcie_bus_config_types pcie_bus_config;
1045
1046 extern struct bus_type pci_bus_type;
1047
1048 /* Do NOT directly access these two variables, unless you are arch-specific PCI
1049 * code, or PCI core code. */
1050 extern struct list_head pci_root_buses; /* List of all known PCI buses */
1051 /* Some device drivers need know if PCI is initiated */
1052 int no_pci_devices(void);
1053
1054 void pcibios_resource_survey_bus(struct pci_bus *bus);
1055 void pcibios_bus_add_device(struct pci_dev *pdev);
1056 void pcibios_add_bus(struct pci_bus *bus);
1057 void pcibios_remove_bus(struct pci_bus *bus);
1058 void pcibios_fixup_bus(struct pci_bus *);
1059 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1060 /* Architecture-specific versions may override this (weak) */
1061 char *pcibios_setup(char *str);
1062
1063 /* Used only when drivers/pci/setup.c is used */
1064 resource_size_t pcibios_align_resource(void *, const struct resource *,
1065 resource_size_t,
1066 resource_size_t);
1067
1068 /* Weak but can be overridden by arch */
1069 void pci_fixup_cardbus(struct pci_bus *);
1070
1071 /* Generic PCI functions used internally */
1072
1073 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1074 struct resource *res);
1075 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1076 struct pci_bus_region *region);
1077 void pcibios_scan_specific_bus(int busn);
1078 struct pci_bus *pci_find_bus(int domain, int busnr);
1079 void pci_bus_add_devices(const struct pci_bus *bus);
1080 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1081 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1082 struct pci_ops *ops, void *sysdata,
1083 struct list_head *resources);
1084 int pci_host_probe(struct pci_host_bridge *bridge);
1085 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1086 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1087 void pci_bus_release_busn_res(struct pci_bus *b);
1088 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1089 struct pci_ops *ops, void *sysdata,
1090 struct list_head *resources);
1091 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1092 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1093 int busnr);
1094 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1095 const char *name,
1096 struct hotplug_slot *hotplug);
1097 void pci_destroy_slot(struct pci_slot *slot);
1098 #ifdef CONFIG_SYSFS
1099 void pci_dev_assign_slot(struct pci_dev *dev);
1100 #else
pci_dev_assign_slot(struct pci_dev * dev)1101 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1102 #endif
1103 int pci_scan_slot(struct pci_bus *bus, int devfn);
1104 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1105 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1106 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1107 void pci_bus_add_device(struct pci_dev *dev);
1108 void pci_read_bridge_bases(struct pci_bus *child);
1109 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1110 struct resource *res);
1111 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1112 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1113 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1114 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1115 void pci_dev_put(struct pci_dev *dev);
1116 void pci_remove_bus(struct pci_bus *b);
1117 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1118 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1119 void pci_stop_root_bus(struct pci_bus *bus);
1120 void pci_remove_root_bus(struct pci_bus *bus);
1121 void pci_setup_cardbus(struct pci_bus *bus);
1122 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1123 void pci_sort_breadthfirst(void);
1124 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1125 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1126
1127 /* Generic PCI functions exported to card drivers */
1128
1129 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1130 u8 pci_find_capability(struct pci_dev *dev, int cap);
1131 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1132 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1133 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
1134 u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1135 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
1136 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1137 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
1138 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec);
1139
1140 u64 pci_get_dsn(struct pci_dev *dev);
1141
1142 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1143 struct pci_dev *from);
1144 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1145 unsigned int ss_vendor, unsigned int ss_device,
1146 struct pci_dev *from);
1147 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1148 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1149 unsigned int devfn);
1150 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1151 int pci_dev_present(const struct pci_device_id *ids);
1152
1153 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1154 int where, u8 *val);
1155 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1156 int where, u16 *val);
1157 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1158 int where, u32 *val);
1159 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1160 int where, u8 val);
1161 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1162 int where, u16 val);
1163 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1164 int where, u32 val);
1165
1166 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1167 int where, int size, u32 *val);
1168 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1169 int where, int size, u32 val);
1170 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1171 int where, int size, u32 *val);
1172 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1173 int where, int size, u32 val);
1174
1175 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1176
1177 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1178 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1179 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1180 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1181 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1182 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1183
1184 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1185 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1186 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1187 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1188 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1189 u16 clear, u16 set);
1190 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1191 u32 clear, u32 set);
1192
pcie_capability_set_word(struct pci_dev * dev,int pos,u16 set)1193 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1194 u16 set)
1195 {
1196 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1197 }
1198
pcie_capability_set_dword(struct pci_dev * dev,int pos,u32 set)1199 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1200 u32 set)
1201 {
1202 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1203 }
1204
pcie_capability_clear_word(struct pci_dev * dev,int pos,u16 clear)1205 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1206 u16 clear)
1207 {
1208 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1209 }
1210
pcie_capability_clear_dword(struct pci_dev * dev,int pos,u32 clear)1211 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1212 u32 clear)
1213 {
1214 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1215 }
1216
1217 /* User-space driven config access */
1218 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1219 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1220 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1221 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1222 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1223 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1224
1225 int __must_check pci_enable_device(struct pci_dev *dev);
1226 int __must_check pci_enable_device_io(struct pci_dev *dev);
1227 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1228 int __must_check pci_reenable_device(struct pci_dev *);
1229 int __must_check pcim_enable_device(struct pci_dev *pdev);
1230 void pcim_pin_device(struct pci_dev *pdev);
1231
pci_intx_mask_supported(struct pci_dev * pdev)1232 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1233 {
1234 /*
1235 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1236 * writable and no quirk has marked the feature broken.
1237 */
1238 return !pdev->broken_intx_masking;
1239 }
1240
pci_is_enabled(struct pci_dev * pdev)1241 static inline int pci_is_enabled(struct pci_dev *pdev)
1242 {
1243 return (atomic_read(&pdev->enable_cnt) > 0);
1244 }
1245
pci_is_managed(struct pci_dev * pdev)1246 static inline int pci_is_managed(struct pci_dev *pdev)
1247 {
1248 return pdev->is_managed;
1249 }
1250
1251 void pci_disable_device(struct pci_dev *dev);
1252
1253 extern unsigned int pcibios_max_latency;
1254 void pci_set_master(struct pci_dev *dev);
1255 void pci_clear_master(struct pci_dev *dev);
1256
1257 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1258 int pci_set_cacheline_size(struct pci_dev *dev);
1259 int __must_check pci_set_mwi(struct pci_dev *dev);
1260 int __must_check pcim_set_mwi(struct pci_dev *dev);
1261 int pci_try_set_mwi(struct pci_dev *dev);
1262 void pci_clear_mwi(struct pci_dev *dev);
1263 void pci_disable_parity(struct pci_dev *dev);
1264 void pci_intx(struct pci_dev *dev, int enable);
1265 bool pci_check_and_mask_intx(struct pci_dev *dev);
1266 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1267 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1268 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1269 int pcix_get_max_mmrbc(struct pci_dev *dev);
1270 int pcix_get_mmrbc(struct pci_dev *dev);
1271 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1272 int pcie_get_readrq(struct pci_dev *dev);
1273 int pcie_set_readrq(struct pci_dev *dev, int rq);
1274 int pcie_get_mps(struct pci_dev *dev);
1275 int pcie_set_mps(struct pci_dev *dev, int mps);
1276 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1277 enum pci_bus_speed *speed,
1278 enum pcie_link_width *width);
1279 void pcie_print_link_status(struct pci_dev *dev);
1280 int pcie_reset_flr(struct pci_dev *dev, bool probe);
1281 int pcie_flr(struct pci_dev *dev);
1282 int __pci_reset_function_locked(struct pci_dev *dev);
1283 int pci_reset_function(struct pci_dev *dev);
1284 int pci_reset_function_locked(struct pci_dev *dev);
1285 int pci_try_reset_function(struct pci_dev *dev);
1286 int pci_probe_reset_slot(struct pci_slot *slot);
1287 int pci_probe_reset_bus(struct pci_bus *bus);
1288 int pci_reset_bus(struct pci_dev *dev);
1289 void pci_reset_secondary_bus(struct pci_dev *dev);
1290 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1291 void pci_update_resource(struct pci_dev *dev, int resno);
1292 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1293 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1294 void pci_release_resource(struct pci_dev *dev, int resno);
pci_rebar_bytes_to_size(u64 bytes)1295 static inline int pci_rebar_bytes_to_size(u64 bytes)
1296 {
1297 bytes = roundup_pow_of_two(bytes);
1298
1299 /* Return BAR size as defined in the resizable BAR specification */
1300 return max(ilog2(bytes), 20) - 20;
1301 }
1302
1303 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1304 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1305 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1306 bool pci_device_is_present(struct pci_dev *pdev);
1307 void pci_ignore_hotplug(struct pci_dev *dev);
1308 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1309 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1310
1311 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1312 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1313 const char *fmt, ...);
1314 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1315
1316 /* ROM control related routines */
1317 int pci_enable_rom(struct pci_dev *pdev);
1318 void pci_disable_rom(struct pci_dev *pdev);
1319 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1320 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1321
1322 /* Power management related routines */
1323 int pci_save_state(struct pci_dev *dev);
1324 void pci_restore_state(struct pci_dev *dev);
1325 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1326 int pci_load_saved_state(struct pci_dev *dev,
1327 struct pci_saved_state *state);
1328 int pci_load_and_free_saved_state(struct pci_dev *dev,
1329 struct pci_saved_state **state);
1330 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1331 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1332 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1333 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1334 void pci_pme_active(struct pci_dev *dev, bool enable);
1335 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1336 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1337 int pci_prepare_to_sleep(struct pci_dev *dev);
1338 int pci_back_from_sleep(struct pci_dev *dev);
1339 bool pci_dev_run_wake(struct pci_dev *dev);
1340 void pci_d3cold_enable(struct pci_dev *dev);
1341 void pci_d3cold_disable(struct pci_dev *dev);
1342 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1343 void pci_resume_bus(struct pci_bus *bus);
1344 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1345
1346 /* For use by arch with custom probe code */
1347 void set_pcie_port_type(struct pci_dev *pdev);
1348 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1349
1350 /* Functions for PCI Hotplug drivers to use */
1351 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1352 unsigned int pci_rescan_bus(struct pci_bus *bus);
1353 void pci_lock_rescan_remove(void);
1354 void pci_unlock_rescan_remove(void);
1355
1356 /* Vital Product Data routines */
1357 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1358 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1359 ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1360 ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1361
1362 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1363 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1364 void pci_bus_assign_resources(const struct pci_bus *bus);
1365 void pci_bus_claim_resources(struct pci_bus *bus);
1366 void pci_bus_size_bridges(struct pci_bus *bus);
1367 int pci_claim_resource(struct pci_dev *, int);
1368 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1369 void pci_assign_unassigned_resources(void);
1370 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1371 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1372 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1373 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1374 void pdev_enable_device(struct pci_dev *);
1375 int pci_enable_resources(struct pci_dev *, int mask);
1376 void pci_assign_irq(struct pci_dev *dev);
1377 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1378 #define HAVE_PCI_REQ_REGIONS 2
1379 int __must_check pci_request_regions(struct pci_dev *, const char *);
1380 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1381 void pci_release_regions(struct pci_dev *);
1382 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1383 void pci_release_region(struct pci_dev *, int);
1384 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1385 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1386 void pci_release_selected_regions(struct pci_dev *, int);
1387
1388 /* drivers/pci/bus.c */
1389 void pci_add_resource(struct list_head *resources, struct resource *res);
1390 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1391 resource_size_t offset);
1392 void pci_free_resource_list(struct list_head *resources);
1393 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1394 unsigned int flags);
1395 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1396 void pci_bus_remove_resources(struct pci_bus *bus);
1397 int devm_request_pci_bus_resources(struct device *dev,
1398 struct list_head *resources);
1399
1400 /* Temporary until new and working PCI SBR API in place */
1401 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1402
1403 #define pci_bus_for_each_resource(bus, res, i) \
1404 for (i = 0; \
1405 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1406 i++)
1407
1408 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1409 struct resource *res, resource_size_t size,
1410 resource_size_t align, resource_size_t min,
1411 unsigned long type_mask,
1412 resource_size_t (*alignf)(void *,
1413 const struct resource *,
1414 resource_size_t,
1415 resource_size_t),
1416 void *alignf_data);
1417
1418
1419 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1420 resource_size_t size);
1421 unsigned long pci_address_to_pio(phys_addr_t addr);
1422 phys_addr_t pci_pio_to_address(unsigned long pio);
1423 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1424 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1425 phys_addr_t phys_addr);
1426 void pci_unmap_iospace(struct resource *res);
1427 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1428 resource_size_t offset,
1429 resource_size_t size);
1430 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1431 struct resource *res);
1432
pci_bus_address(struct pci_dev * pdev,int bar)1433 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1434 {
1435 struct pci_bus_region region;
1436
1437 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1438 return region.start;
1439 }
1440
1441 /* Proper probing supporting hot-pluggable devices */
1442 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1443 const char *mod_name);
1444
1445 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1446 #define pci_register_driver(driver) \
1447 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1448
1449 void pci_unregister_driver(struct pci_driver *dev);
1450
1451 /**
1452 * module_pci_driver() - Helper macro for registering a PCI driver
1453 * @__pci_driver: pci_driver struct
1454 *
1455 * Helper macro for PCI drivers which do not do anything special in module
1456 * init/exit. This eliminates a lot of boilerplate. Each module may only
1457 * use this macro once, and calling it replaces module_init() and module_exit()
1458 */
1459 #define module_pci_driver(__pci_driver) \
1460 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1461
1462 /**
1463 * builtin_pci_driver() - Helper macro for registering a PCI driver
1464 * @__pci_driver: pci_driver struct
1465 *
1466 * Helper macro for PCI drivers which do not do anything special in their
1467 * init code. This eliminates a lot of boilerplate. Each driver may only
1468 * use this macro once, and calling it replaces device_initcall(...)
1469 */
1470 #define builtin_pci_driver(__pci_driver) \
1471 builtin_driver(__pci_driver, pci_register_driver)
1472
1473 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1474 int pci_add_dynid(struct pci_driver *drv,
1475 unsigned int vendor, unsigned int device,
1476 unsigned int subvendor, unsigned int subdevice,
1477 unsigned int class, unsigned int class_mask,
1478 unsigned long driver_data);
1479 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1480 struct pci_dev *dev);
1481 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1482 int pass);
1483
1484 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1485 void *userdata);
1486 int pci_cfg_space_size(struct pci_dev *dev);
1487 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1488 void pci_setup_bridge(struct pci_bus *bus);
1489 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1490 unsigned long type);
1491
1492 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1493 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1494
1495 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1496 unsigned int command_bits, u32 flags);
1497
1498 /*
1499 * Virtual interrupts allow for more interrupts to be allocated
1500 * than the device has interrupts for. These are not programmed
1501 * into the device's MSI-X table and must be handled by some
1502 * other driver means.
1503 */
1504 #define PCI_IRQ_VIRTUAL (1 << 4)
1505
1506 #define PCI_IRQ_ALL_TYPES \
1507 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1508
1509 #include <linux/dmapool.h>
1510
1511 struct msix_entry {
1512 u32 vector; /* Kernel uses to write allocated vector */
1513 u16 entry; /* Driver uses to specify entry, OS writes */
1514 };
1515
1516 #ifdef CONFIG_PCI_MSI
1517 int pci_msi_vec_count(struct pci_dev *dev);
1518 void pci_disable_msi(struct pci_dev *dev);
1519 int pci_msix_vec_count(struct pci_dev *dev);
1520 void pci_disable_msix(struct pci_dev *dev);
1521 void pci_restore_msi_state(struct pci_dev *dev);
1522 int pci_msi_enabled(void);
1523 int pci_enable_msi(struct pci_dev *dev);
1524 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1525 int minvec, int maxvec);
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1526 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1527 struct msix_entry *entries, int nvec)
1528 {
1529 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1530 if (rc < 0)
1531 return rc;
1532 return 0;
1533 }
1534 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1535 unsigned int max_vecs, unsigned int flags,
1536 struct irq_affinity *affd);
1537
1538 void pci_free_irq_vectors(struct pci_dev *dev);
1539 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1540 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1541
1542 #else
pci_msi_vec_count(struct pci_dev * dev)1543 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msi(struct pci_dev * dev)1544 static inline void pci_disable_msi(struct pci_dev *dev) { }
pci_msix_vec_count(struct pci_dev * dev)1545 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msix(struct pci_dev * dev)1546 static inline void pci_disable_msix(struct pci_dev *dev) { }
pci_restore_msi_state(struct pci_dev * dev)1547 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
pci_msi_enabled(void)1548 static inline int pci_msi_enabled(void) { return 0; }
pci_enable_msi(struct pci_dev * dev)1549 static inline int pci_enable_msi(struct pci_dev *dev)
1550 { return -ENOSYS; }
pci_enable_msix_range(struct pci_dev * dev,struct msix_entry * entries,int minvec,int maxvec)1551 static inline int pci_enable_msix_range(struct pci_dev *dev,
1552 struct msix_entry *entries, int minvec, int maxvec)
1553 { return -ENOSYS; }
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1554 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1555 struct msix_entry *entries, int nvec)
1556 { return -ENOSYS; }
1557
1558 static inline int
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,struct irq_affinity * aff_desc)1559 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1560 unsigned int max_vecs, unsigned int flags,
1561 struct irq_affinity *aff_desc)
1562 {
1563 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1564 return 1;
1565 return -ENOSPC;
1566 }
1567
pci_free_irq_vectors(struct pci_dev * dev)1568 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1569 {
1570 }
1571
pci_irq_vector(struct pci_dev * dev,unsigned int nr)1572 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1573 {
1574 if (WARN_ON_ONCE(nr > 0))
1575 return -EINVAL;
1576 return dev->irq;
1577 }
pci_irq_get_affinity(struct pci_dev * pdev,int vec)1578 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1579 int vec)
1580 {
1581 return cpu_possible_mask;
1582 }
1583 #endif
1584
1585 /**
1586 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1587 * @d: the INTx IRQ domain
1588 * @node: the DT node for the device whose interrupt we're translating
1589 * @intspec: the interrupt specifier data from the DT
1590 * @intsize: the number of entries in @intspec
1591 * @out_hwirq: pointer at which to write the hwirq number
1592 * @out_type: pointer at which to write the interrupt type
1593 *
1594 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1595 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1596 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1597 * INTx value to obtain the hwirq number.
1598 *
1599 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1600 */
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1601 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1602 struct device_node *node,
1603 const u32 *intspec,
1604 unsigned int intsize,
1605 unsigned long *out_hwirq,
1606 unsigned int *out_type)
1607 {
1608 const u32 intx = intspec[0];
1609
1610 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1611 return -EINVAL;
1612
1613 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1614 return 0;
1615 }
1616
1617 #ifdef CONFIG_PCIEPORTBUS
1618 extern bool pcie_ports_disabled;
1619 extern bool pcie_ports_native;
1620 #else
1621 #define pcie_ports_disabled true
1622 #define pcie_ports_native false
1623 #endif
1624
1625 #define PCIE_LINK_STATE_L0S BIT(0)
1626 #define PCIE_LINK_STATE_L1 BIT(1)
1627 #define PCIE_LINK_STATE_CLKPM BIT(2)
1628 #define PCIE_LINK_STATE_L1_1 BIT(3)
1629 #define PCIE_LINK_STATE_L1_2 BIT(4)
1630 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1631 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1632
1633 #ifdef CONFIG_PCIEASPM
1634 int pci_disable_link_state(struct pci_dev *pdev, int state);
1635 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1636 void pcie_no_aspm(void);
1637 bool pcie_aspm_support_enabled(void);
1638 bool pcie_aspm_enabled(struct pci_dev *pdev);
1639 #else
pci_disable_link_state(struct pci_dev * pdev,int state)1640 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1641 { return 0; }
pci_disable_link_state_locked(struct pci_dev * pdev,int state)1642 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1643 { return 0; }
pcie_no_aspm(void)1644 static inline void pcie_no_aspm(void) { }
pcie_aspm_support_enabled(void)1645 static inline bool pcie_aspm_support_enabled(void) { return false; }
pcie_aspm_enabled(struct pci_dev * pdev)1646 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1647 #endif
1648
1649 #ifdef CONFIG_PCIEAER
1650 bool pci_aer_available(void);
1651 #else
pci_aer_available(void)1652 static inline bool pci_aer_available(void) { return false; }
1653 #endif
1654
1655 bool pci_ats_disabled(void);
1656
1657 #ifdef CONFIG_PCIE_PTM
1658 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1659 bool pcie_ptm_enabled(struct pci_dev *dev);
1660 #else
pci_enable_ptm(struct pci_dev * dev,u8 * granularity)1661 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1662 { return -EINVAL; }
pcie_ptm_enabled(struct pci_dev * dev)1663 static inline bool pcie_ptm_enabled(struct pci_dev *dev)
1664 { return false; }
1665 #endif
1666
1667 void pci_cfg_access_lock(struct pci_dev *dev);
1668 bool pci_cfg_access_trylock(struct pci_dev *dev);
1669 void pci_cfg_access_unlock(struct pci_dev *dev);
1670
1671 void pci_dev_lock(struct pci_dev *dev);
1672 int pci_dev_trylock(struct pci_dev *dev);
1673 void pci_dev_unlock(struct pci_dev *dev);
1674
1675 /*
1676 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1677 * a PCI domain is defined to be a set of PCI buses which share
1678 * configuration space.
1679 */
1680 #ifdef CONFIG_PCI_DOMAINS
1681 extern int pci_domains_supported;
1682 #else
1683 enum { pci_domains_supported = 0 };
pci_domain_nr(struct pci_bus * bus)1684 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_proc_domain(struct pci_bus * bus)1685 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1686 #endif /* CONFIG_PCI_DOMAINS */
1687
1688 /*
1689 * Generic implementation for PCI domain support. If your
1690 * architecture does not need custom management of PCI
1691 * domains then this implementation will be used
1692 */
1693 #ifdef CONFIG_PCI_DOMAINS_GENERIC
pci_domain_nr(struct pci_bus * bus)1694 static inline int pci_domain_nr(struct pci_bus *bus)
1695 {
1696 return bus->domain_nr;
1697 }
1698 #ifdef CONFIG_ACPI
1699 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1700 #else
acpi_pci_bus_find_domain_nr(struct pci_bus * bus)1701 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1702 { return 0; }
1703 #endif
1704 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1705 #endif
1706
1707 /* Some architectures require additional setup to direct VGA traffic */
1708 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1709 unsigned int command_bits, u32 flags);
1710 void pci_register_set_vga_state(arch_set_vga_state_t func);
1711
1712 static inline int
pci_request_io_regions(struct pci_dev * pdev,const char * name)1713 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1714 {
1715 return pci_request_selected_regions(pdev,
1716 pci_select_bars(pdev, IORESOURCE_IO), name);
1717 }
1718
1719 static inline void
pci_release_io_regions(struct pci_dev * pdev)1720 pci_release_io_regions(struct pci_dev *pdev)
1721 {
1722 return pci_release_selected_regions(pdev,
1723 pci_select_bars(pdev, IORESOURCE_IO));
1724 }
1725
1726 static inline int
pci_request_mem_regions(struct pci_dev * pdev,const char * name)1727 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1728 {
1729 return pci_request_selected_regions(pdev,
1730 pci_select_bars(pdev, IORESOURCE_MEM), name);
1731 }
1732
1733 static inline void
pci_release_mem_regions(struct pci_dev * pdev)1734 pci_release_mem_regions(struct pci_dev *pdev)
1735 {
1736 return pci_release_selected_regions(pdev,
1737 pci_select_bars(pdev, IORESOURCE_MEM));
1738 }
1739
1740 #else /* CONFIG_PCI is not enabled */
1741
pci_set_flags(int flags)1742 static inline void pci_set_flags(int flags) { }
pci_add_flags(int flags)1743 static inline void pci_add_flags(int flags) { }
pci_clear_flags(int flags)1744 static inline void pci_clear_flags(int flags) { }
pci_has_flag(int flag)1745 static inline int pci_has_flag(int flag) { return 0; }
1746
1747 /*
1748 * If the system does not have PCI, clearly these return errors. Define
1749 * these as simple inline functions to avoid hair in drivers.
1750 */
1751 #define _PCI_NOP(o, s, t) \
1752 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1753 int where, t val) \
1754 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1755
1756 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1757 _PCI_NOP(o, word, u16 x) \
1758 _PCI_NOP(o, dword, u32 x)
1759 _PCI_NOP_ALL(read, *)
1760 _PCI_NOP_ALL(write,)
1761
pci_get_device(unsigned int vendor,unsigned int device,struct pci_dev * from)1762 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1763 unsigned int device,
1764 struct pci_dev *from)
1765 { return NULL; }
1766
pci_get_subsys(unsigned int vendor,unsigned int device,unsigned int ss_vendor,unsigned int ss_device,struct pci_dev * from)1767 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1768 unsigned int device,
1769 unsigned int ss_vendor,
1770 unsigned int ss_device,
1771 struct pci_dev *from)
1772 { return NULL; }
1773
pci_get_class(unsigned int class,struct pci_dev * from)1774 static inline struct pci_dev *pci_get_class(unsigned int class,
1775 struct pci_dev *from)
1776 { return NULL; }
1777
1778 #define pci_dev_present(ids) (0)
1779 #define no_pci_devices() (1)
1780 #define pci_dev_put(dev) do { } while (0)
1781
pci_set_master(struct pci_dev * dev)1782 static inline void pci_set_master(struct pci_dev *dev) { }
pci_enable_device(struct pci_dev * dev)1783 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
pci_disable_device(struct pci_dev * dev)1784 static inline void pci_disable_device(struct pci_dev *dev) { }
pcim_enable_device(struct pci_dev * pdev)1785 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
pci_assign_resource(struct pci_dev * dev,int i)1786 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1787 { return -EBUSY; }
__pci_register_driver(struct pci_driver * drv,struct module * owner,const char * mod_name)1788 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1789 struct module *owner,
1790 const char *mod_name)
1791 { return 0; }
pci_register_driver(struct pci_driver * drv)1792 static inline int pci_register_driver(struct pci_driver *drv)
1793 { return 0; }
pci_unregister_driver(struct pci_driver * drv)1794 static inline void pci_unregister_driver(struct pci_driver *drv) { }
pci_find_capability(struct pci_dev * dev,int cap)1795 static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
1796 { return 0; }
pci_find_next_capability(struct pci_dev * dev,u8 post,int cap)1797 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1798 int cap)
1799 { return 0; }
pci_find_ext_capability(struct pci_dev * dev,int cap)1800 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1801 { return 0; }
1802
pci_get_dsn(struct pci_dev * dev)1803 static inline u64 pci_get_dsn(struct pci_dev *dev)
1804 { return 0; }
1805
1806 /* Power management related routines */
pci_save_state(struct pci_dev * dev)1807 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
pci_restore_state(struct pci_dev * dev)1808 static inline void pci_restore_state(struct pci_dev *dev) { }
pci_set_power_state(struct pci_dev * dev,pci_power_t state)1809 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1810 { return 0; }
pci_wake_from_d3(struct pci_dev * dev,bool enable)1811 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1812 { return 0; }
pci_choose_state(struct pci_dev * dev,pm_message_t state)1813 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1814 pm_message_t state)
1815 { return PCI_D0; }
pci_enable_wake(struct pci_dev * dev,pci_power_t state,int enable)1816 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1817 int enable)
1818 { return 0; }
1819
pci_find_resource(struct pci_dev * dev,struct resource * res)1820 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1821 struct resource *res)
1822 { return NULL; }
pci_request_regions(struct pci_dev * dev,const char * res_name)1823 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1824 { return -EIO; }
pci_release_regions(struct pci_dev * dev)1825 static inline void pci_release_regions(struct pci_dev *dev) { }
1826
pci_register_io_range(struct fwnode_handle * fwnode,phys_addr_t addr,resource_size_t size)1827 static inline int pci_register_io_range(struct fwnode_handle *fwnode,
1828 phys_addr_t addr, resource_size_t size)
1829 { return -EINVAL; }
1830
pci_address_to_pio(phys_addr_t addr)1831 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1832
pci_find_next_bus(const struct pci_bus * from)1833 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1834 { return NULL; }
pci_get_slot(struct pci_bus * bus,unsigned int devfn)1835 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1836 unsigned int devfn)
1837 { return NULL; }
pci_get_domain_bus_and_slot(int domain,unsigned int bus,unsigned int devfn)1838 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1839 unsigned int bus, unsigned int devfn)
1840 { return NULL; }
1841
pci_domain_nr(struct pci_bus * bus)1842 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_dev_get(struct pci_dev * dev)1843 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1844
1845 #define dev_is_pci(d) (false)
1846 #define dev_is_pf(d) (false)
pci_acs_enabled(struct pci_dev * pdev,u16 acs_flags)1847 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1848 { return false; }
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1849 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1850 struct device_node *node,
1851 const u32 *intspec,
1852 unsigned int intsize,
1853 unsigned long *out_hwirq,
1854 unsigned int *out_type)
1855 { return -EINVAL; }
1856
pci_match_id(const struct pci_device_id * ids,struct pci_dev * dev)1857 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1858 struct pci_dev *dev)
1859 { return NULL; }
pci_ats_disabled(void)1860 static inline bool pci_ats_disabled(void) { return true; }
1861
pci_irq_vector(struct pci_dev * dev,unsigned int nr)1862 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1863 {
1864 return -EINVAL;
1865 }
1866
1867 static inline int
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,struct irq_affinity * aff_desc)1868 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1869 unsigned int max_vecs, unsigned int flags,
1870 struct irq_affinity *aff_desc)
1871 {
1872 return -ENOSPC;
1873 }
1874 #endif /* CONFIG_PCI */
1875
1876 static inline int
pci_alloc_irq_vectors(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags)1877 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1878 unsigned int max_vecs, unsigned int flags)
1879 {
1880 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1881 NULL);
1882 }
1883
1884 /* Include architecture-dependent settings and functions */
1885
1886 #include <asm/pci.h>
1887
1888 /* These two functions provide almost identical functionality. Depending
1889 * on the architecture, one will be implemented as a wrapper around the
1890 * other (in drivers/pci/mmap.c).
1891 *
1892 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1893 * is expected to be an offset within that region.
1894 *
1895 * pci_mmap_page_range() is the legacy architecture-specific interface,
1896 * which accepts a "user visible" resource address converted by
1897 * pci_resource_to_user(), as used in the legacy mmap() interface in
1898 * /proc/bus/pci/.
1899 */
1900 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1901 struct vm_area_struct *vma,
1902 enum pci_mmap_state mmap_state, int write_combine);
1903 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1904 struct vm_area_struct *vma,
1905 enum pci_mmap_state mmap_state, int write_combine);
1906
1907 #ifndef arch_can_pci_mmap_wc
1908 #define arch_can_pci_mmap_wc() 0
1909 #endif
1910
1911 #ifndef arch_can_pci_mmap_io
1912 #define arch_can_pci_mmap_io() 0
1913 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1914 #else
1915 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1916 #endif
1917
1918 #ifndef pci_root_bus_fwnode
1919 #define pci_root_bus_fwnode(bus) NULL
1920 #endif
1921
1922 /*
1923 * These helpers provide future and backwards compatibility
1924 * for accessing popular PCI BAR info
1925 */
1926 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1927 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1928 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1929 #define pci_resource_len(dev,bar) \
1930 ((pci_resource_end((dev), (bar)) == 0) ? 0 : \
1931 \
1932 (pci_resource_end((dev), (bar)) - \
1933 pci_resource_start((dev), (bar)) + 1))
1934
1935 /*
1936 * Similar to the helpers above, these manipulate per-pci_dev
1937 * driver-specific data. They are really just a wrapper around
1938 * the generic device structure functions of these calls.
1939 */
pci_get_drvdata(struct pci_dev * pdev)1940 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1941 {
1942 return dev_get_drvdata(&pdev->dev);
1943 }
1944
pci_set_drvdata(struct pci_dev * pdev,void * data)1945 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1946 {
1947 dev_set_drvdata(&pdev->dev, data);
1948 }
1949
pci_name(const struct pci_dev * pdev)1950 static inline const char *pci_name(const struct pci_dev *pdev)
1951 {
1952 return dev_name(&pdev->dev);
1953 }
1954
1955 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1956 const struct resource *rsrc,
1957 resource_size_t *start, resource_size_t *end);
1958
1959 /*
1960 * The world is not perfect and supplies us with broken PCI devices.
1961 * For at least a part of these bugs we need a work-around, so both
1962 * generic (drivers/pci/quirks.c) and per-architecture code can define
1963 * fixup hooks to be called for particular buggy devices.
1964 */
1965
1966 struct pci_fixup {
1967 u16 vendor; /* Or PCI_ANY_ID */
1968 u16 device; /* Or PCI_ANY_ID */
1969 u32 class; /* Or PCI_ANY_ID */
1970 unsigned int class_shift; /* should be 0, 8, 16 */
1971 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1972 int hook_offset;
1973 #else
1974 void (*hook)(struct pci_dev *dev);
1975 #endif
1976 };
1977
1978 enum pci_fixup_pass {
1979 pci_fixup_early, /* Before probing BARs */
1980 pci_fixup_header, /* After reading configuration header */
1981 pci_fixup_final, /* Final phase of device fixups */
1982 pci_fixup_enable, /* pci_enable_device() time */
1983 pci_fixup_resume, /* pci_device_resume() */
1984 pci_fixup_suspend, /* pci_device_suspend() */
1985 pci_fixup_resume_early, /* pci_device_resume_early() */
1986 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1987 };
1988
1989 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1990 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1991 class_shift, hook) \
1992 __ADDRESSABLE(hook) \
1993 asm(".section " #sec ", \"a\" \n" \
1994 ".balign 16 \n" \
1995 ".short " #vendor ", " #device " \n" \
1996 ".long " #class ", " #class_shift " \n" \
1997 ".long " #hook " - . \n" \
1998 ".previous \n");
1999
2000 /*
2001 * Clang's LTO may rename static functions in C, but has no way to
2002 * handle such renamings when referenced from inline asm. To work
2003 * around this, create global C stubs for these cases.
2004 */
2005 #ifdef CONFIG_LTO_CLANG
2006 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2007 class_shift, hook, stub) \
2008 void __cficanonical stub(struct pci_dev *dev); \
2009 void __cficanonical stub(struct pci_dev *dev) \
2010 { \
2011 hook(dev); \
2012 } \
2013 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2014 class_shift, stub)
2015 #else
2016 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2017 class_shift, hook, stub) \
2018 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2019 class_shift, hook)
2020 #endif
2021
2022 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2023 class_shift, hook) \
2024 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2025 class_shift, hook, __UNIQUE_ID(hook))
2026 #else
2027 /* Anonymous variables would be nice... */
2028 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
2029 class_shift, hook) \
2030 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
2031 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
2032 = { vendor, device, class, class_shift, hook };
2033 #endif
2034
2035 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
2036 class_shift, hook) \
2037 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2038 hook, vendor, device, class, class_shift, hook)
2039 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
2040 class_shift, hook) \
2041 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2042 hook, vendor, device, class, class_shift, hook)
2043 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
2044 class_shift, hook) \
2045 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2046 hook, vendor, device, class, class_shift, hook)
2047 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
2048 class_shift, hook) \
2049 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2050 hook, vendor, device, class, class_shift, hook)
2051 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
2052 class_shift, hook) \
2053 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2054 resume##hook, vendor, device, class, class_shift, hook)
2055 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
2056 class_shift, hook) \
2057 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2058 resume_early##hook, vendor, device, class, class_shift, hook)
2059 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
2060 class_shift, hook) \
2061 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2062 suspend##hook, vendor, device, class, class_shift, hook)
2063 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2064 class_shift, hook) \
2065 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2066 suspend_late##hook, vendor, device, class, class_shift, hook)
2067
2068 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2069 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2070 hook, vendor, device, PCI_ANY_ID, 0, hook)
2071 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2072 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2073 hook, vendor, device, PCI_ANY_ID, 0, hook)
2074 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2075 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2076 hook, vendor, device, PCI_ANY_ID, 0, hook)
2077 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2078 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2079 hook, vendor, device, PCI_ANY_ID, 0, hook)
2080 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2081 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2082 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2083 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2084 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2085 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2086 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2087 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2088 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2089 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2090 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2091 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2092
2093 #ifdef CONFIG_PCI_QUIRKS
2094 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2095 #else
pci_fixup_device(enum pci_fixup_pass pass,struct pci_dev * dev)2096 static inline void pci_fixup_device(enum pci_fixup_pass pass,
2097 struct pci_dev *dev) { }
2098 #endif
2099
2100 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2101 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2102 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2103 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2104 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2105 const char *name);
2106 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2107
2108 extern int pci_pci_problems;
2109 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2110 #define PCIPCI_TRITON 2
2111 #define PCIPCI_NATOMA 4
2112 #define PCIPCI_VIAETBF 8
2113 #define PCIPCI_VSFX 16
2114 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2115 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2116
2117 extern unsigned long pci_cardbus_io_size;
2118 extern unsigned long pci_cardbus_mem_size;
2119 extern u8 pci_dfl_cache_line_size;
2120 extern u8 pci_cache_line_size;
2121
2122 /* Architecture-specific versions may override these (weak) */
2123 void pcibios_disable_device(struct pci_dev *dev);
2124 void pcibios_set_master(struct pci_dev *dev);
2125 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2126 enum pcie_reset_state state);
2127 int pcibios_device_add(struct pci_dev *dev);
2128 void pcibios_release_device(struct pci_dev *dev);
2129 #ifdef CONFIG_PCI
2130 void pcibios_penalize_isa_irq(int irq, int active);
2131 #else
pcibios_penalize_isa_irq(int irq,int active)2132 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2133 #endif
2134 int pcibios_alloc_irq(struct pci_dev *dev);
2135 void pcibios_free_irq(struct pci_dev *dev);
2136 resource_size_t pcibios_default_alignment(void);
2137
2138 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2139 void __init pci_mmcfg_early_init(void);
2140 void __init pci_mmcfg_late_init(void);
2141 #else
pci_mmcfg_early_init(void)2142 static inline void pci_mmcfg_early_init(void) { }
pci_mmcfg_late_init(void)2143 static inline void pci_mmcfg_late_init(void) { }
2144 #endif
2145
2146 int pci_ext_cfg_avail(void);
2147
2148 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2149 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2150
2151 #ifdef CONFIG_PCI_IOV
2152 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2153 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2154
2155 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2156 void pci_disable_sriov(struct pci_dev *dev);
2157
2158 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2159 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2160 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2161 int pci_num_vf(struct pci_dev *dev);
2162 int pci_vfs_assigned(struct pci_dev *dev);
2163 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2164 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2165 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2166 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2167 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2168
2169 /* Arch may override these (weak) */
2170 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2171 int pcibios_sriov_disable(struct pci_dev *pdev);
2172 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2173 #else
pci_iov_virtfn_bus(struct pci_dev * dev,int id)2174 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2175 {
2176 return -ENOSYS;
2177 }
pci_iov_virtfn_devfn(struct pci_dev * dev,int id)2178 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2179 {
2180 return -ENOSYS;
2181 }
pci_enable_sriov(struct pci_dev * dev,int nr_virtfn)2182 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2183 { return -ENODEV; }
2184
pci_iov_sysfs_link(struct pci_dev * dev,struct pci_dev * virtfn,int id)2185 static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2186 struct pci_dev *virtfn, int id)
2187 {
2188 return -ENODEV;
2189 }
pci_iov_add_virtfn(struct pci_dev * dev,int id)2190 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2191 {
2192 return -ENOSYS;
2193 }
pci_iov_remove_virtfn(struct pci_dev * dev,int id)2194 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2195 int id) { }
pci_disable_sriov(struct pci_dev * dev)2196 static inline void pci_disable_sriov(struct pci_dev *dev) { }
pci_num_vf(struct pci_dev * dev)2197 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
pci_vfs_assigned(struct pci_dev * dev)2198 static inline int pci_vfs_assigned(struct pci_dev *dev)
2199 { return 0; }
pci_sriov_set_totalvfs(struct pci_dev * dev,u16 numvfs)2200 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2201 { return 0; }
pci_sriov_get_totalvfs(struct pci_dev * dev)2202 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2203 { return 0; }
2204 #define pci_sriov_configure_simple NULL
pci_iov_resource_size(struct pci_dev * dev,int resno)2205 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2206 { return 0; }
pci_vf_drivers_autoprobe(struct pci_dev * dev,bool probe)2207 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2208 #endif
2209
2210 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2211 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2212 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2213 #endif
2214
2215 /**
2216 * pci_pcie_cap - get the saved PCIe capability offset
2217 * @dev: PCI device
2218 *
2219 * PCIe capability offset is calculated at PCI device initialization
2220 * time and saved in the data structure. This function returns saved
2221 * PCIe capability offset. Using this instead of pci_find_capability()
2222 * reduces unnecessary search in the PCI configuration space. If you
2223 * need to calculate PCIe capability offset from raw device for some
2224 * reasons, please use pci_find_capability() instead.
2225 */
pci_pcie_cap(struct pci_dev * dev)2226 static inline int pci_pcie_cap(struct pci_dev *dev)
2227 {
2228 return dev->pcie_cap;
2229 }
2230
2231 /**
2232 * pci_is_pcie - check if the PCI device is PCI Express capable
2233 * @dev: PCI device
2234 *
2235 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2236 */
pci_is_pcie(struct pci_dev * dev)2237 static inline bool pci_is_pcie(struct pci_dev *dev)
2238 {
2239 return pci_pcie_cap(dev);
2240 }
2241
2242 /**
2243 * pcie_caps_reg - get the PCIe Capabilities Register
2244 * @dev: PCI device
2245 */
pcie_caps_reg(const struct pci_dev * dev)2246 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2247 {
2248 return dev->pcie_flags_reg;
2249 }
2250
2251 /**
2252 * pci_pcie_type - get the PCIe device/port type
2253 * @dev: PCI device
2254 */
pci_pcie_type(const struct pci_dev * dev)2255 static inline int pci_pcie_type(const struct pci_dev *dev)
2256 {
2257 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2258 }
2259
2260 /**
2261 * pcie_find_root_port - Get the PCIe root port device
2262 * @dev: PCI device
2263 *
2264 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2265 * for a given PCI/PCIe Device.
2266 */
pcie_find_root_port(struct pci_dev * dev)2267 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2268 {
2269 while (dev) {
2270 if (pci_is_pcie(dev) &&
2271 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2272 return dev;
2273 dev = pci_upstream_bridge(dev);
2274 }
2275
2276 return NULL;
2277 }
2278
2279 void pci_request_acs(void);
2280 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2281 bool pci_acs_path_enabled(struct pci_dev *start,
2282 struct pci_dev *end, u16 acs_flags);
2283 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2284
2285 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2286 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2287
2288 /* Large Resource Data Type Tag Item Names */
2289 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2290 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2291 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2292
2293 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2294 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2295 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2296
2297 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2298 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2299 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2300 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2301 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2302
2303 /**
2304 * pci_vpd_alloc - Allocate buffer and read VPD into it
2305 * @dev: PCI device
2306 * @size: pointer to field where VPD length is returned
2307 *
2308 * Returns pointer to allocated buffer or an ERR_PTR in case of failure
2309 */
2310 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size);
2311
2312 /**
2313 * pci_vpd_find_id_string - Locate id string in VPD
2314 * @buf: Pointer to buffered VPD data
2315 * @len: The length of the buffer area in which to search
2316 * @size: Pointer to field where length of id string is returned
2317 *
2318 * Returns the index of the id string or -ENOENT if not found.
2319 */
2320 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size);
2321
2322 /**
2323 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section
2324 * @buf: Pointer to buffered VPD data
2325 * @len: The length of the buffer area in which to search
2326 * @kw: The keyword to search for
2327 * @size: Pointer to field where length of found keyword data is returned
2328 *
2329 * Returns the index of the information field keyword data or -ENOENT if
2330 * not found.
2331 */
2332 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
2333 const char *kw, unsigned int *size);
2334
2335 /**
2336 * pci_vpd_check_csum - Check VPD checksum
2337 * @buf: Pointer to buffered VPD data
2338 * @len: VPD size
2339 *
2340 * Returns 1 if VPD has no checksum, otherwise 0 or an errno
2341 */
2342 int pci_vpd_check_csum(const void *buf, unsigned int len);
2343
2344 /* PCI <-> OF binding helpers */
2345 #ifdef CONFIG_OF
2346 struct device_node;
2347 struct irq_domain;
2348 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2349 bool pci_host_of_has_msi_map(struct device *dev);
2350
2351 /* Arch may override this (weak) */
2352 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2353
2354 #else /* CONFIG_OF */
2355 static inline struct irq_domain *
pci_host_bridge_of_msi_domain(struct pci_bus * bus)2356 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
pci_host_of_has_msi_map(struct device * dev)2357 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; }
2358 #endif /* CONFIG_OF */
2359
2360 static inline struct device_node *
pci_device_to_OF_node(const struct pci_dev * pdev)2361 pci_device_to_OF_node(const struct pci_dev *pdev)
2362 {
2363 return pdev ? pdev->dev.of_node : NULL;
2364 }
2365
pci_bus_to_OF_node(struct pci_bus * bus)2366 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2367 {
2368 return bus ? bus->dev.of_node : NULL;
2369 }
2370
2371 #ifdef CONFIG_ACPI
2372 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2373
2374 void
2375 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2376 bool pci_pr3_present(struct pci_dev *pdev);
2377 #else
2378 static inline struct irq_domain *
pci_host_bridge_acpi_msi_domain(struct pci_bus * bus)2379 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
pci_pr3_present(struct pci_dev * pdev)2380 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2381 #endif
2382
2383 #ifdef CONFIG_EEH
pci_dev_to_eeh_dev(struct pci_dev * pdev)2384 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2385 {
2386 return pdev->dev.archdata.edev;
2387 }
2388 #endif
2389
2390 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2391 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2392 int pci_for_each_dma_alias(struct pci_dev *pdev,
2393 int (*fn)(struct pci_dev *pdev,
2394 u16 alias, void *data), void *data);
2395
2396 /* Helper functions for operation of device flag */
pci_set_dev_assigned(struct pci_dev * pdev)2397 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2398 {
2399 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2400 }
pci_clear_dev_assigned(struct pci_dev * pdev)2401 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2402 {
2403 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2404 }
pci_is_dev_assigned(struct pci_dev * pdev)2405 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2406 {
2407 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2408 }
2409
2410 /**
2411 * pci_ari_enabled - query ARI forwarding status
2412 * @bus: the PCI bus
2413 *
2414 * Returns true if ARI forwarding is enabled.
2415 */
pci_ari_enabled(struct pci_bus * bus)2416 static inline bool pci_ari_enabled(struct pci_bus *bus)
2417 {
2418 return bus->self && bus->self->ari_enabled;
2419 }
2420
2421 /**
2422 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2423 * @pdev: PCI device to check
2424 *
2425 * Walk upwards from @pdev and check for each encountered bridge if it's part
2426 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2427 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2428 */
pci_is_thunderbolt_attached(struct pci_dev * pdev)2429 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2430 {
2431 struct pci_dev *parent = pdev;
2432
2433 if (pdev->is_thunderbolt)
2434 return true;
2435
2436 while ((parent = pci_upstream_bridge(parent)))
2437 if (parent->is_thunderbolt)
2438 return true;
2439
2440 return false;
2441 }
2442
2443 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2444 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2445 #endif
2446
2447 /* Provide the legacy pci_dma_* API */
2448 #include <linux/pci-dma-compat.h>
2449
2450 #define pci_printk(level, pdev, fmt, arg...) \
2451 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2452
2453 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2454 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2455 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2456 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2457 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2458 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2459 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2460 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2461
2462 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2463 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2464
2465 #define pci_info_ratelimited(pdev, fmt, arg...) \
2466 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2467
2468 #define pci_WARN(pdev, condition, fmt, arg...) \
2469 WARN(condition, "%s %s: " fmt, \
2470 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2471
2472 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2473 WARN_ONCE(condition, "%s %s: " fmt, \
2474 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2475
2476 #endif /* LINUX_PCI_H */
2477