1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2018 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _ASM_ARCH_SDRAM_PHY_PX30_H 7 #define _ASM_ARCH_SDRAM_PHY_PX30_H 8 #include <asm/arch-rockchip/sdram_common.h> 9 #include <asm/arch-rockchip/sdram_phy_ron_rtt_px30.h> 10 11 #ifndef __ASSEMBLY__ 12 #include <linux/bitops.h> 13 #endif 14 15 struct ddr_phy_regs { 16 u32 phy[5][2]; 17 }; 18 19 #define PHY_REG(base, n) ((base) + 4 * (n)) 20 21 /* PHY_REG0 */ 22 #define DIGITAL_DERESET BIT(3) 23 #define ANALOG_DERESET BIT(2) 24 #define DIGITAL_RESET (0 << 3) 25 #define ANALOG_RESET (0 << 2) 26 27 /* PHY_REG1 */ 28 #define PHY_DDR2 (0) 29 #define PHY_LPDDR2 (1) 30 #define PHY_DDR3 (2) 31 #define PHY_LPDDR3 (3) 32 #define PHY_DDR4 (4) 33 #define PHY_BL_4 (0 << 2) 34 #define PHY_BL_8 BIT(2) 35 36 /* PHY_REG2 */ 37 #define PHY_DTT_EN BIT(0) 38 #define PHY_DTT_DISB (0 << 0) 39 #define PHY_WRITE_LEVELING_EN BIT(2) 40 #define PHY_WRITE_LEVELING_DISB (0 << 2) 41 #define PHY_SELECT_CS0 (2) 42 #define PHY_SELECT_CS1 (1) 43 #define PHY_SELECT_CS0_1 (0) 44 #define PHY_WRITE_LEVELING_SELECTCS(n) ((n) << 6) 45 #define PHY_DATA_TRAINING_SELECTCS(n) ((n) << 4) 46 47 struct ddr_phy_skew { 48 u32 a0_a1_skew[15]; 49 u32 cs0_dm0_skew[11]; 50 u32 cs0_dm1_skew[11]; 51 u32 cs0_dm2_skew[11]; 52 u32 cs0_dm3_skew[11]; 53 u32 cs1_dm0_skew[11]; 54 u32 cs1_dm1_skew[11]; 55 u32 cs1_dm2_skew[11]; 56 u32 cs1_dm3_skew[11]; 57 }; 58 59 void phy_soft_reset(void __iomem *phy_base); 60 void phy_dram_set_bw(void __iomem *phy_base, u32 bw); 61 void phy_cfg(void __iomem *phy_base, 62 struct ddr_phy_regs *phy_regs, struct ddr_phy_skew *skew, 63 struct sdram_base_params *base, u32 bw); 64 int phy_data_training(void __iomem *phy_base, u32 cs, u32 dramtype); 65 66 #endif 67