1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2009-2012 Freescale Semiconductor, Inc. 4 * Copyright 2020 NXP 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include <linux/stringify.h> 14 15 #include "../board/freescale/common/ics307_clk.h" 16 17 #ifdef CONFIG_RAMBOOT_PBL 18 #ifdef CONFIG_NXP_ESBC 19 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 20 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 21 #ifdef CONFIG_MTD_RAW_NAND 22 #define CONFIG_RAMBOOT_NAND 23 #endif 24 #define CONFIG_BOOTSCRIPT_COPY_RAM 25 #else 26 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 28 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 29 #if defined(CONFIG_TARGET_P3041DS) 30 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg 31 #elif defined(CONFIG_TARGET_P4080DS) 32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg 33 #elif defined(CONFIG_TARGET_P5020DS) 34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg 35 #elif defined(CONFIG_TARGET_P5040DS) 36 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg 37 #endif 38 #endif 39 #endif 40 41 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 42 /* Set 1M boot space */ 43 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 44 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 45 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 46 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 47 #endif 48 49 /* High Level Configuration Options */ 50 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 51 52 #ifndef CONFIG_RESET_VECTOR_ADDRESS 53 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 54 #endif 55 56 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 57 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 58 #define CONFIG_PCIE1 /* PCIE controller 1 */ 59 #define CONFIG_PCIE2 /* PCIE controller 2 */ 60 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 61 62 #if defined(CONFIG_SPIFLASH) 63 #elif defined(CONFIG_SDCARD) 64 #define CONFIG_FSL_FIXED_MMC_LOCATION 65 #endif 66 67 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 68 69 /* 70 * These can be toggled for performance analysis, otherwise use default. 71 */ 72 #define CONFIG_SYS_CACHE_STASHING 73 #define CONFIG_BACKSIDE_L2_CACHE 74 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 75 #define CONFIG_BTB /* toggle branch predition */ 76 #define CONFIG_DDR_ECC 77 #ifdef CONFIG_DDR_ECC 78 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 79 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 80 #endif 81 82 #define CONFIG_ENABLE_36BIT_PHYS 83 84 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 85 86 /* 87 * Config the L3 Cache as L3 SRAM 88 */ 89 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 90 #ifdef CONFIG_PHYS_64BIT 91 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 92 #else 93 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 94 #endif 95 #define CONFIG_SYS_L3_SIZE (1024 << 10) 96 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 97 98 #ifdef CONFIG_PHYS_64BIT 99 #define CONFIG_SYS_DCSRBAR 0xf0000000 100 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 101 #endif 102 103 /* EEPROM */ 104 #define CONFIG_ID_EEPROM 105 #define CONFIG_SYS_I2C_EEPROM_NXID 106 #define CONFIG_SYS_EEPROM_BUS_NUM 0 107 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 108 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 109 110 /* 111 * DDR Setup 112 */ 113 #define CONFIG_VERY_BIG_RAM 114 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 115 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 116 117 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 118 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 119 120 #define CONFIG_DDR_SPD 121 122 #define CONFIG_SYS_SPD_BUS_NUM 1 123 #define SPD_EEPROM_ADDRESS1 0x51 124 #define SPD_EEPROM_ADDRESS2 0x52 125 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 126 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 127 128 /* 129 * Local Bus Definitions 130 */ 131 132 /* Set the local bus clock 1/8 of platform clock */ 133 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 134 135 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 136 #ifdef CONFIG_PHYS_64BIT 137 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 138 #else 139 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 140 #endif 141 142 #define CONFIG_SYS_FLASH_BR_PRELIM \ 143 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ 144 | BR_PS_16 | BR_V) 145 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 146 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 147 148 #define CONFIG_SYS_BR1_PRELIM \ 149 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 150 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 151 152 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 153 #ifdef CONFIG_PHYS_64BIT 154 #define PIXIS_BASE_PHYS 0xfffdf0000ull 155 #else 156 #define PIXIS_BASE_PHYS PIXIS_BASE 157 #endif 158 159 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 160 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 161 162 #define PIXIS_LBMAP_SWITCH 7 163 #define PIXIS_LBMAP_MASK 0xf0 164 #define PIXIS_LBMAP_SHIFT 4 165 #define PIXIS_LBMAP_ALTBANK 0x40 166 167 #define CONFIG_SYS_FLASH_QUIET_TEST 168 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 169 170 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 171 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 172 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 173 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 174 175 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 176 177 #if defined(CONFIG_RAMBOOT_PBL) 178 #define CONFIG_SYS_RAMBOOT 179 #endif 180 181 /* Nand Flash */ 182 #ifdef CONFIG_NAND_FSL_ELBC 183 #define CONFIG_SYS_NAND_BASE 0xffa00000 184 #ifdef CONFIG_PHYS_64BIT 185 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 186 #else 187 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 188 #endif 189 190 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 191 #define CONFIG_SYS_MAX_NAND_DEVICE 1 192 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 193 194 /* NAND flash config */ 195 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 196 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 197 | BR_PS_8 /* Port Size = 8 bit */ \ 198 | BR_MS_FCM /* MSEL = FCM */ \ 199 | BR_V) /* valid */ 200 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 201 | OR_FCM_PGS /* Large Page*/ \ 202 | OR_FCM_CSCT \ 203 | OR_FCM_CST \ 204 | OR_FCM_CHT \ 205 | OR_FCM_SCY_1 \ 206 | OR_FCM_TRLX \ 207 | OR_FCM_EHTR) 208 209 #ifdef CONFIG_MTD_RAW_NAND 210 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 211 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 212 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 213 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 214 #else 215 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 216 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 217 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 218 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 219 #endif 220 #else 221 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 222 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 223 #endif /* CONFIG_NAND_FSL_ELBC */ 224 225 #define CONFIG_SYS_FLASH_EMPTY_INFO 226 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 227 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 228 229 #define CONFIG_HWCONFIG 230 231 /* define to use L1 as initial stack */ 232 #define CONFIG_L1_INIT_RAM 233 #define CONFIG_SYS_INIT_RAM_LOCK 234 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 235 #ifdef CONFIG_PHYS_64BIT 236 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 237 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 238 /* The assembler doesn't like typecast */ 239 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 240 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 241 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 242 #else 243 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 244 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 245 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 246 #endif 247 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 248 249 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 250 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 251 252 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 253 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 254 255 /* Serial Port - controlled on board with jumper J8 256 * open - index 2 257 * shorted - index 1 258 */ 259 #define CONFIG_SYS_NS16550_SERIAL 260 #define CONFIG_SYS_NS16550_REG_SIZE 1 261 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 262 263 #define CONFIG_SYS_BAUDRATE_TABLE \ 264 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 265 266 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 267 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 268 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 269 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 270 271 /* I2C */ 272 #if !CONFIG_IS_ENABLED(DM_I2C) 273 #define CONFIG_SYS_I2C 274 #define CONFIG_SYS_FSL_I2C_SPEED 400000 275 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 276 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 277 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 278 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 279 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 280 #else 281 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM 282 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 283 #endif 284 #define CONFIG_SYS_I2C_FSL 285 286 /* 287 * RapidIO 288 */ 289 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 290 #ifdef CONFIG_PHYS_64BIT 291 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 292 #else 293 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 294 #endif 295 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 296 297 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 298 #ifdef CONFIG_PHYS_64BIT 299 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 300 #else 301 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 302 #endif 303 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 304 305 /* 306 * for slave u-boot IMAGE instored in master memory space, 307 * PHYS must be aligned based on the SIZE 308 */ 309 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 310 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 311 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 312 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 313 /* 314 * for slave UCODE and ENV instored in master memory space, 315 * PHYS must be aligned based on the SIZE 316 */ 317 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 318 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 319 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 320 321 /* slave core release by master*/ 322 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 323 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 324 325 /* 326 * SRIO_PCIE_BOOT - SLAVE 327 */ 328 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 329 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 330 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 331 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 332 #endif 333 334 /* 335 * eSPI - Enhanced SPI 336 */ 337 338 /* 339 * General PCI 340 * Memory space is mapped 1-1, but I/O space must start from 0. 341 */ 342 343 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 344 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 345 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 346 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 347 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 348 349 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 350 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 351 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 352 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 353 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 354 355 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 356 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 357 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 358 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 359 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 360 361 /* controller 4, Base address 203000 */ 362 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 363 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 364 365 /* Qman/Bman */ 366 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 367 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 368 #ifdef CONFIG_PHYS_64BIT 369 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 370 #else 371 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 372 #endif 373 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 374 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 375 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 376 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 377 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 378 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 379 CONFIG_SYS_BMAN_CENA_SIZE) 380 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 381 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 382 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 383 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 384 #ifdef CONFIG_PHYS_64BIT 385 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 386 #else 387 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 388 #endif 389 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 390 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 391 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 392 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 393 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 394 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 395 CONFIG_SYS_QMAN_CENA_SIZE) 396 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 397 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 398 399 #define CONFIG_SYS_DPAA_FMAN 400 #define CONFIG_SYS_DPAA_PME 401 /* Default address of microcode for the Linux Fman driver */ 402 #if defined(CONFIG_SPIFLASH) 403 /* 404 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 405 * env, so we got 0x110000. 406 */ 407 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 408 #elif defined(CONFIG_SDCARD) 409 /* 410 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 411 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 412 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 413 */ 414 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 415 #elif defined(CONFIG_MTD_RAW_NAND) 416 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 417 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 418 /* 419 * Slave has no ucode locally, it can fetch this from remote. When implementing 420 * in two corenet boards, slave's ucode could be stored in master's memory 421 * space, the address can be mapped from slave TLB->slave LAW-> 422 * slave SRIO or PCIE outbound window->master inbound window-> 423 * master LAW->the ucode address in master's memory space. 424 */ 425 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 426 #else 427 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 428 #endif 429 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 430 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 431 432 #ifdef CONFIG_PCI 433 #if !defined(CONFIG_DM_PCI) 434 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 435 #define CONFIG_PCI_INDIRECT_BRIDGE 436 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 437 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 438 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 439 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 440 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 441 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 442 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 443 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 444 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 445 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 446 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 447 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 448 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 449 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 450 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 451 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 452 #endif 453 454 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 455 #endif /* CONFIG_PCI */ 456 457 /* SATA */ 458 #ifdef CONFIG_FSL_SATA_V2 459 #define CONFIG_SYS_SATA_MAX_DEVICE 2 460 #define CONFIG_SATA1 461 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 462 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 463 #define CONFIG_SATA2 464 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 465 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 466 467 #define CONFIG_LBA48 468 #endif 469 470 #ifdef CONFIG_FMAN_ENET 471 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 472 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 473 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 474 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 475 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 476 477 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 478 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 479 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 480 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 481 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 482 483 #define CONFIG_SYS_TBIPA_VALUE 8 484 #define CONFIG_ETHPRIME "FM1@DTSEC1" 485 #endif 486 487 /* 488 * Environment 489 */ 490 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 491 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 492 493 /* 494 * USB 495 */ 496 #define CONFIG_HAS_FSL_DR_USB 497 #define CONFIG_HAS_FSL_MPH_USB 498 499 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 500 #define CONFIG_USB_EHCI_FSL 501 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 502 #endif 503 504 #ifdef CONFIG_MMC 505 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 506 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 507 #endif 508 509 /* 510 * Miscellaneous configurable options 511 */ 512 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 513 514 /* 515 * For booting Linux, the board info and command line data 516 * have to be in the first 64 MB of memory, since this is 517 * the maximum mapped by the Linux kernel during initialization. 518 */ 519 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 520 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 521 522 #ifdef CONFIG_CMD_KGDB 523 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 524 #endif 525 526 /* 527 * Environment Configuration 528 */ 529 #define CONFIG_ROOTPATH "/opt/nfsroot" 530 #define CONFIG_BOOTFILE "uImage" 531 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 532 533 /* default location for tftp and bootm */ 534 #define CONFIG_LOADADDR 1000000 535 536 #ifdef CONFIG_TARGET_P4080DS 537 #define __USB_PHY_TYPE ulpi 538 #else 539 #define __USB_PHY_TYPE utmi 540 #endif 541 542 #define CONFIG_EXTRA_ENV_SETTINGS \ 543 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 544 "bank_intlv=cs0_cs1;" \ 545 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 546 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 547 "netdev=eth0\0" \ 548 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 549 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 550 "tftpflash=tftpboot $loadaddr $uboot && " \ 551 "protect off $ubootaddr +$filesize && " \ 552 "erase $ubootaddr +$filesize && " \ 553 "cp.b $loadaddr $ubootaddr $filesize && " \ 554 "protect on $ubootaddr +$filesize && " \ 555 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 556 "consoledev=ttyS0\0" \ 557 "ramdiskaddr=2000000\0" \ 558 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 559 "fdtaddr=1e00000\0" \ 560 "fdtfile=p4080ds/p4080ds.dtb\0" \ 561 "bdev=sda3\0" 562 563 #define CONFIG_HDBOOT \ 564 "setenv bootargs root=/dev/$bdev rw " \ 565 "console=$consoledev,$baudrate $othbootargs;" \ 566 "tftp $loadaddr $bootfile;" \ 567 "tftp $fdtaddr $fdtfile;" \ 568 "bootm $loadaddr - $fdtaddr" 569 570 #define CONFIG_NFSBOOTCOMMAND \ 571 "setenv bootargs root=/dev/nfs rw " \ 572 "nfsroot=$serverip:$rootpath " \ 573 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 574 "console=$consoledev,$baudrate $othbootargs;" \ 575 "tftp $loadaddr $bootfile;" \ 576 "tftp $fdtaddr $fdtfile;" \ 577 "bootm $loadaddr - $fdtaddr" 578 579 #define CONFIG_RAMBOOTCOMMAND \ 580 "setenv bootargs root=/dev/ram rw " \ 581 "console=$consoledev,$baudrate $othbootargs;" \ 582 "tftp $ramdiskaddr $ramdiskfile;" \ 583 "tftp $loadaddr $bootfile;" \ 584 "tftp $fdtaddr $fdtfile;" \ 585 "bootm $loadaddr $ramdiskaddr $fdtaddr" 586 587 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 588 589 #include <asm/fsl_secure_boot.h> 590 591 #endif /* __CONFIG_H */ 592