1 /* 2 * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SGM_BASE_PLATFORM_DEF_H 8 #define SGM_BASE_PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <drivers/arm/tzc_common.h> 12 #include <plat/arm/board/common/board_css_def.h> 13 #include <plat/arm/board/common/v2m_def.h> 14 #include <plat/arm/common/arm_def.h> 15 #include <plat/arm/css/common/css_def.h> 16 #include <plat/arm/soc/common/soc_css_def.h> 17 #include <plat/common/common_def.h> 18 19 /* CPU topology */ 20 #define PLAT_ARM_CLUSTER_COUNT U(1) 21 #define PLAT_ARM_CLUSTER_CORE_COUNT U(8) 22 #define PLATFORM_CORE_COUNT PLAT_ARM_CLUSTER_CORE_COUNT 23 24 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 25 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ 26 PLAT_ARM_CLUSTER_COUNT + \ 27 PLATFORM_CORE_COUNT) 28 29 /* 30 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 31 * terminology. On a GICv2 system or mode, the lists will be merged and treated 32 * as Group 0 interrupts. 33 */ 34 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 35 CSS_G1S_IRQ_PROPS(grp), \ 36 ARM_G1S_IRQ_PROPS(grp) 37 38 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 39 40 /* GIC related constants */ 41 #define PLAT_ARM_GICD_BASE 0x30000000 42 #define PLAT_ARM_GICR_BASE 0x300C0000 43 #define PLAT_ARM_GICC_BASE 0x2c000000 44 45 #define CSS_GIC_SIZE 0x00200000 46 47 #define CSS_MAP_GIC_DEVICE MAP_REGION_FLAT( \ 48 PLAT_ARM_GICD_BASE, \ 49 CSS_GIC_SIZE, \ 50 MT_DEVICE | MT_RW | MT_SECURE) 51 52 /* Platform ID address */ 53 #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) 54 #ifndef __ASSEMBLER__ 55 /* SSC_VERSION related accessors */ 56 /* Returns the part number of the platform */ 57 #define GET_PLAT_PART_NUM \ 58 GET_SSC_VERSION_PART_NUM(mmio_read_32(SSC_VERSION)) 59 /* Returns the configuration number of the platform */ 60 #define GET_PLAT_CONFIG_NUM \ 61 GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION)) 62 #endif /* __ASSEMBLER__ */ 63 64 65 /************************************************************************* 66 * Definitions common to all SGM CSS based platforms 67 *************************************************************************/ 68 69 /* TZC-400 related constants */ 70 #define PLAT_ARM_TZC_BASE 0x2a500000 71 #define TZC_NSAID_ALL_AP 0 /* Note: Same as default NSAID!! */ 72 #define TZC_NSAID_HDLCD0 2 73 #define TZC_NSAID_HDLCD1 3 74 #define TZC_NSAID_GPU 9 75 #define TZC_NSAID_VIDEO 10 76 #define TZC_NSAID_DISP0 11 77 #define TZC_NSAID_DISP1 12 78 79 80 /************************************************************************* 81 * Required platform porting definitions common to all SGM CSS based 82 * platforms 83 *************************************************************************/ 84 85 #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */ 86 87 /* MHU related constants */ 88 #define PLAT_CSS_MHU_BASE 0x2b1f0000 89 90 #define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 91 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 92 93 #define PLAT_ARM_CCI_BASE 0x2a000000 94 95 /* Cluster to CCI slave mapping */ 96 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 6 97 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5 98 99 /* System timer related constants */ 100 #define PLAT_ARM_NSTIMER_FRAME_ID 0 101 102 /* TZC related constants */ 103 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 104 TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP) | \ 105 TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0) | \ 106 TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD1) | \ 107 TZC_REGION_ACCESS_RDWR(TZC_NSAID_GPU) | \ 108 TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIDEO) | \ 109 TZC_REGION_ACCESS_RDWR(TZC_NSAID_DISP0) | \ 110 TZC_REGION_ACCESS_RDWR(TZC_NSAID_DISP1)) 111 112 /* Display Processor register definitions to setup the NSAIDs */ 113 #define MALI_DP_BASE 0x2cc00000 114 #define DP_NPROT_NSAID_OFFSET 0x1000c 115 #define W_NPROT_NSAID_SHIFT 24 116 #define LS_NPORT_NSAID_SHIFT 12 117 118 /* 119 * Base address of the first memory region used for communication between AP 120 * and SCP. Used by the BootOverMHU and SCPI protocols. 121 */ 122 #if !CSS_USE_SCMI_SDS_DRIVER 123 /* 124 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 125 * means the SCP/AP configuration data gets overwritten when the AP initiates 126 * communication with the SCP. The configuration data is expected to be a 127 * 32-bit word on all CSS platforms. Part of this configuration is 128 * which CPU is the primary, according to the shift and mask definitions below. 129 */ 130 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80) 131 #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 132 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 133 #endif 134 135 /* 136 * SCP_BL2 uses up whatever remaining space is available as it is loaded before 137 * anything else in this memory region and is handed over to the SCP before 138 * BL31 is loaded over the top. 139 */ 140 #define PLAT_CSS_MAX_SCP_BL2_SIZE \ 141 ((SCP_BL2_LIMIT - ARM_FW_CONFIG_LIMIT) & ~PAGE_SIZE_MASK) 142 143 #define PLAT_CSS_MAX_SCP_BL2U_SIZE PLAT_CSS_MAX_SCP_BL2_SIZE 144 145 /* 146 * Most platform porting definitions provided by included headers 147 */ 148 149 /* 150 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 151 * plat_arm_mmap array defined for each BL stage. 152 */ 153 #if defined(IMAGE_BL31) 154 # define PLAT_ARM_MMAP_ENTRIES 8 155 # define MAX_XLAT_TABLES 5 156 #elif defined(IMAGE_BL32) 157 # define PLAT_ARM_MMAP_ENTRIES 8 158 # define MAX_XLAT_TABLES 5 159 #elif !USE_ROMLIB 160 # define PLAT_ARM_MMAP_ENTRIES 11 161 # define MAX_XLAT_TABLES 5 162 #else 163 # define PLAT_ARM_MMAP_ENTRIES 12 164 # define MAX_XLAT_TABLES 6 165 #endif 166 167 /* 168 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 169 * plus a little space for growth. 170 */ 171 #define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000 172 173 /* 174 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 175 */ 176 177 #if USE_ROMLIB 178 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 179 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 180 #else 181 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 182 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 183 #endif 184 185 /* 186 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 187 * little space for growth. 188 */ 189 #if TRUSTED_BOARD_BOOT 190 # define PLAT_ARM_MAX_BL2_SIZE 0x1D000 191 #else 192 # define PLAT_ARM_MAX_BL2_SIZE 0x12000 193 #endif 194 195 /* 196 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 197 * calculated using the current BL31 PROGBITS debug size plus the sizes of 198 * BL2 and BL1-RW 199 */ 200 #define PLAT_ARM_MAX_BL31_SIZE 0x3B000 201 202 /* 203 * Size of cacheable stacks 204 */ 205 #if defined(IMAGE_BL1) 206 # if TRUSTED_BOARD_BOOT 207 # define PLATFORM_STACK_SIZE 0x1000 208 # else 209 # define PLATFORM_STACK_SIZE 0x440 210 # endif 211 #elif defined(IMAGE_BL2) 212 # if TRUSTED_BOARD_BOOT 213 # define PLATFORM_STACK_SIZE 0x1000 214 # else 215 # define PLATFORM_STACK_SIZE 0x400 216 # endif 217 #elif defined(IMAGE_BL2U) 218 # define PLATFORM_STACK_SIZE 0x400 219 #elif defined(IMAGE_BL31) 220 # define PLATFORM_STACK_SIZE 0x400 221 #elif defined(IMAGE_BL32) 222 # define PLATFORM_STACK_SIZE 0x440 223 #endif 224 225 /******************************************************************************* 226 * Memprotect definitions 227 ******************************************************************************/ 228 /* PSCI memory protect definitions: 229 * This variable is stored in a non-secure flash because some ARM reference 230 * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT 231 * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. 232 */ 233 #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ 234 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 235 236 /* System power domain level */ 237 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 238 239 /* Number of SCMI channels on the platform */ 240 #define PLAT_ARM_SCMI_CHANNEL_COUNT U(1) 241 242 #endif /* SGM_BASE_PLATFORM_DEF_H */ 243