1 /* 2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <plat/common/common_def.h> 12 #include <platform_def.h> 13 #include "../fpga_def.h" 14 15 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 16 17 #define PLATFORM_LINKER_ARCH aarch64 18 19 #define PLATFORM_STACK_SIZE UL(0x800) 20 21 #define CACHE_WRITEBACK_SHIFT U(6) 22 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 23 24 #define PLATFORM_CORE_COUNT \ 25 (FPGA_MAX_CLUSTER_COUNT * \ 26 FPGA_MAX_CPUS_PER_CLUSTER * \ 27 FPGA_MAX_PE_PER_CPU) 28 29 #define PLAT_NUM_PWR_DOMAINS (FPGA_MAX_CLUSTER_COUNT + PLATFORM_CORE_COUNT + 1) 30 31 #if !ENABLE_PIE 32 #define BL31_BASE UL(0x80000000) 33 #define BL31_LIMIT UL(0x80070000) 34 #else 35 #define BL31_BASE UL(0x0) 36 #define BL31_LIMIT UL(0x01000000) 37 #endif 38 39 #define PLAT_SDEI_NORMAL_PRI 0x70 40 41 #define ARM_IRQ_SEC_PHY_TIMER 29 42 43 #define ARM_IRQ_SEC_SGI_0 8 44 #define ARM_IRQ_SEC_SGI_1 9 45 #define ARM_IRQ_SEC_SGI_2 10 46 #define ARM_IRQ_SEC_SGI_3 11 47 #define ARM_IRQ_SEC_SGI_4 12 48 #define ARM_IRQ_SEC_SGI_5 13 49 #define ARM_IRQ_SEC_SGI_6 14 50 #define ARM_IRQ_SEC_SGI_7 15 51 52 /* 53 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 54 * terminology. On a GICv2 system or mode, the lists will be merged and treated 55 * as Group 0 interrupts. 56 */ 57 #define PLATFORM_G1S_PROPS(grp) \ 58 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 59 GIC_INTR_CFG_LEVEL), \ 60 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 61 GIC_INTR_CFG_EDGE), \ 62 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 63 GIC_INTR_CFG_EDGE), \ 64 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 65 GIC_INTR_CFG_EDGE), \ 66 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 67 GIC_INTR_CFG_EDGE), \ 68 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 69 GIC_INTR_CFG_EDGE), \ 70 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 71 GIC_INTR_CFG_EDGE) 72 73 #define PLATFORM_G0_PROPS(grp) \ 74 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 75 GIC_INTR_CFG_EDGE), \ 76 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 77 GIC_INTR_CFG_EDGE) 78 79 #define PLAT_MAX_RET_STATE 1 80 #define PLAT_MAX_OFF_STATE 2 81 82 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 83 84 #define PLAT_FPGA_HOLD_ENTRY_SHIFT 3 85 #define PLAT_FPGA_HOLD_STATE_WAIT 0 86 #define PLAT_FPGA_HOLD_STATE_GO 1 87 88 #endif 89