1 /* 2 * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef FVP_R_PLATFORM_DEF_H 8 #define FVP_R_PLATFORM_DEF_H 9 10 #define PLAT_V2M_OFFSET 0x80000000 11 12 #define BL33_IMAGE_DESC { \ 13 .image_id = BL33_IMAGE_ID, \ 14 SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, \ 15 VERSION_2, image_info_t, 0), \ 16 .image_info.image_base = PLAT_ARM_DRAM1_BASE + 0x1000, \ 17 .image_info.image_max_size = UL(0x3ffff000), \ 18 SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, \ 19 VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),\ 20 .ep_info.pc = PLAT_ARM_DRAM1_BASE + 0x1000, \ 21 .ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS), \ 22 } 23 24 #include "../fvp_r_def.h" 25 #include <drivers/arm/tzc400.h> 26 #include <lib/utils_def.h> 27 #include <plat/arm/board/common/v2m_def.h> 28 29 /* These are referenced by arm_def.h #included next, so #define first. */ 30 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x80000000) 31 #define PLAT_ARM_TRUSTED_SRAM_BASE UL(0x84000000) 32 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x86000000) 33 #define PLAT_ARM_DRAM1_BASE ULL(0x0) 34 #define PLAT_ARM_DRAM2_BASE ULL(0x080000000) 35 36 #define PLAT_HW_CONFIG_DTB_BASE ULL(0x12000000) 37 #define PLAT_ARM_SYS_CNTCTL_BASE UL(0xaa430000) 38 #define PLAT_ARM_SYS_CNTREAD_BASE UL(0xaa800000) 39 #define PLAT_ARM_SYS_TIMCTL_BASE UL(0xaa810000) 40 #define PLAT_ARM_SYS_CNT_BASE_S UL(0xaa820000) 41 #define PLAT_ARM_SYS_CNT_BASE_NS UL(0xaa830000) 42 #define PLAT_ARM_SP805_TWDG_BASE UL(0xaa490000) 43 44 #include <plat/arm/common/arm_def.h> 45 #include <plat/common/common_def.h> 46 47 48 /* Required to create plat_regions: */ 49 #define MIN_LVL_BLOCK_DESC U(1) 50 51 /* Required platform porting definitions */ 52 #define PLATFORM_CORE_COUNT (U(FVP_R_CLUSTER_COUNT) * \ 53 U(FVP_R_MAX_CPUS_PER_CLUSTER) * \ 54 U(FVP_R_MAX_PE_PER_CPU)) 55 56 #define PLAT_NUM_PWR_DOMAINS (U(FVP_R_CLUSTER_COUNT) + \ 57 PLATFORM_CORE_COUNT + U(1)) 58 59 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 60 61 /* 62 * Other platform porting definitions are provided by included headers 63 */ 64 65 /* 66 * Required ARM standard platform porting definitions 67 */ 68 #define PLAT_ARM_CLUSTER_COUNT U(FVP_R_CLUSTER_COUNT) 69 #define PLAT_ARM_DRAM1_SIZE ULL(0x7fffffff) 70 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 71 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 72 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 73 74 /* These two are defined thus in arm_def.h, but doesn't seem to see it... */ 75 #define PLAT_BL1_RO_LIMIT (BL1_RO_BASE \ 76 + PLAT_ARM_TRUSTED_ROM_SIZE) 77 78 #define PLAT_ARM_SYS_CNTCTL_BASE UL(0xaa430000) 79 #define PLAT_ARM_SYS_CNTREAD_BASE UL(0xaa800000) 80 #define PLAT_ARM_SYS_TIMCTL_BASE UL(0xaa810000) 81 #define PLAT_ARM_SYS_CNT_BASE_S UL(0xaa820000) 82 #define PLAT_ARM_SYS_CNT_BASE_NS UL(0xaa830000) 83 #define PLAT_ARM_SP805_TWDG_BASE UL(0xaa490000) 84 85 /* virtual address used by dynamic mem_protect for chunk_base */ 86 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 87 88 /* No SCP in FVP_R */ 89 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 90 91 #define PLAT_ARM_DRAM2_SIZE UL(0x80000000) 92 93 #define PLAT_HW_CONFIG_DTB_SIZE ULL(0x8000) 94 95 #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ 96 PLAT_HW_CONFIG_DTB_BASE, \ 97 PLAT_HW_CONFIG_DTB_SIZE, \ 98 MT_MEMORY | MT_RO | MT_NS) 99 100 #define V2M_FVP_R_SYSREGS_BASE UL(0x9c010000) 101 102 /* 103 * Load address of BL33 for this platform port, 104 * U-Boot specifically must be loaded at a 4K aligned address. 105 */ 106 #define PLAT_ARM_NS_IMAGE_BASE (PLAT_ARM_DRAM1_BASE + 0x1000) 107 108 /* 109 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 110 * plat_arm_mmap array defined for each BL stage. 111 */ 112 #if !USE_ROMLIB 113 # define PLAT_ARM_MMAP_ENTRIES 11 114 # define MAX_XLAT_TABLES 5 115 #else 116 # define PLAT_ARM_MMAP_ENTRIES 12 117 # define MAX_XLAT_TABLES 6 118 #endif 119 # define N_MPU_REGIONS 16 /* number of MPU regions */ 120 # define ALL_MPU_EL2_REGIONS_USED 0xffffffff 121 /* this is the PRENR_EL2 value if all MPU regions are in use */ 122 123 /* 124 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 125 * plus a little space for growth. 126 */ 127 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 128 129 /* 130 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 131 */ 132 133 #if USE_ROMLIB 134 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 135 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 136 #define FVP_R_BL2_ROMLIB_OPTIMIZATION UL(0x6000) 137 #else 138 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 139 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 140 #define FVP_R_BL2_ROMLIB_OPTIMIZATION UL(0) 141 #endif 142 143 /* 144 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 145 * little space for growth. 146 */ 147 #if TRUSTED_BOARD_BOOT 148 #if COT_DESC_IN_DTB 149 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1E000) - FVP_R_BL2_ROMLIB_OPTIMIZATION) 150 #else 151 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_R_BL2_ROMLIB_OPTIMIZATION) 152 #endif 153 #else 154 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - FVP_R_BL2_ROMLIB_OPTIMIZATION) 155 #endif 156 157 /* 158 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 159 * calculated using the current BL31 PROGBITS debug size plus the sizes of 160 * BL2 and BL1-RW 161 */ 162 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3D000) 163 164 /* 165 * Size of cacheable stacks 166 */ 167 #if defined(IMAGE_BL1) 168 # if TRUSTED_BOARD_BOOT 169 # define PLATFORM_STACK_SIZE UL(0x1000) 170 # else 171 # define PLATFORM_STACK_SIZE UL(0x500) 172 # endif 173 #endif 174 175 #define MAX_IO_DEVICES 3 176 #define MAX_IO_HANDLES 4 177 178 /* 179 * These nominally reserve the last block of flash for PSCI MEM PROTECT flag, 180 * but no PSCI in FVP_R platform, so reserve nothing: 181 */ 182 #define PLAT_ARM_FLASH_IMAGE_BASE (PLAT_ARM_DRAM1_BASE + UL(0x40000000)) 183 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (PLAT_ARM_DRAM1_SIZE - UL(0x40000000)) 184 185 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 186 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 187 188 /* 189 * PL011 related constants 190 */ 191 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 192 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 193 194 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 195 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 196 197 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 198 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 199 200 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 201 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 202 203 /* CCI related constants */ 204 #define PLAT_FVP_R_CCI400_BASE UL(0xac090000) 205 #define PLAT_FVP_R_CCI400_CLUS0_SL_PORT 3 206 #define PLAT_FVP_R_CCI400_CLUS1_SL_PORT 4 207 208 /* CCI-500/CCI-550 on Base platform */ 209 #define PLAT_FVP_R_CCI5XX_BASE UL(0xaa000000) 210 #define PLAT_FVP_R_CCI5XX_CLUS0_SL_PORT 5 211 #define PLAT_FVP_R_CCI5XX_CLUS1_SL_PORT 6 212 213 /* System timer related constants */ 214 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 215 216 /* Mailbox base address */ 217 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 218 219 220 /* TrustZone controller related constants 221 * 222 * Currently only filters 0 and 2 are connected on Base FVP_R. 223 * Filter 0 : CPU clusters (no access to DRAM by default) 224 * Filter 1 : not connected 225 * Filter 2 : LCDs (access to VRAM allowed by default) 226 * Filter 3 : not connected 227 * Programming unconnected filters will have no effect at the 228 * moment. These filter could, however, be connected in future. 229 * So care should be taken not to configure the unused filters. 230 * 231 * Allow only non-secure access to all DRAM to supported devices. 232 * Give access to the CPUs and Virtio. Some devices 233 * would normally use the default ID so allow that too. 234 */ 235 #define PLAT_ARM_TZC_BASE UL(0xaa4a0000) 236 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 237 238 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 239 TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_DEFAULT) | \ 240 TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_PCI) | \ 241 TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_AP) | \ 242 TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_VIRTIO) | \ 243 TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_VIRTIO_OLD)) 244 245 /* 246 * GIC related constants to cater for both GICv2 and GICv3 instances of an 247 * FVP_R. They could be overridden at runtime in case the FVP_R implements the 248 * legacy VE memory map. 249 */ 250 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 251 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 252 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 253 254 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 255 PLAT_SP_IMAGE_NS_BUF_SIZE) 256 257 #define PLAT_SP_PRI PLAT_RAS_PRI 258 259 /* 260 * Physical and virtual address space limits for MPU in AARCH64 & AARCH32 modes 261 */ 262 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 263 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 264 265 #define ARM_SOC_CONTINUATION_SHIFT U(24) 266 #define ARM_SOC_IDENTIFICATION_SHIFT U(16) 267 268 #endif /* FVP_R_PLATFORM_DEF_H */ 269