1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #ifndef PLATFORM_DEF_H 9 #define PLATFORM_DEF_H 10 11 #ifndef __ASSEMBLER__ 12 #include <stdio.h> 13 #endif /* __ASSEMBLER__ */ 14 15 #include <common/interrupt_props.h> 16 #include <drivers/arm/gic_common.h> 17 18 #include <board_marvell_def.h> 19 #include <mvebu_def.h> 20 21 /* 22 * Most platform porting definitions provided by included headers 23 */ 24 25 /* 26 * DRAM Memory layout: 27 * +-----------------------+ 28 * : : 29 * : Linux : 30 * 0x04X00000-->+-----------------------+ 31 * | BL3-3(u-boot) |>>}>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> 32 * |-----------------------| } | 33 * | BL3-[0,1, 2] | }---------------------------------> | 34 * |-----------------------| } || | 35 * | BL2 | }->FIP (loaded by || | 36 * |-----------------------| } BootROM to DRAM) || | 37 * | FIP_TOC | } || | 38 * 0x04120000-->|-----------------------| || | 39 * | BL1 (RO) | || | 40 * 0x04100000-->+-----------------------+ || | 41 * : : || | 42 * : Trusted SRAM section : \/ | 43 * 0x04040000-->+-----------------------+ Replaced by BL2 +----------------+ | 44 * | BL1 (RW) | <<<<<<<<<<<<<<<< | BL3-1 NOBITS | | 45 * 0x04037000-->|-----------------------| <<<<<<<<<<<<<<<< |----------------| | 46 * | | <<<<<<<<<<<<<<<< | BL3-1 PROGBITS | | 47 * 0x04023000-->|-----------------------| +----------------+ | 48 * | BL2 | | 49 * |-----------------------| | 50 * | | | 51 * 0x04001000-->|-----------------------| | 52 * | Shared | | 53 * 0x04000000-->+-----------------------+ | 54 * : : | 55 * : Linux : | 56 * : : | 57 * |-----------------------| | 58 * | | U-Boot(BL3-3) Loaded by BL2 | 59 * | U-Boot | <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< 60 * 0x00000000-->+-----------------------+ 61 * 62 * Trusted SRAM section 0x4000000..0x4200000: 63 * ---------------------------------------- 64 * SRAM_BASE = 0x4001000 65 * BL2_BASE = 0x4006000 66 * BL2_LIMIT = BL31_BASE 67 * BL31_BASE = 0x4023000 = (64MB + 256KB - 0x1D000) 68 * BL31_PROGBITS_LIMIT = BL1_RW_BASE 69 * BL1_RW_BASE = 0x4037000 = (64MB + 256KB - 0x9000) 70 * BL1_RW_LIMIT = BL31_LIMIT = 0x4040000 71 * 72 * 73 * PLAT_MARVELL_FIP_BASE = 0x4120000 74 */ 75 76 #define PLAT_MARVELL_SRAM_BASE 0xFFE1C048 77 #define PLAT_MARVELL_SRAM_END 0xFFE78000 78 79 #define PLAT_MARVELL_ATF_BASE 0x4000000 80 #define PLAT_MARVELL_ATF_LOAD_ADDR (PLAT_MARVELL_ATF_BASE + \ 81 0x100000) 82 83 #define PLAT_MARVELL_FIP_BASE (PLAT_MARVELL_ATF_LOAD_ADDR + \ 84 0x20000) 85 #define PLAT_MARVELL_FIP_MAX_SIZE 0x4000000 86 87 #define PLAT_MARVELL_NORTHB_COUNT 1 88 89 #define PLAT_MARVELL_CLUSTER_COUNT U(2) 90 #define PLAT_MARVELL_CLUSTER_CORE_COUNT U(2) 91 92 #define PLAT_MARVELL_CORE_COUNT (PLAT_MARVELL_CLUSTER_COUNT * \ 93 PLAT_MARVELL_CLUSTER_CORE_COUNT) 94 95 #define PLAT_MAX_CPUS_PER_CLUSTER PLAT_MARVELL_CLUSTER_CORE_COUNT 96 97 /* Part of DRAM that is used as Trusted ROM */ 98 #define PLAT_MARVELL_TRUSTED_ROM_BASE PLAT_MARVELL_ATF_LOAD_ADDR 99 /* 4 MB for FIP image */ 100 #define PLAT_MARVELL_TRUSTED_ROM_SIZE 0x00400000 101 /* Reserve 12MB for SCP (Secure PayLoad) Trusted RAM 102 * OP-TEE 4MB SHMEM follows this region 103 */ 104 #define PLAT_MARVELL_TRUSTED_RAM_BASE 0x04400000 105 #define PLAT_MARVELL_TRUSTED_RAM_SIZE 0x00C00000 /* 12 MB DRAM */ 106 107 #define PLAT_MARVELL_LLC_SRAM_BASE 0x05400000 108 #define PLAT_MARVELL_LLC_SRAM_SIZE 0x00100000 /* 1 MB SRAM */ 109 110 /* 111 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 112 * plus a little space for growth. 113 */ 114 #define PLAT_MARVELL_MAX_BL1_RW_SIZE 0xA000 115 116 /* 117 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 118 * little space for growth. 119 */ 120 #define PLAT_MARVELL_MAX_BL2_SIZE 0xF000 121 122 /* 123 * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a 124 * little space for growth. 125 */ 126 #define PLAT_MARVEL_MAX_BL31_SIZE 0x5D000 127 128 #define PLAT_MARVELL_CPU_ENTRY_ADDR BL1_RO_BASE 129 130 /* GIC related definitions */ 131 #define PLAT_MARVELL_GICD_BASE (MVEBU_REGS_BASE + MVEBU_GICD_BASE) 132 #define PLAT_MARVELL_GICC_BASE (MVEBU_REGS_BASE + MVEBU_GICC_BASE) 133 134 #define PLAT_MARVELL_G0_IRQ_PROPS(grp) \ 135 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 136 GIC_INTR_CFG_LEVEL), \ 137 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 138 GIC_INTR_CFG_LEVEL), \ 139 INTR_PROP_DESC(MARVELL_IRQ_PIC0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 140 GIC_INTR_CFG_LEVEL) 141 142 #define PLAT_MARVELL_G1S_IRQ_PROPS(grp) \ 143 INTR_PROP_DESC(MARVELL_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ 144 grp, GIC_INTR_CFG_LEVEL), \ 145 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 146 GIC_INTR_CFG_LEVEL), \ 147 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 148 GIC_INTR_CFG_LEVEL), \ 149 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 150 GIC_INTR_CFG_LEVEL), \ 151 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 152 GIC_INTR_CFG_LEVEL), \ 153 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 154 GIC_INTR_CFG_LEVEL), \ 155 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 156 GIC_INTR_CFG_LEVEL) 157 158 #define PLAT_MARVELL_SHARED_RAM_CACHED 1 159 160 /* 161 * Load address of BL3-3 for this platform port 162 */ 163 #define PLAT_MARVELL_NS_IMAGE_OFFSET 0x0 164 165 /* System Reference Clock*/ 166 #define PLAT_REF_CLK_IN_HZ COUNTER_FREQUENCY 167 168 /* 169 * PL011 related constants 170 */ 171 #define PLAT_MARVELL_UART_BASE (MVEBU_REGS_BASE + 0x512000) 172 #define PLAT_MARVELL_UART_CLK_IN_HZ 200000000 173 174 /* Recovery image enable */ 175 #define PLAT_RECOVERY_IMAGE_ENABLE 0 176 177 /* Required platform porting definitions */ 178 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 179 180 /* System timer related constants */ 181 #define PLAT_MARVELL_NSTIMER_FRAME_ID 1 182 183 /* Mailbox base address (note the lower memory space 184 * is reserved for BLE data) 185 */ 186 #define PLAT_MARVELL_MAILBOX_BASE (MARVELL_SHARED_RAM_BASE \ 187 + 0x400) 188 #define PLAT_MARVELL_MAILBOX_SIZE 0x100 189 #define PLAT_MARVELL_MAILBOX_MAGIC_NUM 0x6D72766C /* mrvl */ 190 191 /* Securities */ 192 #define IRQ_SEC_OS_TICK_INT MARVELL_IRQ_SEC_PHY_TIMER 193 194 #define MVEBU_PMU_IRQ_WA 195 196 #endif /* PLATFORM_DEF_H */ 197