1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2016, GlobalLogic 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef PLATFORM_CONFIG_H 30 #define PLATFORM_CONFIG_H 31 32 #include <mm/generic_ram_layout.h> 33 34 #define RCAR_CACHE_LINE_SZ 64 35 36 /* Make stacks aligned to data cache line length */ 37 #define STACK_ALIGNMENT RCAR_CACHE_LINE_SZ 38 39 #define GIC_BASE 0xF1000000 40 #define GICC_BASE 0xF1020000 41 #define GICD_BASE 0xF1010000 42 43 #define CONSOLE_UART_BASE 0xE6E88000 44 45 #define PRR_BASE 0xFFF00000 46 47 #if defined(PLATFORM_FLAVOR_salvator_h3) 48 #define NSEC_DDR_0_BASE 0x47E00000 49 #define NSEC_DDR_0_SIZE 0x38200000 50 #define NSEC_DDR_1_BASE 0x500000000U 51 #define NSEC_DDR_1_SIZE 0x40000000 52 #define NSEC_DDR_2_BASE 0x600000000U 53 #define NSEC_DDR_2_SIZE 0x40000000 54 #define NSEC_DDR_3_BASE 0x700000000U 55 #define NSEC_DDR_3_SIZE 0x40000000 56 57 #elif defined(PLATFORM_FLAVOR_salvator_h3_4x2g) 58 #define NSEC_DDR_0_BASE 0x47E00000 59 #define NSEC_DDR_0_SIZE 0x78200000 60 #define NSEC_DDR_1_BASE 0x500000000U 61 #define NSEC_DDR_1_SIZE 0x80000000 62 #define NSEC_DDR_2_BASE 0x600000000U 63 #define NSEC_DDR_2_SIZE 0x80000000 64 #define NSEC_DDR_3_BASE 0x700000000U 65 #define NSEC_DDR_3_SIZE 0x80000000 66 67 #elif defined(PLATFORM_FLAVOR_salvator_m3) 68 #define NSEC_DDR_0_BASE 0x47E00000 69 #define NSEC_DDR_0_SIZE 0x78200000 70 #define NSEC_DDR_1_BASE 0x600000000U 71 #define NSEC_DDR_1_SIZE 0x80000000 72 73 #elif defined(PLATFORM_FLAVOR_salvator_m3_2x4g) 74 #define NSEC_DDR_0_BASE 0x47E00000 75 #define NSEC_DDR_0_SIZE 0x78200000 76 #define NSEC_DDR_1_BASE 0x480000000U 77 #define NSEC_DDR_1_SIZE 0x80000000 78 #define NSEC_DDR_2_BASE 0x600000000U 79 #define NSEC_DDR_2_SIZE 0x100000000U 80 81 #else 82 83 /* Generic DT-based platform */ 84 85 #endif 86 87 /* Full GlobalPlatform test suite requires TEE_SHMEM_SIZE to be at least 2MB */ 88 #define TEE_SHMEM_START (TZDRAM_BASE + TZDRAM_SIZE) 89 #define TEE_SHMEM_SIZE 0x100000 90 91 #endif /*PLATFORM_CONFIG_H*/ 92