1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2017 Intel Corporation. 4 * Take from coreboot project file of the same name 5 */ 6 7 #ifndef _ASM_ARCH_SYSTEMAGENT_H 8 #define _ASM_ARCH_SYSTEMAGENT_H 9 10 /* Device 0:0.0 PCI configuration space */ 11 #include <linux/bitops.h> 12 13 struct udevice; 14 15 #define MCHBAR 0x48 16 17 /* RAPL Package Power Limit register under MCHBAR */ 18 #define PUNIT_THERMAL_DEVICE_IRQ 0x700C 19 #define PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER 0x18 20 #define PUINT_THERMAL_DEVICE_IRQ_LOCK 0x80000000 21 #define BIOS_RESET_CPL 0x7078 22 #define PCODE_INIT_DONE BIT(8) 23 #define MCHBAR_RAPL_PPL 0x70A8 24 #define CORE_DISABLE_MASK 0x7168 25 #define CAPID0_A 0xE4 26 #define VTD_DISABLE BIT(23) 27 #define DEFVTBAR 0x6c80 28 #define GFXVTBAR 0x6c88 29 #define VTBAR_ENABLED 0x01 30 #define VTBAR_MASK GENMASK_ULL(39, 12) 31 #define VTBAR_SIZE 0x1000 32 33 /** 34 * enable_bios_reset_cpl() - Tell the system agent that memory/power are ready 35 * 36 * This should be called when U-Boot has set up the memory and power 37 * management. 38 */ 39 void enable_bios_reset_cpl(void); 40 41 /** 42 * sa_get_tolud_base() - Get the TOLUD base address 43 * 44 * This returns the Top Of Low Useable DRAM, marking the top of usable DRAM 45 * below 4GB 46 * 47 * @dev: hostbridge device 48 * @return TOLUD address 49 */ 50 ulong sa_get_tolud_base(struct udevice *dev); 51 52 /** 53 * sa_get_gsm_base() - Get the GSM base address 54 * 55 * This returns the base of GTT Stolen Memory, marking the start of memory used 56 * for Graphics Translation Tables. 57 * 58 * @dev: hostbridge device 59 * @return GSM address 60 */ 61 ulong sa_get_gsm_base(struct udevice *dev); 62 63 /** 64 * sa_get_tseg_base() - Get the TSEG base address 65 * 66 * This returns the top address of DRAM available below 4GB 67 * 68 * @return TSEG base 69 */ 70 ulong sa_get_tseg_base(struct udevice *dev); 71 72 #endif 73