1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
4  *
5  * Authors: 	Shlomi Gridish <gridish@freescale.com>
6  * 		Li Yang <leoli@freescale.com>
7  *
8  * Description:
9  * QUICC Engine (QE) external definitions and structure.
10  */
11 #ifndef _ASM_POWERPC_QE_H
12 #define _ASM_POWERPC_QE_H
13 #ifdef __KERNEL__
14 
15 #include <linux/compiler.h>
16 #include <linux/genalloc.h>
17 #include <linux/spinlock.h>
18 #include <linux/errno.h>
19 #include <linux/err.h>
20 #include <soc/fsl/cpm.h>
21 #include <soc/fsl/qe/immap_qe.h>
22 #include <linux/of.h>
23 #include <linux/of_address.h>
24 #include <linux/types.h>
25 
26 #define QE_NUM_OF_SNUM	256	/* There are 256 serial number in QE */
27 #define QE_NUM_OF_BRGS	16
28 #define QE_NUM_OF_PORTS	1024
29 
30 /* Clocks and BRGs */
31 enum qe_clock {
32 	QE_CLK_NONE = 0,
33 	QE_BRG1,		/* Baud Rate Generator 1 */
34 	QE_BRG2,		/* Baud Rate Generator 2 */
35 	QE_BRG3,		/* Baud Rate Generator 3 */
36 	QE_BRG4,		/* Baud Rate Generator 4 */
37 	QE_BRG5,		/* Baud Rate Generator 5 */
38 	QE_BRG6,		/* Baud Rate Generator 6 */
39 	QE_BRG7,		/* Baud Rate Generator 7 */
40 	QE_BRG8,		/* Baud Rate Generator 8 */
41 	QE_BRG9,		/* Baud Rate Generator 9 */
42 	QE_BRG10,		/* Baud Rate Generator 10 */
43 	QE_BRG11,		/* Baud Rate Generator 11 */
44 	QE_BRG12,		/* Baud Rate Generator 12 */
45 	QE_BRG13,		/* Baud Rate Generator 13 */
46 	QE_BRG14,		/* Baud Rate Generator 14 */
47 	QE_BRG15,		/* Baud Rate Generator 15 */
48 	QE_BRG16,		/* Baud Rate Generator 16 */
49 	QE_CLK1,		/* Clock 1 */
50 	QE_CLK2,		/* Clock 2 */
51 	QE_CLK3,		/* Clock 3 */
52 	QE_CLK4,		/* Clock 4 */
53 	QE_CLK5,		/* Clock 5 */
54 	QE_CLK6,		/* Clock 6 */
55 	QE_CLK7,		/* Clock 7 */
56 	QE_CLK8,		/* Clock 8 */
57 	QE_CLK9,		/* Clock 9 */
58 	QE_CLK10,		/* Clock 10 */
59 	QE_CLK11,		/* Clock 11 */
60 	QE_CLK12,		/* Clock 12 */
61 	QE_CLK13,		/* Clock 13 */
62 	QE_CLK14,		/* Clock 14 */
63 	QE_CLK15,		/* Clock 15 */
64 	QE_CLK16,		/* Clock 16 */
65 	QE_CLK17,		/* Clock 17 */
66 	QE_CLK18,		/* Clock 18 */
67 	QE_CLK19,		/* Clock 19 */
68 	QE_CLK20,		/* Clock 20 */
69 	QE_CLK21,		/* Clock 21 */
70 	QE_CLK22,		/* Clock 22 */
71 	QE_CLK23,		/* Clock 23 */
72 	QE_CLK24,		/* Clock 24 */
73 	QE_RSYNC_PIN,		/* RSYNC from pin */
74 	QE_TSYNC_PIN,		/* TSYNC from pin */
75 	QE_CLK_DUMMY
76 };
77 
qe_clock_is_brg(enum qe_clock clk)78 static inline bool qe_clock_is_brg(enum qe_clock clk)
79 {
80 	return clk >= QE_BRG1 && clk <= QE_BRG16;
81 }
82 
83 extern spinlock_t cmxgcr_lock;
84 
85 /* Export QE common operations */
86 #ifdef CONFIG_QUICC_ENGINE
87 extern void qe_reset(void);
88 #else
qe_reset(void)89 static inline void qe_reset(void) {}
90 #endif
91 
92 int cpm_muram_init(void);
93 
94 #if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE)
95 s32 cpm_muram_alloc(unsigned long size, unsigned long align);
96 void cpm_muram_free(s32 offset);
97 s32 cpm_muram_alloc_fixed(unsigned long offset, unsigned long size);
98 void __iomem *cpm_muram_addr(unsigned long offset);
99 unsigned long cpm_muram_offset(const void __iomem *addr);
100 dma_addr_t cpm_muram_dma(void __iomem *addr);
101 void cpm_muram_free_addr(const void __iomem *addr);
102 #else
cpm_muram_alloc(unsigned long size,unsigned long align)103 static inline s32 cpm_muram_alloc(unsigned long size,
104 				  unsigned long align)
105 {
106 	return -ENOSYS;
107 }
108 
cpm_muram_free(s32 offset)109 static inline void cpm_muram_free(s32 offset)
110 {
111 }
112 
cpm_muram_alloc_fixed(unsigned long offset,unsigned long size)113 static inline s32 cpm_muram_alloc_fixed(unsigned long offset,
114 					unsigned long size)
115 {
116 	return -ENOSYS;
117 }
118 
cpm_muram_addr(unsigned long offset)119 static inline void __iomem *cpm_muram_addr(unsigned long offset)
120 {
121 	return NULL;
122 }
123 
cpm_muram_offset(const void __iomem * addr)124 static inline unsigned long cpm_muram_offset(const void __iomem *addr)
125 {
126 	return -ENOSYS;
127 }
128 
cpm_muram_dma(void __iomem * addr)129 static inline dma_addr_t cpm_muram_dma(void __iomem *addr)
130 {
131 	return 0;
132 }
cpm_muram_free_addr(const void __iomem * addr)133 static inline void cpm_muram_free_addr(const void __iomem *addr)
134 {
135 }
136 #endif /* defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) */
137 
138 /* QE PIO */
139 #define QE_PIO_PINS 32
140 
141 struct qe_pio_regs {
142 	__be32	cpodr;		/* Open drain register */
143 	__be32	cpdata;		/* Data register */
144 	__be32	cpdir1;		/* Direction register */
145 	__be32	cpdir2;		/* Direction register */
146 	__be32	cppar1;		/* Pin assignment register */
147 	__be32	cppar2;		/* Pin assignment register */
148 #ifdef CONFIG_PPC_85xx
149 	u8	pad[8];
150 #endif
151 };
152 
153 #define QE_PIO_DIR_IN	2
154 #define QE_PIO_DIR_OUT	1
155 extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin,
156 				int dir, int open_drain, int assignment,
157 				int has_irq);
158 #ifdef CONFIG_QUICC_ENGINE
159 extern int par_io_init(struct device_node *np);
160 extern int par_io_of_config(struct device_node *np);
161 extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
162 			     int assignment, int has_irq);
163 extern int par_io_data_set(u8 port, u8 pin, u8 val);
164 #else
par_io_init(struct device_node * np)165 static inline int par_io_init(struct device_node *np) { return -ENOSYS; }
par_io_of_config(struct device_node * np)166 static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; }
par_io_config_pin(u8 port,u8 pin,int dir,int open_drain,int assignment,int has_irq)167 static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
168 		int assignment, int has_irq) { return -ENOSYS; }
par_io_data_set(u8 port,u8 pin,u8 val)169 static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; }
170 #endif /* CONFIG_QUICC_ENGINE */
171 
172 /*
173  * Pin multiplexing functions.
174  */
175 struct qe_pin;
176 #ifdef CONFIG_QE_GPIO
177 extern struct qe_pin *qe_pin_request(struct device_node *np, int index);
178 extern void qe_pin_free(struct qe_pin *qe_pin);
179 extern void qe_pin_set_gpio(struct qe_pin *qe_pin);
180 extern void qe_pin_set_dedicated(struct qe_pin *pin);
181 #else
qe_pin_request(struct device_node * np,int index)182 static inline struct qe_pin *qe_pin_request(struct device_node *np, int index)
183 {
184 	return ERR_PTR(-ENOSYS);
185 }
qe_pin_free(struct qe_pin * qe_pin)186 static inline void qe_pin_free(struct qe_pin *qe_pin) {}
qe_pin_set_gpio(struct qe_pin * qe_pin)187 static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {}
qe_pin_set_dedicated(struct qe_pin * pin)188 static inline void qe_pin_set_dedicated(struct qe_pin *pin) {}
189 #endif /* CONFIG_QE_GPIO */
190 
191 #ifdef CONFIG_QUICC_ENGINE
192 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
193 #else
qe_issue_cmd(u32 cmd,u32 device,u8 mcn_protocol,u32 cmd_input)194 static inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol,
195 			       u32 cmd_input)
196 {
197 	return -ENOSYS;
198 }
199 #endif /* CONFIG_QUICC_ENGINE */
200 
201 /* QE internal API */
202 enum qe_clock qe_clock_source(const char *source);
203 unsigned int qe_get_brg_clk(void);
204 int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
205 int qe_get_snum(void);
206 void qe_put_snum(u8 snum);
207 unsigned int qe_get_num_of_risc(void);
208 unsigned int qe_get_num_of_snums(void);
209 
qe_alive_during_sleep(void)210 static inline int qe_alive_during_sleep(void)
211 {
212 	/*
213 	 * MPC8568E reference manual says:
214 	 *
215 	 * "...power down sequence waits for all I/O interfaces to become idle.
216 	 *  In some applications this may happen eventually without actively
217 	 *  shutting down interfaces, but most likely, software will have to
218 	 *  take steps to shut down the eTSEC, QUICC Engine Block, and PCI
219 	 *  interfaces before issuing the command (either the write to the core
220 	 *  MSR[WE] as described above or writing to POWMGTCSR) to put the
221 	 *  device into sleep state."
222 	 *
223 	 * MPC8569E reference manual has a similar paragraph.
224 	 */
225 #ifdef CONFIG_PPC_85xx
226 	return 0;
227 #else
228 	return 1;
229 #endif
230 }
231 
232 /* we actually use cpm_muram implementation, define this for convenience */
233 #define qe_muram_init cpm_muram_init
234 #define qe_muram_alloc cpm_muram_alloc
235 #define qe_muram_alloc_fixed cpm_muram_alloc_fixed
236 #define qe_muram_free cpm_muram_free
237 #define qe_muram_addr cpm_muram_addr
238 #define qe_muram_offset cpm_muram_offset
239 #define qe_muram_dma cpm_muram_dma
240 #define qe_muram_free_addr cpm_muram_free_addr
241 
242 #define qe_setbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) |  (_v), (_addr))
243 #define qe_clrbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
244 
245 #define qe_setbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) |  (_v), (_addr))
246 #define qe_clrbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
247 
248 #define qe_setbits_8(_addr, _v) iowrite8(ioread8(_addr) |  (_v), (_addr))
249 #define qe_clrbits_8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
250 
251 #define qe_clrsetbits_be32(addr, clear, set) \
252 	iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
253 #define qe_clrsetbits_be16(addr, clear, set) \
254 	iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
255 #define qe_clrsetbits_8(addr, clear, set) \
256 	iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
257 
258 /* Structure that defines QE firmware binary files.
259  *
260  * See Documentation/powerpc/qe_firmware.rst for a description of these
261  * fields.
262  */
263 struct qe_firmware {
264 	struct qe_header {
265 		__be32 length;  /* Length of the entire structure, in bytes */
266 		u8 magic[3];    /* Set to { 'Q', 'E', 'F' } */
267 		u8 version;     /* Version of this layout. First ver is '1' */
268 	} header;
269 	u8 id[62];      /* Null-terminated identifier string */
270 	u8 split;	/* 0 = shared I-RAM, 1 = split I-RAM */
271 	u8 count;       /* Number of microcode[] structures */
272 	struct {
273 		__be16 model;   	/* The SOC model  */
274 		u8 major;       	/* The SOC revision major */
275 		u8 minor;       	/* The SOC revision minor */
276 	} __attribute__ ((packed)) soc;
277 	u8 padding[4];			/* Reserved, for alignment */
278 	__be64 extended_modes;		/* Extended modes */
279 	__be32 vtraps[8];		/* Virtual trap addresses */
280 	u8 reserved[4];			/* Reserved, for future expansion */
281 	struct qe_microcode {
282 		u8 id[32];      	/* Null-terminated identifier */
283 		__be32 traps[16];       /* Trap addresses, 0 == ignore */
284 		__be32 eccr;    	/* The value for the ECCR register */
285 		__be32 iram_offset;     /* Offset into I-RAM for the code */
286 		__be32 count;   	/* Number of 32-bit words of the code */
287 		__be32 code_offset;     /* Offset of the actual microcode */
288 		u8 major;       	/* The microcode version major */
289 		u8 minor;       	/* The microcode version minor */
290 		u8 revision;		/* The microcode version revision */
291 		u8 padding;		/* Reserved, for alignment */
292 		u8 reserved[4];		/* Reserved, for future expansion */
293 	} __packed microcode[];
294 	/* All microcode binaries should be located here */
295 	/* CRC32 should be located here, after the microcode binaries */
296 } __attribute__ ((packed));
297 
298 struct qe_firmware_info {
299 	char id[64];		/* Firmware name */
300 	u32 vtraps[8];		/* Virtual trap addresses */
301 	u64 extended_modes;	/* Extended modes */
302 };
303 
304 #ifdef CONFIG_QUICC_ENGINE
305 /* Upload a firmware to the QE */
306 int qe_upload_firmware(const struct qe_firmware *firmware);
307 #else
qe_upload_firmware(const struct qe_firmware * firmware)308 static inline int qe_upload_firmware(const struct qe_firmware *firmware)
309 {
310 	return -ENOSYS;
311 }
312 #endif /* CONFIG_QUICC_ENGINE */
313 
314 /* Obtain information on the uploaded firmware */
315 struct qe_firmware_info *qe_get_firmware_info(void);
316 
317 /* QE USB */
318 int qe_usb_clock_set(enum qe_clock clk, int rate);
319 
320 /* Buffer descriptors */
321 struct qe_bd {
322 	__be16 status;
323 	__be16 length;
324 	__be32 buf;
325 } __attribute__ ((packed));
326 
327 #define BD_STATUS_MASK	0xffff0000
328 #define BD_LENGTH_MASK	0x0000ffff
329 
330 /* Alignment */
331 #define QE_INTR_TABLE_ALIGN	16	/* ??? */
332 #define QE_ALIGNMENT_OF_BD	8
333 #define QE_ALIGNMENT_OF_PRAM	64
334 
335 /* RISC allocation */
336 #define QE_RISC_ALLOCATION_RISC1	0x1  /* RISC 1 */
337 #define QE_RISC_ALLOCATION_RISC2	0x2  /* RISC 2 */
338 #define QE_RISC_ALLOCATION_RISC3	0x4  /* RISC 3 */
339 #define QE_RISC_ALLOCATION_RISC4	0x8  /* RISC 4 */
340 #define QE_RISC_ALLOCATION_RISC1_AND_RISC2	(QE_RISC_ALLOCATION_RISC1 | \
341 						 QE_RISC_ALLOCATION_RISC2)
342 #define QE_RISC_ALLOCATION_FOUR_RISCS	(QE_RISC_ALLOCATION_RISC1 | \
343 					 QE_RISC_ALLOCATION_RISC2 | \
344 					 QE_RISC_ALLOCATION_RISC3 | \
345 					 QE_RISC_ALLOCATION_RISC4)
346 
347 /* QE extended filtering Table Lookup Key Size */
348 enum qe_fltr_tbl_lookup_key_size {
349 	QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
350 		= 0x3f,		/* LookupKey parsed by the Generate LookupKey
351 				   CMD is truncated to 8 bytes */
352 	QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
353 		= 0x5f,		/* LookupKey parsed by the Generate LookupKey
354 				   CMD is truncated to 16 bytes */
355 };
356 
357 /* QE FLTR extended filtering Largest External Table Lookup Key Size */
358 enum qe_fltr_largest_external_tbl_lookup_key_size {
359 	QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
360 		= 0x0,/* not used */
361 	QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
362 		= QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES,	/* 8 bytes */
363 	QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
364 		= QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES,	/* 16 bytes */
365 };
366 
367 /* structure representing QE parameter RAM */
368 struct qe_timer_tables {
369 	u16 tm_base;		/* QE timer table base adr */
370 	u16 tm_ptr;		/* QE timer table pointer */
371 	u16 r_tmr;		/* QE timer mode register */
372 	u16 r_tmv;		/* QE timer valid register */
373 	u32 tm_cmd;		/* QE timer cmd register */
374 	u32 tm_cnt;		/* QE timer internal cnt */
375 } __attribute__ ((packed));
376 
377 #define QE_FLTR_TAD_SIZE	8
378 
379 /* QE extended filtering Termination Action Descriptor (TAD) */
380 struct qe_fltr_tad {
381 	u8 serialized[QE_FLTR_TAD_SIZE];
382 } __attribute__ ((packed));
383 
384 /* Communication Direction */
385 enum comm_dir {
386 	COMM_DIR_NONE = 0,
387 	COMM_DIR_RX = 1,
388 	COMM_DIR_TX = 2,
389 	COMM_DIR_RX_AND_TX = 3
390 };
391 
392 /* QE CMXUCR Registers.
393  * There are two UCCs represented in each of the four CMXUCR registers.
394  * These values are for the UCC in the LSBs
395  */
396 #define QE_CMXUCR_MII_ENET_MNG		0x00007000
397 #define QE_CMXUCR_MII_ENET_MNG_SHIFT	12
398 #define QE_CMXUCR_GRANT			0x00008000
399 #define QE_CMXUCR_TSA			0x00004000
400 #define QE_CMXUCR_BKPT			0x00000100
401 #define QE_CMXUCR_TX_CLK_SRC_MASK	0x0000000F
402 
403 /* QE CMXGCR Registers.
404 */
405 #define QE_CMXGCR_MII_ENET_MNG		0x00007000
406 #define QE_CMXGCR_MII_ENET_MNG_SHIFT	12
407 #define QE_CMXGCR_USBCS			0x0000000f
408 #define QE_CMXGCR_USBCS_CLK3		0x1
409 #define QE_CMXGCR_USBCS_CLK5		0x2
410 #define QE_CMXGCR_USBCS_CLK7		0x3
411 #define QE_CMXGCR_USBCS_CLK9		0x4
412 #define QE_CMXGCR_USBCS_CLK13		0x5
413 #define QE_CMXGCR_USBCS_CLK17		0x6
414 #define QE_CMXGCR_USBCS_CLK19		0x7
415 #define QE_CMXGCR_USBCS_CLK21		0x8
416 #define QE_CMXGCR_USBCS_BRG9		0x9
417 #define QE_CMXGCR_USBCS_BRG10		0xa
418 
419 /* QE CECR Commands.
420 */
421 #define QE_CR_FLG			0x00010000
422 #define QE_RESET			0x80000000
423 #define QE_INIT_TX_RX			0x00000000
424 #define QE_INIT_RX			0x00000001
425 #define QE_INIT_TX			0x00000002
426 #define QE_ENTER_HUNT_MODE		0x00000003
427 #define QE_STOP_TX			0x00000004
428 #define QE_GRACEFUL_STOP_TX		0x00000005
429 #define QE_RESTART_TX			0x00000006
430 #define QE_CLOSE_RX_BD			0x00000007
431 #define QE_SWITCH_COMMAND		0x00000007
432 #define QE_SET_GROUP_ADDRESS		0x00000008
433 #define QE_START_IDMA			0x00000009
434 #define QE_MCC_STOP_RX			0x00000009
435 #define QE_ATM_TRANSMIT			0x0000000a
436 #define QE_HPAC_CLEAR_ALL		0x0000000b
437 #define QE_GRACEFUL_STOP_RX		0x0000001a
438 #define QE_RESTART_RX			0x0000001b
439 #define QE_HPAC_SET_PRIORITY		0x0000010b
440 #define QE_HPAC_STOP_TX			0x0000020b
441 #define QE_HPAC_STOP_RX			0x0000030b
442 #define QE_HPAC_GRACEFUL_STOP_TX	0x0000040b
443 #define QE_HPAC_GRACEFUL_STOP_RX	0x0000050b
444 #define QE_HPAC_START_TX		0x0000060b
445 #define QE_HPAC_START_RX		0x0000070b
446 #define QE_USB_STOP_TX			0x0000000a
447 #define QE_USB_RESTART_TX		0x0000000c
448 #define QE_QMC_STOP_TX			0x0000000c
449 #define QE_QMC_STOP_RX			0x0000000d
450 #define QE_SS7_SU_FIL_RESET		0x0000000e
451 /* jonathbr added from here down for 83xx */
452 #define QE_RESET_BCS			0x0000000a
453 #define QE_MCC_INIT_TX_RX_16		0x00000003
454 #define QE_MCC_STOP_TX			0x00000004
455 #define QE_MCC_INIT_TX_1		0x00000005
456 #define QE_MCC_INIT_RX_1		0x00000006
457 #define QE_MCC_RESET			0x00000007
458 #define QE_SET_TIMER			0x00000008
459 #define QE_RANDOM_NUMBER		0x0000000c
460 #define QE_ATM_MULTI_THREAD_INIT	0x00000011
461 #define QE_ASSIGN_PAGE			0x00000012
462 #define QE_ADD_REMOVE_HASH_ENTRY	0x00000013
463 #define QE_START_FLOW_CONTROL		0x00000014
464 #define QE_STOP_FLOW_CONTROL		0x00000015
465 #define QE_ASSIGN_PAGE_TO_DEVICE	0x00000016
466 
467 #define QE_ASSIGN_RISC			0x00000010
468 #define QE_CR_MCN_NORMAL_SHIFT		6
469 #define QE_CR_MCN_USB_SHIFT		4
470 #define QE_CR_MCN_RISC_ASSIGN_SHIFT	8
471 #define QE_CR_SNUM_SHIFT		17
472 
473 /* QE CECR Sub Block - sub block of QE command.
474 */
475 #define QE_CR_SUBBLOCK_INVALID		0x00000000
476 #define QE_CR_SUBBLOCK_USB		0x03200000
477 #define QE_CR_SUBBLOCK_UCCFAST1		0x02000000
478 #define QE_CR_SUBBLOCK_UCCFAST2		0x02200000
479 #define QE_CR_SUBBLOCK_UCCFAST3		0x02400000
480 #define QE_CR_SUBBLOCK_UCCFAST4		0x02600000
481 #define QE_CR_SUBBLOCK_UCCFAST5		0x02800000
482 #define QE_CR_SUBBLOCK_UCCFAST6		0x02a00000
483 #define QE_CR_SUBBLOCK_UCCFAST7		0x02c00000
484 #define QE_CR_SUBBLOCK_UCCFAST8		0x02e00000
485 #define QE_CR_SUBBLOCK_UCCSLOW1		0x00000000
486 #define QE_CR_SUBBLOCK_UCCSLOW2		0x00200000
487 #define QE_CR_SUBBLOCK_UCCSLOW3		0x00400000
488 #define QE_CR_SUBBLOCK_UCCSLOW4		0x00600000
489 #define QE_CR_SUBBLOCK_UCCSLOW5		0x00800000
490 #define QE_CR_SUBBLOCK_UCCSLOW6		0x00a00000
491 #define QE_CR_SUBBLOCK_UCCSLOW7		0x00c00000
492 #define QE_CR_SUBBLOCK_UCCSLOW8		0x00e00000
493 #define QE_CR_SUBBLOCK_MCC1		0x03800000
494 #define QE_CR_SUBBLOCK_MCC2		0x03a00000
495 #define QE_CR_SUBBLOCK_MCC3		0x03000000
496 #define QE_CR_SUBBLOCK_IDMA1		0x02800000
497 #define QE_CR_SUBBLOCK_IDMA2		0x02a00000
498 #define QE_CR_SUBBLOCK_IDMA3		0x02c00000
499 #define QE_CR_SUBBLOCK_IDMA4		0x02e00000
500 #define QE_CR_SUBBLOCK_HPAC		0x01e00000
501 #define QE_CR_SUBBLOCK_SPI1		0x01400000
502 #define QE_CR_SUBBLOCK_SPI2		0x01600000
503 #define QE_CR_SUBBLOCK_RAND		0x01c00000
504 #define QE_CR_SUBBLOCK_TIMER		0x01e00000
505 #define QE_CR_SUBBLOCK_GENERAL		0x03c00000
506 
507 /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
508 #define QE_CR_PROTOCOL_UNSPECIFIED	0x00	/* For all other protocols */
509 #define QE_CR_PROTOCOL_HDLC_TRANSPARENT	0x00
510 #define QE_CR_PROTOCOL_QMC		0x02
511 #define QE_CR_PROTOCOL_UART		0x04
512 #define QE_CR_PROTOCOL_ATM_POS		0x0A
513 #define QE_CR_PROTOCOL_ETHERNET		0x0C
514 #define QE_CR_PROTOCOL_L2_SWITCH	0x0D
515 
516 /* BRG configuration register */
517 #define QE_BRGC_ENABLE		0x00010000
518 #define QE_BRGC_DIVISOR_SHIFT	1
519 #define QE_BRGC_DIVISOR_MAX	0xFFF
520 #define QE_BRGC_DIV16		1
521 
522 /* QE Timers registers */
523 #define QE_GTCFR1_PCAS	0x80
524 #define QE_GTCFR1_STP2	0x20
525 #define QE_GTCFR1_RST2	0x10
526 #define QE_GTCFR1_GM2	0x08
527 #define QE_GTCFR1_GM1	0x04
528 #define QE_GTCFR1_STP1	0x02
529 #define QE_GTCFR1_RST1	0x01
530 
531 /* SDMA registers */
532 #define QE_SDSR_BER1	0x02000000
533 #define QE_SDSR_BER2	0x01000000
534 
535 #define QE_SDMR_GLB_1_MSK	0x80000000
536 #define QE_SDMR_ADR_SEL		0x20000000
537 #define QE_SDMR_BER1_MSK	0x02000000
538 #define QE_SDMR_BER2_MSK	0x01000000
539 #define QE_SDMR_EB1_MSK		0x00800000
540 #define QE_SDMR_ER1_MSK		0x00080000
541 #define QE_SDMR_ER2_MSK		0x00040000
542 #define QE_SDMR_CEN_MASK	0x0000E000
543 #define QE_SDMR_SBER_1		0x00000200
544 #define QE_SDMR_SBER_2		0x00000200
545 #define QE_SDMR_EB1_PR_MASK	0x000000C0
546 #define QE_SDMR_ER1_PR		0x00000008
547 
548 #define QE_SDMR_CEN_SHIFT	13
549 #define QE_SDMR_EB1_PR_SHIFT	6
550 
551 #define QE_SDTM_MSNUM_SHIFT	24
552 
553 #define QE_SDEBCR_BA_MASK	0x01FFFFFF
554 
555 /* Communication Processor */
556 #define QE_CP_CERCR_MEE		0x8000	/* Multi-user RAM ECC enable */
557 #define QE_CP_CERCR_IEE		0x4000	/* Instruction RAM ECC enable */
558 #define QE_CP_CERCR_CIR		0x0800	/* Common instruction RAM */
559 
560 /* I-RAM */
561 #define QE_IRAM_IADD_AIE	0x80000000	/* Auto Increment Enable */
562 #define QE_IRAM_IADD_BADDR	0x00080000	/* Base Address */
563 #define QE_IRAM_READY           0x80000000      /* Ready */
564 
565 /* UPC */
566 #define UPGCR_PROTOCOL	0x80000000	/* protocol ul2 or pl2 */
567 #define UPGCR_TMS	0x40000000	/* Transmit master/slave mode */
568 #define UPGCR_RMS	0x20000000	/* Receive master/slave mode */
569 #define UPGCR_ADDR	0x10000000	/* Master MPHY Addr multiplexing */
570 #define UPGCR_DIAG	0x01000000	/* Diagnostic mode */
571 
572 /* UCC GUEMR register */
573 #define UCC_GUEMR_MODE_MASK_RX	0x02
574 #define UCC_GUEMR_MODE_FAST_RX	0x02
575 #define UCC_GUEMR_MODE_SLOW_RX	0x00
576 #define UCC_GUEMR_MODE_MASK_TX	0x01
577 #define UCC_GUEMR_MODE_FAST_TX	0x01
578 #define UCC_GUEMR_MODE_SLOW_TX	0x00
579 #define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
580 #define UCC_GUEMR_SET_RESERVED3	0x10	/* Bit 3 in the guemr is reserved but
581 					   must be set 1 */
582 
583 /* structure representing UCC SLOW parameter RAM */
584 struct ucc_slow_pram {
585 	__be16 rbase;		/* RX BD base address */
586 	__be16 tbase;		/* TX BD base address */
587 	u8 rbmr;		/* RX bus mode register (same as CPM's RFCR) */
588 	u8 tbmr;		/* TX bus mode register (same as CPM's TFCR) */
589 	__be16 mrblr;		/* Rx buffer length */
590 	__be32 rstate;		/* Rx internal state */
591 	__be32 rptr;		/* Rx internal data pointer */
592 	__be16 rbptr;		/* rb BD Pointer */
593 	__be16 rcount;		/* Rx internal byte count */
594 	__be32 rtemp;		/* Rx temp */
595 	__be32 tstate;		/* Tx internal state */
596 	__be32 tptr;		/* Tx internal data pointer */
597 	__be16 tbptr;		/* Tx BD pointer */
598 	__be16 tcount;		/* Tx byte count */
599 	__be32 ttemp;		/* Tx temp */
600 	__be32 rcrc;		/* temp receive CRC */
601 	__be32 tcrc;		/* temp transmit CRC */
602 } __attribute__ ((packed));
603 
604 /* General UCC SLOW Mode Register (GUMRH & GUMRL) */
605 #define UCC_SLOW_GUMR_H_SAM_QMC		0x00000000
606 #define UCC_SLOW_GUMR_H_SAM_SATM	0x00008000
607 #define UCC_SLOW_GUMR_H_REVD		0x00002000
608 #define UCC_SLOW_GUMR_H_TRX		0x00001000
609 #define UCC_SLOW_GUMR_H_TTX		0x00000800
610 #define UCC_SLOW_GUMR_H_CDP		0x00000400
611 #define UCC_SLOW_GUMR_H_CTSP		0x00000200
612 #define UCC_SLOW_GUMR_H_CDS		0x00000100
613 #define UCC_SLOW_GUMR_H_CTSS		0x00000080
614 #define UCC_SLOW_GUMR_H_TFL		0x00000040
615 #define UCC_SLOW_GUMR_H_RFW		0x00000020
616 #define UCC_SLOW_GUMR_H_TXSY		0x00000010
617 #define UCC_SLOW_GUMR_H_4SYNC		0x00000004
618 #define UCC_SLOW_GUMR_H_8SYNC		0x00000008
619 #define UCC_SLOW_GUMR_H_16SYNC		0x0000000c
620 #define UCC_SLOW_GUMR_H_RTSM		0x00000002
621 #define UCC_SLOW_GUMR_H_RSYN		0x00000001
622 
623 #define UCC_SLOW_GUMR_L_TCI		0x10000000
624 #define UCC_SLOW_GUMR_L_RINV		0x02000000
625 #define UCC_SLOW_GUMR_L_TINV		0x01000000
626 #define UCC_SLOW_GUMR_L_TEND		0x00040000
627 #define UCC_SLOW_GUMR_L_TDCR_MASK	0x00030000
628 #define UCC_SLOW_GUMR_L_TDCR_32	        0x00030000
629 #define UCC_SLOW_GUMR_L_TDCR_16	        0x00020000
630 #define UCC_SLOW_GUMR_L_TDCR_8	        0x00010000
631 #define UCC_SLOW_GUMR_L_TDCR_1	        0x00000000
632 #define UCC_SLOW_GUMR_L_RDCR_MASK	0x0000c000
633 #define UCC_SLOW_GUMR_L_RDCR_32		0x0000c000
634 #define UCC_SLOW_GUMR_L_RDCR_16	        0x00008000
635 #define UCC_SLOW_GUMR_L_RDCR_8	        0x00004000
636 #define UCC_SLOW_GUMR_L_RDCR_1		0x00000000
637 #define UCC_SLOW_GUMR_L_RENC_NRZI	0x00000800
638 #define UCC_SLOW_GUMR_L_RENC_NRZ	0x00000000
639 #define UCC_SLOW_GUMR_L_TENC_NRZI	0x00000100
640 #define UCC_SLOW_GUMR_L_TENC_NRZ	0x00000000
641 #define UCC_SLOW_GUMR_L_DIAG_MASK	0x000000c0
642 #define UCC_SLOW_GUMR_L_DIAG_LE	        0x000000c0
643 #define UCC_SLOW_GUMR_L_DIAG_ECHO	0x00000080
644 #define UCC_SLOW_GUMR_L_DIAG_LOOP	0x00000040
645 #define UCC_SLOW_GUMR_L_DIAG_NORM	0x00000000
646 #define UCC_SLOW_GUMR_L_ENR		0x00000020
647 #define UCC_SLOW_GUMR_L_ENT		0x00000010
648 #define UCC_SLOW_GUMR_L_MODE_MASK	0x0000000F
649 #define UCC_SLOW_GUMR_L_MODE_BISYNC	0x00000008
650 #define UCC_SLOW_GUMR_L_MODE_AHDLC	0x00000006
651 #define UCC_SLOW_GUMR_L_MODE_UART	0x00000004
652 #define UCC_SLOW_GUMR_L_MODE_QMC	0x00000002
653 
654 /* General UCC FAST Mode Register */
655 #define UCC_FAST_GUMR_LOOPBACK	0x40000000
656 #define UCC_FAST_GUMR_TCI	0x20000000
657 #define UCC_FAST_GUMR_TRX	0x10000000
658 #define UCC_FAST_GUMR_TTX	0x08000000
659 #define UCC_FAST_GUMR_CDP	0x04000000
660 #define UCC_FAST_GUMR_CTSP	0x02000000
661 #define UCC_FAST_GUMR_CDS	0x01000000
662 #define UCC_FAST_GUMR_CTSS	0x00800000
663 #define UCC_FAST_GUMR_TXSY	0x00020000
664 #define UCC_FAST_GUMR_RSYN	0x00010000
665 #define UCC_FAST_GUMR_SYNL_MASK	0x0000C000
666 #define UCC_FAST_GUMR_SYNL_16	0x0000C000
667 #define UCC_FAST_GUMR_SYNL_8	0x00008000
668 #define UCC_FAST_GUMR_SYNL_AUTO	0x00004000
669 #define UCC_FAST_GUMR_RTSM	0x00002000
670 #define UCC_FAST_GUMR_REVD	0x00000400
671 #define UCC_FAST_GUMR_ENR	0x00000020
672 #define UCC_FAST_GUMR_ENT	0x00000010
673 
674 /* UART Slow UCC Event Register (UCCE) */
675 #define UCC_UART_UCCE_AB	0x0200
676 #define UCC_UART_UCCE_IDLE	0x0100
677 #define UCC_UART_UCCE_GRA	0x0080
678 #define UCC_UART_UCCE_BRKE	0x0040
679 #define UCC_UART_UCCE_BRKS	0x0020
680 #define UCC_UART_UCCE_CCR	0x0008
681 #define UCC_UART_UCCE_BSY	0x0004
682 #define UCC_UART_UCCE_TX	0x0002
683 #define UCC_UART_UCCE_RX	0x0001
684 
685 /* HDLC Slow UCC Event Register (UCCE) */
686 #define UCC_HDLC_UCCE_GLR	0x1000
687 #define UCC_HDLC_UCCE_GLT	0x0800
688 #define UCC_HDLC_UCCE_IDLE	0x0100
689 #define UCC_HDLC_UCCE_BRKE	0x0040
690 #define UCC_HDLC_UCCE_BRKS	0x0020
691 #define UCC_HDLC_UCCE_TXE	0x0010
692 #define UCC_HDLC_UCCE_RXF	0x0008
693 #define UCC_HDLC_UCCE_BSY	0x0004
694 #define UCC_HDLC_UCCE_TXB	0x0002
695 #define UCC_HDLC_UCCE_RXB	0x0001
696 
697 /* BISYNC Slow UCC Event Register (UCCE) */
698 #define UCC_BISYNC_UCCE_GRA	0x0080
699 #define UCC_BISYNC_UCCE_TXE	0x0010
700 #define UCC_BISYNC_UCCE_RCH	0x0008
701 #define UCC_BISYNC_UCCE_BSY	0x0004
702 #define UCC_BISYNC_UCCE_TXB	0x0002
703 #define UCC_BISYNC_UCCE_RXB	0x0001
704 
705 /* Gigabit Ethernet Fast UCC Event Register (UCCE) */
706 #define UCC_GETH_UCCE_MPD       0x80000000
707 #define UCC_GETH_UCCE_SCAR      0x40000000
708 #define UCC_GETH_UCCE_GRA       0x20000000
709 #define UCC_GETH_UCCE_CBPR      0x10000000
710 #define UCC_GETH_UCCE_BSY       0x08000000
711 #define UCC_GETH_UCCE_RXC       0x04000000
712 #define UCC_GETH_UCCE_TXC       0x02000000
713 #define UCC_GETH_UCCE_TXE       0x01000000
714 #define UCC_GETH_UCCE_TXB7      0x00800000
715 #define UCC_GETH_UCCE_TXB6      0x00400000
716 #define UCC_GETH_UCCE_TXB5      0x00200000
717 #define UCC_GETH_UCCE_TXB4      0x00100000
718 #define UCC_GETH_UCCE_TXB3      0x00080000
719 #define UCC_GETH_UCCE_TXB2      0x00040000
720 #define UCC_GETH_UCCE_TXB1      0x00020000
721 #define UCC_GETH_UCCE_TXB0      0x00010000
722 #define UCC_GETH_UCCE_RXB7      0x00008000
723 #define UCC_GETH_UCCE_RXB6      0x00004000
724 #define UCC_GETH_UCCE_RXB5      0x00002000
725 #define UCC_GETH_UCCE_RXB4      0x00001000
726 #define UCC_GETH_UCCE_RXB3      0x00000800
727 #define UCC_GETH_UCCE_RXB2      0x00000400
728 #define UCC_GETH_UCCE_RXB1      0x00000200
729 #define UCC_GETH_UCCE_RXB0      0x00000100
730 #define UCC_GETH_UCCE_RXF7      0x00000080
731 #define UCC_GETH_UCCE_RXF6      0x00000040
732 #define UCC_GETH_UCCE_RXF5      0x00000020
733 #define UCC_GETH_UCCE_RXF4      0x00000010
734 #define UCC_GETH_UCCE_RXF3      0x00000008
735 #define UCC_GETH_UCCE_RXF2      0x00000004
736 #define UCC_GETH_UCCE_RXF1      0x00000002
737 #define UCC_GETH_UCCE_RXF0      0x00000001
738 
739 /* UCC Protocol Specific Mode Register (UPSMR), when used for UART */
740 #define UCC_UART_UPSMR_FLC		0x8000
741 #define UCC_UART_UPSMR_SL		0x4000
742 #define UCC_UART_UPSMR_CL_MASK		0x3000
743 #define UCC_UART_UPSMR_CL_8		0x3000
744 #define UCC_UART_UPSMR_CL_7		0x2000
745 #define UCC_UART_UPSMR_CL_6		0x1000
746 #define UCC_UART_UPSMR_CL_5		0x0000
747 #define UCC_UART_UPSMR_UM_MASK		0x0c00
748 #define UCC_UART_UPSMR_UM_NORMAL	0x0000
749 #define UCC_UART_UPSMR_UM_MAN_MULTI	0x0400
750 #define UCC_UART_UPSMR_UM_AUTO_MULTI	0x0c00
751 #define UCC_UART_UPSMR_FRZ		0x0200
752 #define UCC_UART_UPSMR_RZS		0x0100
753 #define UCC_UART_UPSMR_SYN		0x0080
754 #define UCC_UART_UPSMR_DRT		0x0040
755 #define UCC_UART_UPSMR_PEN		0x0010
756 #define UCC_UART_UPSMR_RPM_MASK		0x000c
757 #define UCC_UART_UPSMR_RPM_ODD		0x0000
758 #define UCC_UART_UPSMR_RPM_LOW		0x0004
759 #define UCC_UART_UPSMR_RPM_EVEN		0x0008
760 #define UCC_UART_UPSMR_RPM_HIGH		0x000C
761 #define UCC_UART_UPSMR_TPM_MASK		0x0003
762 #define UCC_UART_UPSMR_TPM_ODD		0x0000
763 #define UCC_UART_UPSMR_TPM_LOW		0x0001
764 #define UCC_UART_UPSMR_TPM_EVEN		0x0002
765 #define UCC_UART_UPSMR_TPM_HIGH		0x0003
766 
767 /* UCC Protocol Specific Mode Register (UPSMR), when used for Ethernet */
768 #define UCC_GETH_UPSMR_FTFE     0x80000000
769 #define UCC_GETH_UPSMR_PTPE     0x40000000
770 #define UCC_GETH_UPSMR_ECM      0x04000000
771 #define UCC_GETH_UPSMR_HSE      0x02000000
772 #define UCC_GETH_UPSMR_PRO      0x00400000
773 #define UCC_GETH_UPSMR_CAP      0x00200000
774 #define UCC_GETH_UPSMR_RSH      0x00100000
775 #define UCC_GETH_UPSMR_RPM      0x00080000
776 #define UCC_GETH_UPSMR_R10M     0x00040000
777 #define UCC_GETH_UPSMR_RLPB     0x00020000
778 #define UCC_GETH_UPSMR_TBIM     0x00010000
779 #define UCC_GETH_UPSMR_RES1     0x00002000
780 #define UCC_GETH_UPSMR_RMM      0x00001000
781 #define UCC_GETH_UPSMR_CAM      0x00000400
782 #define UCC_GETH_UPSMR_BRO      0x00000200
783 #define UCC_GETH_UPSMR_SMM	0x00000080
784 #define UCC_GETH_UPSMR_SGMM	0x00000020
785 
786 /* UCC Protocol Specific Mode Register (UPSMR), when used for HDLC */
787 #define UCC_HDLC_UPSMR_RTE	0x02000000
788 #define UCC_HDLC_UPSMR_BUS	0x00200000
789 #define UCC_HDLC_UPSMR_CW8	0x00007000
790 
791 /* UCC Transmit On Demand Register (UTODR) */
792 #define UCC_SLOW_TOD	0x8000
793 #define UCC_FAST_TOD	0x8000
794 
795 /* UCC Bus Mode Register masks */
796 /* Not to be confused with the Bundle Mode Register */
797 #define UCC_BMR_GBL		0x20
798 #define UCC_BMR_BO_BE		0x10
799 #define UCC_BMR_CETM		0x04
800 #define UCC_BMR_DTB		0x02
801 #define UCC_BMR_BDB		0x01
802 
803 /* Function code masks */
804 #define FC_GBL				0x20
805 #define FC_DTB_LCL			0x02
806 #define UCC_FAST_FUNCTION_CODE_GBL	0x20
807 #define UCC_FAST_FUNCTION_CODE_DTB_LCL	0x02
808 #define UCC_FAST_FUNCTION_CODE_BDB_LCL	0x01
809 
810 #endif /* __KERNEL__ */
811 #endif /* _ASM_POWERPC_QE_H */
812