1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Common internal memory map for some Freescale SoCs 4 * 5 * Copyright 2014 Freescale Semiconductor, Inc. 6 */ 7 8 #ifndef __FSL_SEC_H 9 #define __FSL_SEC_H 10 11 #include <common.h> 12 #include <asm/io.h> 13 14 #ifdef CONFIG_SYS_FSL_SEC_LE 15 #define sec_in32(a) in_le32(a) 16 #define sec_out32(a, v) out_le32(a, v) 17 #define sec_in16(a) in_le16(a) 18 #define sec_clrbits32 clrbits_le32 19 #define sec_setbits32 setbits_le32 20 #elif defined(CONFIG_SYS_FSL_SEC_BE) 21 #define sec_in32(a) in_be32(a) 22 #define sec_out32(a, v) out_be32(a, v) 23 #define sec_in16(a) in_be16(a) 24 #define sec_clrbits32 clrbits_be32 25 #define sec_setbits32 setbits_be32 26 #elif defined(CONFIG_SYS_FSL_HAS_SEC) 27 #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined 28 #endif 29 30 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ 31 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 32 /* RNG4 TRNG test registers */ 33 struct rng4tst { 34 #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */ 35 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in 36 both entropy shifter and 37 statistical checker */ 38 #define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both 39 entropy shifter and 40 statistical checker */ 41 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in 42 entropy shifter, raw data 43 in statistical checker */ 44 #define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */ 45 u32 rtmctl; /* misc. control register */ 46 u32 rtscmisc; /* statistical check misc. register */ 47 u32 rtpkrrng; /* poker range register */ 48 #define RTSDCTL_ENT_DLY_MIN 3200 49 #define RTSDCTL_ENT_DLY_MAX 12800 50 union { 51 u32 rtpkrmax; /* PRGM=1: poker max. limit register */ 52 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */ 53 }; 54 #define RTSDCTL_ENT_DLY_SHIFT 16 55 #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT) 56 u32 rtsdctl; /* seed control register */ 57 union { 58 u32 rtsblim; /* PRGM=1: sparse bit limit register */ 59 u32 rttotsam; /* PRGM=0: total samples register */ 60 }; 61 u32 rtfreqmin; /* frequency count min. limit register */ 62 #define RTFRQMAX_DISABLE (1 << 20) 63 union { 64 u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */ 65 u32 rtfreqcnt; /* PRGM=0: freq. count register */ 66 }; 67 u32 rsvd1[40]; 68 #define RDSTA_IF(idx) (0x00000001 << (idx)) 69 #define RDSTA_PR(idx) (0x00000010 << (idx)) 70 #define RDSTA_MASK (RDSTA_PR(1) | RDSTA_PR(0) | RDSTA_IF(1) | RDSTA_IF(0)) 71 #define RDSTA_SKVN 0x40000000 72 u32 rdsta; /*RNG DRNG Status Register*/ 73 u32 rsvd2[15]; 74 }; 75 76 /* Version registers (Era 10+) */ 77 struct version_regs { 78 u32 crca; /* CRCA_VERSION */ 79 u32 afha; /* AFHA_VERSION */ 80 u32 kfha; /* KFHA_VERSION */ 81 u32 pkha; /* PKHA_VERSION */ 82 u32 aesa; /* AESA_VERSION */ 83 u32 mdha; /* MDHA_VERSION */ 84 u32 desa; /* DESA_VERSION */ 85 u32 snw8a; /* SNW8A_VERSION */ 86 u32 snw9a; /* SNW9A_VERSION */ 87 u32 zuce; /* ZUCE_VERSION */ 88 u32 zuca; /* ZUCA_VERSION */ 89 u32 ccha; /* CCHA_VERSION */ 90 u32 ptha; /* PTHA_VERSION */ 91 u32 rng; /* RNG_VERSION */ 92 u32 trng; /* TRNG_VERSION */ 93 u32 aaha; /* AAHA_VERSION */ 94 u32 rsvd[10]; 95 u32 sr; /* SR_VERSION */ 96 u32 dma; /* DMA_VERSION */ 97 u32 ai; /* AI_VERSION */ 98 u32 qi; /* QI_VERSION */ 99 u32 jr; /* JR_VERSION */ 100 u32 deco; /* DECO_VERSION */ 101 }; 102 103 #define CHA_VER_NUM_MASK 0x000000ff 104 #define CHA_VER_MISC_SHIFT 8 105 #define CHA_VER_MISC_MASK 0x0000ff00 106 #define CHA_VER_REV_SHIFT 16 107 #define CHA_VER_REV_MASK 0x00ff0000 108 #define CHA_VER_VID_SHIFT 24 109 #define CHA_VER_VID_MASK 0xff000000 110 111 typedef struct ccsr_sec { 112 u32 res0; 113 u32 mcfgr; /* Master CFG Register */ 114 u8 res1[0x4]; 115 u32 scfgr; 116 struct { 117 u32 ms; /* Job Ring LIODN Register, MS */ 118 u32 ls; /* Job Ring LIODN Register, LS */ 119 } jrliodnr[4]; 120 u8 res2[0x2c]; 121 u32 jrstartr; /* Job Ring Start Register */ 122 struct { 123 u32 ms; /* RTIC LIODN Register, MS */ 124 u32 ls; /* RTIC LIODN Register, LS */ 125 } rticliodnr[4]; 126 u8 res3[0x1c]; 127 u32 decorr; /* DECO Request Register */ 128 struct { 129 u32 ms; /* DECO LIODN Register, MS */ 130 u32 ls; /* DECO LIODN Register, LS */ 131 } decoliodnr[16]; 132 u32 dar; /* DECO Avail Register */ 133 u32 drr; /* DECO Reset Register */ 134 u8 res5[0x4d8]; 135 struct rng4tst rng; /* RNG Registers */ 136 u8 res6[0x780]; 137 struct version_regs vreg; /* version registers since era 10 */ 138 u8 res7[0xa0]; 139 u32 crnr_ms; /* CHA Revision Number Register, MS */ 140 u32 crnr_ls; /* CHA Revision Number Register, LS */ 141 u32 ctpr_ms; /* Compile Time Parameters Register, MS */ 142 u32 ctpr_ls; /* Compile Time Parameters Register, LS */ 143 u8 res8[0x10]; 144 u32 far_ms; /* Fault Address Register, MS */ 145 u32 far_ls; /* Fault Address Register, LS */ 146 u32 falr; /* Fault Address LIODN Register */ 147 u32 fadr; /* Fault Address Detail Register */ 148 u8 res9[0x4]; 149 u32 csta; /* CAAM Status Register */ 150 u32 smpart; /* Secure Memory Partition Parameters */ 151 u32 smvid; /* Secure Memory Version ID */ 152 u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/ 153 u32 ccbvid; /* CHA Cluster Block Version ID Register */ 154 u32 chavid_ms; /* CHA Version ID Register, MS */ 155 u32 chavid_ls; /* CHA Version ID Register, LS */ 156 u32 chanum_ms; /* CHA Number Register, MS */ 157 u32 chanum_ls; /* CHA Number Register, LS */ 158 u32 secvid_ms; /* SEC Version ID Register, MS */ 159 u32 secvid_ls; /* SEC Version ID Register, LS */ 160 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) 161 u8 res10[0x6f020]; 162 #else 163 u8 res10[0x6020]; 164 #endif 165 u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */ 166 u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */ 167 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) 168 u8 res11[0x8ffd8]; 169 #else 170 u8 res11[0x8fd8]; 171 #endif 172 } ccsr_sec_t; 173 174 #define SEC_CTPR_MS_AXI_LIODN 0x08000000 175 #define SEC_CTPR_MS_QI 0x02000000 176 #define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001 177 #define SEC_CTPR_MS_VIRT_EN_POR 0x00000002 178 #define SEC_RVID_MA 0x0f000000 179 #define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000 180 #define SEC_CHANUM_MS_JRNUM_SHIFT 28 181 #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000 182 #define SEC_CHANUM_MS_DECONUM_SHIFT 24 183 #define SEC_SECVID_MS_IPID_MASK 0xffff0000 184 #define SEC_SECVID_MS_IPID_SHIFT 16 185 #define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00 186 #define SEC_SECVID_MS_MAJ_REV_SHIFT 8 187 #define SEC_CCBVID_ERA_MASK 0xff000000 188 #define SEC_CCBVID_ERA_SHIFT 24 189 #define SEC_SCFGR_RDBENABLE 0x00000400 190 #define SEC_SCFGR_VIRT_EN 0x00008000 191 #define SEC_CHAVID_LS_RNG_SHIFT 16 192 #define SEC_CHAVID_RNG_LS_MASK 0x000f0000 193 194 #define CONFIG_JRSTARTR_JR0 0x00000001 195 196 struct jr_regs { 197 #if defined(CONFIG_SYS_FSL_SEC_LE) && \ 198 !(defined(CONFIG_MX6) || defined(CONFIG_MX7)) 199 u32 irba_l; 200 u32 irba_h; 201 #else 202 u32 irba_h; 203 u32 irba_l; 204 #endif 205 u32 rsvd1; 206 u32 irs; 207 u32 rsvd2; 208 u32 irsa; 209 u32 rsvd3; 210 u32 irja; 211 #if defined(CONFIG_SYS_FSL_SEC_LE) && \ 212 !(defined(CONFIG_MX6) || defined(CONFIG_MX7)) 213 u32 orba_l; 214 u32 orba_h; 215 #else 216 u32 orba_h; 217 u32 orba_l; 218 #endif 219 u32 rsvd4; 220 u32 ors; 221 u32 rsvd5; 222 u32 orjr; 223 u32 rsvd6; 224 u32 orsf; 225 u32 rsvd7; 226 u32 jrsta; 227 u32 rsvd8; 228 u32 jrint; 229 u32 jrcfg0; 230 u32 jrcfg1; 231 u32 rsvd9; 232 u32 irri; 233 u32 rsvd10; 234 u32 orwi; 235 u32 rsvd11; 236 u32 jrcr; 237 }; 238 239 /* 240 * Scatter Gather Entry - Specifies the the Scatter Gather Format 241 * related information 242 */ 243 struct sg_entry { 244 #if defined(CONFIG_SYS_FSL_SEC_LE) && \ 245 !(defined(CONFIG_MX6) || defined(CONFIG_MX7)) 246 uint32_t addr_lo; /* Memory Address - lo */ 247 uint32_t addr_hi; /* Memory Address of start of buffer - hi */ 248 #else 249 uint32_t addr_hi; /* Memory Address of start of buffer - hi */ 250 uint32_t addr_lo; /* Memory Address - lo */ 251 #endif 252 253 uint32_t len_flag; /* Length of the data in the frame */ 254 #define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF 255 #define SG_ENTRY_EXTENSION_BIT 0x80000000 256 #define SG_ENTRY_FINAL_BIT 0x40000000 257 uint32_t bpid_offset; 258 #define SG_ENTRY_BPID_MASK 0x00FF0000 259 #define SG_ENTRY_BPID_SHIFT 16 260 #define SG_ENTRY_OFFSET_MASK 0x00001FFF 261 #define SG_ENTRY_OFFSET_SHIFT 0 262 }; 263 264 #define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */ 265 266 #if defined(CONFIG_MX6) || defined(CONFIG_MX7) 267 /* Job Ring Base Address */ 268 #define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1)) 269 /* Secure Memory Offset varies accross versions */ 270 #define SM_V1_OFFSET 0x0f4 271 #define SM_V2_OFFSET 0xa00 272 /*Secure Memory Versioning */ 273 #define SMVID_V2 0x20105 274 #define SM_VERSION(x) (x < SMVID_V2 ? 1 : 2) 275 #define SM_OFFSET(x) (x == 1 ? SM_V1_OFFSET : SM_V2_OFFSET) 276 /* CAAM Job Ring 0 Registers */ 277 /* Secure Memory Partition Owner register */ 278 #define SMCSJR_PO (3 << 6) 279 /* JR Allocation Error */ 280 #define SMCSJR_AERR (3 << 12) 281 /* Secure memory partition 0 page 0 owner register */ 282 #define CAAM_SMPO_0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC) 283 /* Secure memory command register */ 284 #define CAAM_SMCJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v)) 285 /* Secure memory command status register */ 286 #define CAAM_SMCSJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_STATUS(v)) 287 /* Secure memory access permissions register */ 288 #define CAAM_SMAPJR(v, jr, y) \ 289 (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_PERM(v) + y * 16) 290 /* Secure memory access group 2 register */ 291 #define CAAM_SMAG2JR(v, jr, y) \ 292 (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP2(v) + y * 16) 293 /* Secure memory access group 1 register */ 294 #define CAAM_SMAG1JR(v, jr, y) \ 295 (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP1(v) + y * 16) 296 297 /* Commands and macros for secure memory */ 298 #define SM_CMD(v) (v == 1 ? 0x0 : 0x1E4) 299 #define SM_STATUS(v) (v == 1 ? 0x8 : 0x1EC) 300 #define SM_PERM(v) (v == 1 ? 0x10 : 0x4) 301 #define SM_GROUP2(v) (v == 1 ? 0x14 : 0x8) 302 #define SM_GROUP1(v) (v == 1 ? 0x18 : 0xC) 303 #define CMD_PAGE_ALLOC 0x1 304 #define CMD_PAGE_DEALLOC 0x2 305 #define CMD_PART_DEALLOC 0x3 306 #define CMD_INQUIRY 0x5 307 #define CMD_COMPLETE (3 << 14) 308 #define PAGE_AVAILABLE 0 309 #define PAGE_OWNED (3 << 6) 310 #define PAGE(x) (x << 16) 311 #define PARTITION(x) (x << 8) 312 #define PARTITION_OWNER(x) (0x3 << (x*2)) 313 314 /* Address of secure 4kbyte pages */ 315 #define SEC_MEM_PAGE0 CAAM_ARB_BASE_ADDR 316 #define SEC_MEM_PAGE1 (CAAM_ARB_BASE_ADDR + 0x1000) 317 #define SEC_MEM_PAGE2 (CAAM_ARB_BASE_ADDR + 0x2000) 318 #define SEC_MEM_PAGE3 (CAAM_ARB_BASE_ADDR + 0x3000) 319 320 #define JR_MID 2 /* Matches ROM configuration */ 321 #define KS_G1 (1 << JR_MID) /* CAAM only */ 322 #define PERM 0x0000B008 /* Clear on release, lock SMAP 323 * lock SMAG group 1 Blob */ 324 325 /* HAB WRAPPED KEY header */ 326 #define WRP_HDR_SIZE 0x08 327 #define HDR_TAG 0x81 328 #define HDR_PAR 0x41 329 /* HAB WRAPPED KEY Data */ 330 #define HAB_MOD 0x66 331 #define HAB_ALG 0x55 332 #define HAB_FLG 0x00 333 334 /* Partition and Page IDs */ 335 #define PARTITION_1 1 336 #define PAGE_1 1 337 338 #define ERROR_IN_PAGE_ALLOC 1 339 #define ECONSTRJDESC -1 340 341 #endif 342 343 /* blob_dek: 344 * Encapsulates the src in a secure blob and stores it dst 345 * @src: reference to the plaintext 346 * @dst: reference to the output adrress 347 * @len: size in bytes of src 348 * @return: 0 on success, error otherwise 349 */ 350 int blob_dek(const u8 *src, u8 *dst, u8 len); 351 352 #if defined(CONFIG_ARCH_C29X) 353 int sec_init_idx(uint8_t); 354 #endif 355 int sec_init(void); 356 357 u8 caam_get_era(void); 358 #endif 359 360 #endif /* __FSL_SEC_H */ 361