1 /****************************************************************************** 2 * config.h 3 * 4 * A Linux-style configuration list. 5 */ 6 7 #ifndef __X86_CONFIG_H__ 8 #define __X86_CONFIG_H__ 9 10 #define LONG_BYTEORDER 3 11 #define CONFIG_PAGING_LEVELS 4 12 13 #define BYTES_PER_LONG (1 << LONG_BYTEORDER) 14 #define BITS_PER_LONG (BYTES_PER_LONG << 3) 15 #define BITS_PER_BYTE 8 16 #define POINTER_ALIGN BYTES_PER_LONG 17 18 #define BITS_PER_LLONG 64 19 20 #define BITS_PER_XEN_ULONG BITS_PER_LONG 21 22 #define CONFIG_X86_PM_TIMER 1 23 #define CONFIG_HPET_TIMER 1 24 #define CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1 25 #define CONFIG_DISCONTIGMEM 1 26 #define CONFIG_NUMA_EMU 1 27 #define CONFIG_DOMAIN_PAGE 1 28 29 #define CONFIG_PAGEALLOC_MAX_ORDER (2 * PAGETABLE_ORDER) 30 #define CONFIG_DOMU_MAX_ORDER PAGETABLE_ORDER 31 #define CONFIG_HWDOM_MAX_ORDER 12 32 33 /* Intel P4 currently has largest cache line (L2 line size is 128 bytes). */ 34 #define CONFIG_X86_L1_CACHE_SHIFT 7 35 36 #define CONFIG_ACPI_NUMA 1 37 #define CONFIG_ACPI_SRAT 1 38 #define CONFIG_ACPI_CSTATE 1 39 40 #define CONFIG_WATCHDOG 1 41 42 #define CONFIG_MULTIBOOT 1 43 44 #define HZ 100 45 46 #define OPT_CONSOLE_STR "vga" 47 48 /* Linkage for x86 */ 49 #ifdef __ASSEMBLY__ 50 #define ALIGN .align 16,0x90 51 #define ENTRY(name) \ 52 .globl name; \ 53 ALIGN; \ 54 name: 55 #define GLOBAL(name) \ 56 .globl name; \ 57 name: 58 #endif 59 60 #define NR_hypercalls 64 61 62 #ifndef NDEBUG 63 #define MEMORY_GUARD 64 #endif 65 66 #define STACK_ORDER 3 67 #define STACK_SIZE (PAGE_SIZE << STACK_ORDER) 68 69 #define IST_SHSTK_SIZE 1024 70 71 #define TRAMPOLINE_STACK_SPACE PAGE_SIZE 72 #define TRAMPOLINE_SPACE (KB(64) - TRAMPOLINE_STACK_SPACE) 73 #define WAKEUP_STACK_MIN 3072 74 75 #define MBI_SPACE_MIN (2 * PAGE_SIZE) 76 77 /* Primary stack is restricted to 8kB by guard pages. */ 78 #define PRIMARY_STACK_SIZE 8192 79 80 /* Primary shadow stack is slot 5 of 8, immediately under the primary stack. */ 81 #define PRIMARY_SHSTK_SLOT 5 82 83 /* Total size of syscall and emulation stubs. */ 84 #define STUB_BUF_SHIFT (L1_CACHE_SHIFT > 7 ? L1_CACHE_SHIFT : 7) 85 #define STUB_BUF_SIZE (1 << STUB_BUF_SHIFT) 86 #define STUBS_PER_PAGE (PAGE_SIZE / STUB_BUF_SIZE) 87 88 /* Return value for zero-size _xmalloc(), distinguished from NULL. */ 89 #define ZERO_BLOCK_PTR ((void *)0xBAD0BAD0BAD0BAD0UL) 90 91 /* Override include/xen/list.h to make these non-canonical addresses. */ 92 #define LIST_POISON1 ((void *)0x0100100100100100UL) 93 #define LIST_POISON2 ((void *)0x0200200200200200UL) 94 95 #ifndef __ASSEMBLY__ 96 extern unsigned long trampoline_phys; 97 #define bootsym_phys(sym) \ 98 (((unsigned long)&(sym)-(unsigned long)&trampoline_start)+trampoline_phys) 99 #define bootsym(sym) \ 100 (*((typeof(sym) *)__va(bootsym_phys(sym)))) 101 102 extern char trampoline_start[], trampoline_end[]; 103 extern char trampoline_realmode_entry[]; 104 extern unsigned int trampoline_xen_phys_start; 105 extern unsigned char trampoline_cpu_started; 106 extern char wakeup_start[]; 107 108 extern unsigned char video_flags; 109 110 extern unsigned short boot_edid_caps; 111 extern unsigned char boot_edid_info[128]; 112 #endif 113 114 #include <xen/const.h> 115 116 #define PML4_ENTRY_BITS 39 117 #define PML4_ENTRY_BYTES (_AC(1,UL) << PML4_ENTRY_BITS) 118 #define PML4_ADDR(_slot) \ 119 (((_AC(_slot, UL) >> 8) * _AC(0xffff000000000000,UL)) | \ 120 (_AC(_slot, UL) << PML4_ENTRY_BITS)) 121 122 /* 123 * Memory layout: 124 * 0x0000000000000000 - 0x00007fffffffffff [128TB, 2^47 bytes, PML4:0-255] 125 * Guest-defined use (see below for compatibility mode guests). 126 * 0x0000800000000000 - 0xffff7fffffffffff [16EB] 127 * Inaccessible: current arch only supports 48-bit sign-extended VAs. 128 * 0xffff800000000000 - 0xffff803fffffffff [256GB, 2^38 bytes, PML4:256] 129 * Read-only machine-to-phys translation table (GUEST ACCESSIBLE). 130 * 0xffff804000000000 - 0xffff807fffffffff [256GB, 2^38 bytes, PML4:256] 131 * Reserved for future shared info with the guest OS (GUEST ACCESSIBLE). 132 * 0xffff808000000000 - 0xffff80ffffffffff [512GB, 2^39 bytes, PML4:257] 133 * ioremap for PCI mmconfig space 134 * 0xffff810000000000 - 0xffff817fffffffff [512GB, 2^39 bytes, PML4:258] 135 * Guest linear page table. 136 * 0xffff818000000000 - 0xffff81ffffffffff [512GB, 2^39 bytes, PML4:259] 137 * Shadow linear page table. 138 * 0xffff820000000000 - 0xffff827fffffffff [512GB, 2^39 bytes, PML4:260] 139 * Per-domain mappings (e.g., GDT, LDT). 140 * 0xffff828000000000 - 0xffff82bfffffffff [256GB, 2^38 bytes, PML4:261] 141 * Machine-to-phys translation table. 142 * 0xffff82c000000000 - 0xffff82cfffffffff [64GB, 2^36 bytes, PML4:261] 143 * vmap()/ioremap()/fixmap area. 144 * 0xffff82d000000000 - 0xffff82d03fffffff [1GB, 2^30 bytes, PML4:261] 145 * Compatibility machine-to-phys translation table. 146 * 0xffff82d040000000 - 0xffff82d07fffffff [1GB, 2^30 bytes, PML4:261] 147 * Xen text, static data, bss. 148 #ifndef CONFIG_BIGMEM 149 * 0xffff82d080000000 - 0xffff82dfffffffff [62GB, PML4:261] 150 * Reserved for future use. 151 * 0xffff82e000000000 - 0xffff82ffffffffff [128GB, 2^37 bytes, PML4:261] 152 * Page-frame information array. 153 * 0xffff830000000000 - 0xffff87ffffffffff [5TB, 5*2^40 bytes, PML4:262-271] 154 * 1:1 direct mapping of all physical memory. 155 #else 156 * 0xffff82d080000000 - 0xffff82ffffffffff [190GB, PML4:261] 157 * Reserved for future use. 158 * 0xffff830000000000 - 0xffff847fffffffff [1.5TB, 3*2^39 bytes, PML4:262-264] 159 * Page-frame information array. 160 * 0xffff848000000000 - 0xffff87ffffffffff [3.5TB, 7*2^39 bytes, PML4:265-271] 161 * 1:1 direct mapping of all physical memory. 162 #endif 163 * 0xffff880000000000 - 0xffffffffffffffff [120TB, PML4:272-511] 164 * PV: Guest-defined use. 165 * 0xffff880000000000 - 0xffffff7fffffffff [119.5TB, PML4:272-510] 166 * HVM/idle: continuation of 1:1 mapping 167 * 0xffffff8000000000 - 0xffffffffffffffff [512GB, 2^39 bytes PML4:511] 168 * HVM/idle: unused 169 * 170 * Compatibility guest area layout: 171 * 0x0000000000000000 - 0x00000000f57fffff [3928MB, PML4:0] 172 * Guest-defined use. 173 * 0x00000000f5800000 - 0x00000000ffffffff [168MB, PML4:0] 174 * Read-only machine-to-phys translation table (GUEST ACCESSIBLE). 175 * 0x0000000100000000 - 0x00007fffffffffff [128TB-4GB, PML4:0-255] 176 * Unused / Reserved for future use. 177 */ 178 179 180 #define ROOT_PAGETABLE_FIRST_XEN_SLOT 256 181 #define ROOT_PAGETABLE_LAST_XEN_SLOT 271 182 #define ROOT_PAGETABLE_XEN_SLOTS \ 183 (L4_PAGETABLE_ENTRIES - ROOT_PAGETABLE_FIRST_XEN_SLOT - 1) 184 #define ROOT_PAGETABLE_PV_XEN_SLOTS \ 185 (ROOT_PAGETABLE_LAST_XEN_SLOT - ROOT_PAGETABLE_FIRST_XEN_SLOT + 1) 186 187 /* Hypervisor reserves PML4 slots 256 to 271 inclusive. */ 188 #define HYPERVISOR_VIRT_START (PML4_ADDR(256)) 189 #define HYPERVISOR_VIRT_END (HYPERVISOR_VIRT_START + PML4_ENTRY_BYTES*16) 190 /* Slot 256: read-only guest-accessible machine-to-phys translation table. */ 191 #define RO_MPT_VIRT_START (PML4_ADDR(256)) 192 #define MPT_VIRT_SIZE (PML4_ENTRY_BYTES / 2) 193 #define RO_MPT_VIRT_END (RO_MPT_VIRT_START + MPT_VIRT_SIZE) 194 /* Slot 257: ioremap for PCI mmconfig space for 2048 segments (512GB) 195 * - full 16-bit segment support needs 44 bits 196 * - since PML4 slot has 39 bits, we limit segments to 2048 (11-bits) 197 */ 198 #define PCI_MCFG_VIRT_START (PML4_ADDR(257)) 199 #define PCI_MCFG_VIRT_END (PCI_MCFG_VIRT_START + PML4_ENTRY_BYTES) 200 /* Slot 258: linear page table (guest table). */ 201 #define LINEAR_PT_VIRT_START (PML4_ADDR(258)) 202 #define LINEAR_PT_VIRT_END (LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES) 203 /* Slot 259: linear page table (shadow table). */ 204 #define SH_LINEAR_PT_VIRT_START (PML4_ADDR(259)) 205 #define SH_LINEAR_PT_VIRT_END (SH_LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES) 206 /* Slot 260: per-domain mappings (including map cache). */ 207 #define PERDOMAIN_VIRT_START (PML4_ADDR(260)) 208 #define PERDOMAIN_SLOT_MBYTES (PML4_ENTRY_BYTES >> (20 + PAGETABLE_ORDER)) 209 #define PERDOMAIN_SLOTS 3 210 #define PERDOMAIN_VIRT_SLOT(s) (PERDOMAIN_VIRT_START + (s) * \ 211 (PERDOMAIN_SLOT_MBYTES << 20)) 212 /* Slot 261: machine-to-phys conversion table (256GB). */ 213 #define RDWR_MPT_VIRT_START (PML4_ADDR(261)) 214 #define RDWR_MPT_VIRT_END (RDWR_MPT_VIRT_START + MPT_VIRT_SIZE) 215 /* Slot 261: vmap()/ioremap()/fixmap area (64GB). */ 216 #define VMAP_VIRT_START RDWR_MPT_VIRT_END 217 #define VMAP_VIRT_END (VMAP_VIRT_START + GB(64)) 218 /* Slot 261: compatibility machine-to-phys conversion table (1GB). */ 219 #define RDWR_COMPAT_MPT_VIRT_START VMAP_VIRT_END 220 #define RDWR_COMPAT_MPT_VIRT_END (RDWR_COMPAT_MPT_VIRT_START + GB(1)) 221 /* Slot 261: xen text, static data, bss, per-cpu stubs and executable fixmap (1GB). */ 222 #define XEN_VIRT_START RDWR_COMPAT_MPT_VIRT_END 223 #define XEN_VIRT_END (XEN_VIRT_START + GB(1)) 224 225 #ifndef CONFIG_BIGMEM 226 /* Slot 261: page-frame information array (128GB). */ 227 #define FRAMETABLE_SIZE GB(128) 228 #else 229 /* Slot 262-264: page-frame information array (1.5TB). */ 230 #define FRAMETABLE_SIZE GB(1536) 231 #endif 232 #define FRAMETABLE_VIRT_END DIRECTMAP_VIRT_START 233 #define FRAMETABLE_NR (FRAMETABLE_SIZE / sizeof(*frame_table)) 234 #define FRAMETABLE_VIRT_START (FRAMETABLE_VIRT_END - FRAMETABLE_SIZE) 235 236 #ifndef CONFIG_BIGMEM 237 /* Slot 262-271/510: A direct 1:1 mapping of all of physical memory. */ 238 #define DIRECTMAP_VIRT_START (PML4_ADDR(262)) 239 #define DIRECTMAP_SIZE (PML4_ENTRY_BYTES * (511 - 262)) 240 #else 241 /* Slot 265-271/510: A direct 1:1 mapping of all of physical memory. */ 242 #define DIRECTMAP_VIRT_START (PML4_ADDR(265)) 243 #define DIRECTMAP_SIZE (PML4_ENTRY_BYTES * (511 - 265)) 244 #endif 245 #define DIRECTMAP_VIRT_END (DIRECTMAP_VIRT_START + DIRECTMAP_SIZE) 246 247 #ifndef __ASSEMBLY__ 248 249 /* This is not a fixed value, just a lower limit. */ 250 #define __HYPERVISOR_COMPAT_VIRT_START 0xF5800000 251 #define HYPERVISOR_COMPAT_VIRT_START(d) ((d)->arch.hv_compat_vstart) 252 #define MACH2PHYS_COMPAT_VIRT_START HYPERVISOR_COMPAT_VIRT_START 253 #define MACH2PHYS_COMPAT_VIRT_END 0xFFE00000 254 #define MACH2PHYS_COMPAT_NR_ENTRIES(d) \ 255 ((MACH2PHYS_COMPAT_VIRT_END-MACH2PHYS_COMPAT_VIRT_START(d))>>2) 256 257 #define COMPAT_L2_PAGETABLE_FIRST_XEN_SLOT(d) \ 258 l2_table_offset(HYPERVISOR_COMPAT_VIRT_START(d)) 259 #define COMPAT_L2_PAGETABLE_LAST_XEN_SLOT l2_table_offset(~0U) 260 #define COMPAT_L2_PAGETABLE_XEN_SLOTS(d) \ 261 (COMPAT_L2_PAGETABLE_LAST_XEN_SLOT - COMPAT_L2_PAGETABLE_FIRST_XEN_SLOT(d) + 1) 262 263 #define COMPAT_LEGACY_MAX_VCPUS XEN_LEGACY_MAX_VCPUS 264 #define COMPAT_HAVE_PV_GUEST_ENTRY XEN_HAVE_PV_GUEST_ENTRY 265 #define COMPAT_HAVE_PV_UPCALL_MASK XEN_HAVE_PV_UPCALL_MASK 266 267 #endif 268 269 #define __HYPERVISOR_CS 0xe008 270 #define __HYPERVISOR_DS64 0x0000 271 #define __HYPERVISOR_DS32 0xe010 272 #define __HYPERVISOR_DS __HYPERVISOR_DS64 273 274 #define SYMBOLS_ORIGIN XEN_VIRT_START 275 276 /* For generic assembly code: use macros to define operation/operand sizes. */ 277 #define __OS "q" /* Operation Suffix */ 278 #define __OP "r" /* Operand Prefix */ 279 280 #ifndef __ASSEMBLY__ 281 extern unsigned long xen_phys_start; 282 #endif 283 284 /* GDT/LDT shadow mapping area. The first per-domain-mapping sub-area. */ 285 #define GDT_LDT_VCPU_SHIFT 5 286 #define GDT_LDT_VCPU_VA_SHIFT (GDT_LDT_VCPU_SHIFT + PAGE_SHIFT) 287 #define GDT_LDT_MBYTES PERDOMAIN_SLOT_MBYTES 288 #define MAX_VIRT_CPUS (GDT_LDT_MBYTES << (20-GDT_LDT_VCPU_VA_SHIFT)) 289 #define GDT_LDT_VIRT_START PERDOMAIN_VIRT_SLOT(0) 290 #define GDT_LDT_VIRT_END (GDT_LDT_VIRT_START + (GDT_LDT_MBYTES << 20)) 291 292 /* The address of a particular VCPU's GDT or LDT. */ 293 #define GDT_VIRT_START(v) \ 294 (PERDOMAIN_VIRT_START + ((v)->vcpu_id << GDT_LDT_VCPU_VA_SHIFT)) 295 #define LDT_VIRT_START(v) \ 296 (GDT_VIRT_START(v) + (64*1024)) 297 298 /* map_domain_page() map cache. The second per-domain-mapping sub-area. */ 299 #define MAPCACHE_VCPU_ENTRIES (CONFIG_PAGING_LEVELS * CONFIG_PAGING_LEVELS) 300 #define MAPCACHE_ENTRIES (MAX_VIRT_CPUS * MAPCACHE_VCPU_ENTRIES) 301 #define MAPCACHE_VIRT_START PERDOMAIN_VIRT_SLOT(1) 302 #define MAPCACHE_VIRT_END (MAPCACHE_VIRT_START + \ 303 MAPCACHE_ENTRIES * PAGE_SIZE) 304 305 /* Argument translation area. The third per-domain-mapping sub-area. */ 306 #define ARG_XLAT_VIRT_START PERDOMAIN_VIRT_SLOT(2) 307 /* Allow for at least one guard page (COMPAT_ARG_XLAT_SIZE being 2 pages): */ 308 #define ARG_XLAT_VA_SHIFT (2 + PAGE_SHIFT) 309 #define ARG_XLAT_START(v) \ 310 (ARG_XLAT_VIRT_START + ((v)->vcpu_id << ARG_XLAT_VA_SHIFT)) 311 312 #define ELFSIZE 64 313 314 #define ARCH_CRASH_SAVE_VMCOREINFO 315 316 #endif /* __X86_CONFIG_H__ */ 317