1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6 #ifndef _MV_DDR_PLAT_H 7 #define _MV_DDR_PLAT_H 8 9 #include <linux/delay.h> 10 11 #define MAX_DEVICE_NUM 1 12 #define MAX_INTERFACE_NUM 1 13 #define MAX_BUS_NUM 5 14 #define DDR_IF_CTRL_SUBPHYS_NUM 3 15 16 #define DFS_LOW_FREQ_VALUE 120 17 #define SDRAM_CS_SIZE 0xfffffff /* FIXME: implement a function for cs size for each platform */ 18 19 #define INTER_REGS_BASE SOC_REGS_PHY_BASE 20 #define AP_INT_REG_START_ADDR 0xd0000000 21 #define AP_INT_REG_END_ADDR 0xd0100000 22 23 /* Controler bus divider 1 for 32 bit, 2 for 64 bit */ 24 #define DDR_CONTROLLER_BUS_WIDTH_MULTIPLIER 1 25 26 /* Tune internal training params values */ 27 #define TUNE_TRAINING_PARAMS_CK_DELAY 160 28 #define TUNE_TRAINING_PARAMS_PHYREG3VAL 0xA 29 #define TUNE_TRAINING_PARAMS_PRI_DATA 123 30 #define TUNE_TRAINING_PARAMS_NRI_DATA 123 31 #define TUNE_TRAINING_PARAMS_PRI_CTRL 74 32 #define TUNE_TRAINING_PARAMS_NRI_CTRL 74 33 #define TUNE_TRAINING_PARAMS_P_ODT_DATA 45 34 #define TUNE_TRAINING_PARAMS_N_ODT_DATA 45 35 #define TUNE_TRAINING_PARAMS_P_ODT_CTRL 45 36 #define TUNE_TRAINING_PARAMS_N_ODT_CTRL 45 37 #define TUNE_TRAINING_PARAMS_DIC 0x2 38 #define TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS 0x120012 39 #define TUNE_TRAINING_PARAMS_ODT_CONFIG_1CS 0x10000 40 #define TUNE_TRAINING_PARAMS_RTT_NOM 0x44 41 42 #define TUNE_TRAINING_PARAMS_RTT_WR_1CS 0x0 /*off*/ 43 #define TUNE_TRAINING_PARAMS_RTT_WR_2CS 0x0 /*off*/ 44 45 #define MARVELL_BOARD MARVELL_BOARD_ID_BASE 46 47 48 #define REG_DEVICE_SAR1_ADDR 0xe4204 49 #define RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET 17 50 #define RST2_CPU_DDR_CLOCK_SELECT_IN_MASK 0x1f 51 #define DEVICE_SAMPLE_AT_RESET2_REG 0x18604 52 53 #define DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET 0 54 #define DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_25MHZ 0 55 #define DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_40MHZ 1 56 57 /* DRAM Windows */ 58 #define REG_XBAR_WIN_5_CTRL_ADDR 0x20050 59 #define REG_XBAR_WIN_5_BASE_ADDR 0x20054 60 61 /* DRAM Windows */ 62 #define REG_XBAR_WIN_4_CTRL_ADDR 0x20040 63 #define REG_XBAR_WIN_4_BASE_ADDR 0x20044 64 #define REG_XBAR_WIN_4_REMAP_ADDR 0x20048 65 #define REG_XBAR_WIN_7_REMAP_ADDR 0x20078 66 #define REG_XBAR_WIN_16_CTRL_ADDR 0x200d0 67 #define REG_XBAR_WIN_16_BASE_ADDR 0x200d4 68 #define REG_XBAR_WIN_16_REMAP_ADDR 0x200dc 69 #define REG_XBAR_WIN_19_CTRL_ADDR 0x200e8 70 71 #define REG_FASTPATH_WIN_BASE_ADDR(win) (0x20180 + (0x8 * win)) 72 #define REG_FASTPATH_WIN_CTRL_ADDR(win) (0x20184 + (0x8 * win)) 73 74 #define CPU_CONFIGURATION_REG(id) (0x21800 + (id * 0x100)) 75 #define CPU_MRVL_ID_OFFSET 0x10 76 #define SAR1_CPU_CORE_MASK 0x00000018 77 #define SAR1_CPU_CORE_OFFSET 3 78 79 /* SatR defined too change topology busWidth and ECC configuration */ 80 #define DDR_SATR_CONFIG_MASK_WIDTH 0x8 81 #define DDR_SATR_CONFIG_MASK_ECC 0x10 82 #define DDR_SATR_CONFIG_MASK_ECC_PUP 0x20 83 84 #define REG_SAMPLE_RESET_HIGH_ADDR 0x18600 85 86 #define MV_BOARD_REFCLK_25MHZ 25000000 87 #define MV_BOARD_REFCLK MV_BOARD_REFCLK_25MHZ 88 89 #define MAX_DQ_NUM 40 90 91 /* dram line buffer registers */ 92 #define DLB_CTRL_REG 0x1700 93 #define DLB_EN_OFFS 0 94 #define DLB_EN_MASK 0x1 95 #define DLB_EN_ENA 1 96 #define DLB_EN_DIS 0 97 #define WR_COALESCE_EN_OFFS 2 98 #define WR_COALESCE_EN_MASK 0x1 99 #define WR_COALESCE_EN_ENA 1 100 #define WR_COALESCE_EN_DIS 0 101 #define AXI_PREFETCH_EN_OFFS 3 102 #define AXI_PREFETCH_EN_MASK 0x1 103 #define AXI_PREFETCH_EN_ENA 1 104 #define AXI_PREFETCH_EN_DIS 0 105 #define MBUS_PREFETCH_EN_OFFS 4 106 #define MBUS_PREFETCH_EN_MASK 0x1 107 #define MBUS_PREFETCH_EN_ENA 1 108 #define MBUS_PREFETCH_EN_DIS 0 109 #define PREFETCH_NXT_LN_SZ_TRIG_OFFS 6 110 #define PREFETCH_NXT_LN_SZ_TRIG_MASK 0x1 111 #define PREFETCH_NXT_LN_SZ_TRIG_ENA 1 112 #define PREFETCH_NXT_LN_SZ_TRIG_DIS 0 113 114 #define DLB_BUS_OPT_WT_REG 0x1704 115 #define DLB_AGING_REG 0x1708 116 #define DLB_EVICTION_CTRL_REG 0x170c 117 #define DLB_EVICTION_TIMERS_REG 0x1710 118 #define DLB_USER_CMD_REG 0x1714 119 #define DLB_WTS_DIFF_CS_REG 0x1770 120 #define DLB_WTS_DIFF_BG_REG 0x1774 121 #define DLB_WTS_SAME_BG_REG 0x1778 122 #define DLB_WTS_CMDS_REG 0x177c 123 #define DLB_WTS_ATTR_PRIO_REG 0x1780 124 #define DLB_QUEUE_MAP_REG 0x1784 125 #define DLB_SPLIT_REG 0x1788 126 127 /* ck swap control subphy number */ 128 #define CK_SWAP_CTRL_PHY_NUM 2 129 130 /* Subphy result control per byte registers */ 131 #define RESULT_CONTROL_BYTE_PUP_0_REG 0x1830 132 #define RESULT_CONTROL_BYTE_PUP_1_REG 0x1834 133 #define RESULT_CONTROL_BYTE_PUP_2_REG 0x1838 134 #define RESULT_CONTROL_BYTE_PUP_3_REG 0x183c 135 #define RESULT_CONTROL_BYTE_PUP_4_REG 0x18b0 136 137 /* Subphy result control per bit registers */ 138 #define RESULT_CONTROL_PUP_0_BIT_0_REG 0x18b4 139 #define RESULT_CONTROL_PUP_0_BIT_1_REG 0x18b8 140 #define RESULT_CONTROL_PUP_0_BIT_2_REG 0x18bc 141 #define RESULT_CONTROL_PUP_0_BIT_3_REG 0x18c0 142 #define RESULT_CONTROL_PUP_0_BIT_4_REG 0x18c4 143 #define RESULT_CONTROL_PUP_0_BIT_5_REG 0x18c8 144 #define RESULT_CONTROL_PUP_0_BIT_6_REG 0x18cc 145 #define RESULT_CONTROL_PUP_0_BIT_7_REG 0x18f0 146 147 #define RESULT_CONTROL_PUP_1_BIT_0_REG 0x18f4 148 #define RESULT_CONTROL_PUP_1_BIT_1_REG 0x18f8 149 #define RESULT_CONTROL_PUP_1_BIT_2_REG 0x18fc 150 #define RESULT_CONTROL_PUP_1_BIT_3_REG 0x1930 151 #define RESULT_CONTROL_PUP_1_BIT_4_REG 0x1934 152 #define RESULT_CONTROL_PUP_1_BIT_5_REG 0x1938 153 #define RESULT_CONTROL_PUP_1_BIT_6_REG 0x193c 154 #define RESULT_CONTROL_PUP_1_BIT_7_REG 0x19b0 155 156 #define RESULT_CONTROL_PUP_2_BIT_0_REG 0x19b4 157 #define RESULT_CONTROL_PUP_2_BIT_1_REG 0x19b8 158 #define RESULT_CONTROL_PUP_2_BIT_2_REG 0x19bc 159 #define RESULT_CONTROL_PUP_2_BIT_3_REG 0x19c0 160 #define RESULT_CONTROL_PUP_2_BIT_4_REG 0x19c4 161 #define RESULT_CONTROL_PUP_2_BIT_5_REG 0x19c8 162 #define RESULT_CONTROL_PUP_2_BIT_6_REG 0x19cc 163 #define RESULT_CONTROL_PUP_2_BIT_7_REG 0x19f0 164 165 #define RESULT_CONTROL_PUP_3_BIT_0_REG 0x19f4 166 #define RESULT_CONTROL_PUP_3_BIT_1_REG 0x19f8 167 #define RESULT_CONTROL_PUP_3_BIT_2_REG 0x19fc 168 #define RESULT_CONTROL_PUP_3_BIT_3_REG 0x1a30 169 #define RESULT_CONTROL_PUP_3_BIT_4_REG 0x1a34 170 #define RESULT_CONTROL_PUP_3_BIT_5_REG 0x1a38 171 #define RESULT_CONTROL_PUP_3_BIT_6_REG 0x1a3c 172 #define RESULT_CONTROL_PUP_3_BIT_7_REG 0x1ab0 173 174 #define RESULT_CONTROL_PUP_4_BIT_0_REG 0x1ab4 175 #define RESULT_CONTROL_PUP_4_BIT_1_REG 0x1ab8 176 #define RESULT_CONTROL_PUP_4_BIT_2_REG 0x1abc 177 #define RESULT_CONTROL_PUP_4_BIT_3_REG 0x1ac0 178 #define RESULT_CONTROL_PUP_4_BIT_4_REG 0x1ac4 179 #define RESULT_CONTROL_PUP_4_BIT_5_REG 0x1ac8 180 #define RESULT_CONTROL_PUP_4_BIT_6_REG 0x1acc 181 #define RESULT_CONTROL_PUP_4_BIT_7_REG 0x1af0 182 183 /* CPU */ 184 #define REG_BOOTROM_ROUTINE_ADDR 0x182d0 185 #define REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS 12 186 187 /* Matrix enables DRAM modes (bus width/ECC) per boardId */ 188 #define TOPOLOGY_UPDATE_32BIT 0 189 #define TOPOLOGY_UPDATE_32BIT_ECC 1 190 #define TOPOLOGY_UPDATE_16BIT 2 191 #define TOPOLOGY_UPDATE_16BIT_ECC 3 192 #define TOPOLOGY_UPDATE_16BIT_ECC_PUP3 4 193 #define TOPOLOGY_UPDATE { \ 194 /* 32Bit, 32bit ECC, 16bit, 16bit ECC PUP4, 16bit ECC PUP3 */ \ 195 {1, 1, 1, 1, 1}, /* RD_NAS_68XX_ID */ \ 196 {1, 1, 1, 1, 1}, /* DB_68XX_ID */ \ 197 {1, 0, 1, 0, 1}, /* RD_AP_68XX_ID */ \ 198 {1, 0, 1, 0, 1}, /* DB_AP_68XX_ID */ \ 199 {1, 0, 1, 0, 1}, /* DB_GP_68XX_ID */ \ 200 {0, 0, 1, 1, 0}, /* DB_BP_6821_ID */ \ 201 {1, 1, 1, 1, 1} /* DB_AMC_6820_ID */ \ 202 }; 203 204 enum { 205 CPU_1066MHZ_DDR_400MHZ, 206 CPU_RESERVED_DDR_RESERVED0, 207 CPU_667MHZ_DDR_667MHZ, 208 CPU_800MHZ_DDR_800MHZ, 209 CPU_RESERVED_DDR_RESERVED1, 210 CPU_RESERVED_DDR_RESERVED2, 211 CPU_RESERVED_DDR_RESERVED3, 212 LAST_FREQ 213 }; 214 215 /* struct used for DLB configuration array */ 216 struct dlb_config { 217 u32 reg_addr; 218 u32 reg_data; 219 }; 220 221 #define ACTIVE_INTERFACE_MASK 0x1 222 223 extern u32 dmin_phy_reg_table[][2]; 224 extern u16 odt_slope[]; 225 extern u16 odt_intercept[]; 226 227 int mv_ddr_pre_training_soc_config(const char *ddr_type); 228 int mv_ddr_post_training_soc_config(const char *ddr_type); 229 void mv_ddr_mem_scrubbing(void); 230 u32 mv_ddr_init_freq_get(void); 231 void mv_ddr_odpg_enable(void); 232 void mv_ddr_odpg_disable(void); 233 void mv_ddr_odpg_done_clr(void); 234 int mv_ddr_is_odpg_done(u32 count); 235 void mv_ddr_training_enable(void); 236 int mv_ddr_is_training_done(u32 count, u32 *result); 237 u32 mv_ddr_dm_pad_get(void); 238 int mv_ddr_pre_training_fixup(void); 239 int mv_ddr_post_training_fixup(void); 240 int mv_ddr_manual_cal_do(void); 241 int ddr3_calc_mem_cs_size(u32 cs, uint64_t *cs_size); 242 243 #endif /* _MV_DDR_PLAT_H */ 244