1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> 4 */ 5 6 #ifndef _RESET_MANAGER_GEN5_H_ 7 #define _RESET_MANAGER_GEN5_H_ 8 9 #include <dt-bindings/reset/altr,rst-mgr.h> 10 11 void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h); 12 void socfpga_bridges_reset(int enable); 13 14 #define RSTMGR_GEN5_STATUS 0x00 15 #define RSTMGR_GEN5_CTRL 0x04 16 #define RSTMGR_GEN5_MPUMODRST 0x10 17 #define RSTMGR_GEN5_PERMODRST 0x14 18 #define RSTMGR_GEN5_PER2MODRST 0x18 19 #define RSTMGR_GEN5_BRGMODRST 0x1c 20 #define RSTMGR_GEN5_MISCMODRST 0x20 21 22 #define RSTMGR_CTRL RSTMGR_GEN5_CTRL 23 24 /* 25 * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows: 26 * 0 ... mpumodrst 27 * 1 ... permodrst 28 * 2 ... per2modrst 29 * 3 ... brgmodrst 30 * 4 ... miscmodrst 31 */ 32 #define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) 33 #define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) 34 #define RSTMGR_NAND RSTMGR_DEFINE(1, 4) 35 #define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) 36 #define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6) 37 #define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8) 38 #define RSTMGR_UART0 RSTMGR_DEFINE(1, 16) 39 #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18) 40 #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19) 41 #define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22) 42 #define RSTMGR_DMA RSTMGR_DEFINE(1, 28) 43 #define RSTMGR_SDR RSTMGR_DEFINE(1, 29) 44 45 #endif /* _RESET_MANAGER_GEN5_H_ */ 46