1 /* 2 * Copyright (c) 2019, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOCFPGA_RESETMANAGER_H 8 #define SOCFPGA_RESETMANAGER_H 9 10 #include "socfpga_plat_def.h" 11 12 13 /* Register Mapping */ 14 15 #define SOCFPGA_RSTMGR_STAT 0x000 16 #define SOCFPGA_RSTMGR_HDSKEN 0x010 17 #define SOCFPGA_RSTMGR_MPUMODRST 0x020 18 #define SOCFPGA_RSTMGR_PER0MODRST 0x024 19 #define SOCFPGA_RSTMGR_PER1MODRST 0x028 20 #define SOCFPGA_RSTMGR_BRGMODRST 0x02c 21 #define SOCFPGA_RSTMGR_COLDMODRST 0x034 22 #define SOCFPGA_RSTMGR_HDSKTIMEOUT 0x064 23 24 /* Field Mapping */ 25 26 #define RSTMGR_PER0MODRST_EMAC0 0x00000001 27 #define RSTMGR_PER0MODRST_EMAC1 0x00000002 28 #define RSTMGR_PER0MODRST_EMAC2 0x00000004 29 #define RSTMGR_PER0MODRST_USB0 0x00000008 30 #define RSTMGR_PER0MODRST_USB1 0x00000010 31 #define RSTMGR_PER0MODRST_NAND 0x00000020 32 #define RSTMGR_PER0MODRST_SDMMC 0x00000080 33 #define RSTMGR_PER0MODRST_EMAC0OCP 0x00000100 34 #define RSTMGR_PER0MODRST_EMAC1OCP 0x00000200 35 #define RSTMGR_PER0MODRST_EMAC2OCP 0x00000400 36 #define RSTMGR_PER0MODRST_USB0OCP 0x00000800 37 #define RSTMGR_PER0MODRST_USB1OCP 0x00001000 38 #define RSTMGR_PER0MODRST_NANDOCP 0x00002000 39 #define RSTMGR_PER0MODRST_SDMMCOCP 0x00008000 40 #define RSTMGR_PER0MODRST_DMA 0x00010000 41 #define RSTMGR_PER0MODRST_SPIM0 0x00020000 42 #define RSTMGR_PER0MODRST_SPIM1 0x00040000 43 #define RSTMGR_PER0MODRST_SPIS0 0x00080000 44 #define RSTMGR_PER0MODRST_SPIS1 0x00100000 45 #define RSTMGR_PER0MODRST_DMAOCP 0x00200000 46 #define RSTMGR_PER0MODRST_EMACPTP 0x00400000 47 #define RSTMGR_PER0MODRST_DMAIF0 0x01000000 48 #define RSTMGR_PER0MODRST_DMAIF1 0x02000000 49 #define RSTMGR_PER0MODRST_DMAIF2 0x04000000 50 #define RSTMGR_PER0MODRST_DMAIF3 0x08000000 51 #define RSTMGR_PER0MODRST_DMAIF4 0x10000000 52 #define RSTMGR_PER0MODRST_DMAIF5 0x20000000 53 #define RSTMGR_PER0MODRST_DMAIF6 0x40000000 54 #define RSTMGR_PER0MODRST_DMAIF7 0x80000000 55 56 #define RSTMGR_PER1MODRST_WATCHDOG0 0x00000001 57 #define RSTMGR_PER1MODRST_WATCHDOG1 0x00000002 58 #define RSTMGR_PER1MODRST_WATCHDOG2 0x00000004 59 #define RSTMGR_PER1MODRST_WATCHDOG3 0x00000008 60 #define RSTMGR_PER1MODRST_L4SYSTIMER0 0x00000010 61 #define RSTMGR_PER1MODRST_L4SYSTIMER1 0x00000020 62 #define RSTMGR_PER1MODRST_SPTIMER0 0x00000040 63 #define RSTMGR_PER1MODRST_SPTIMER1 0x00000080 64 #define RSTMGR_PER1MODRST_I2C0 0x00000100 65 #define RSTMGR_PER1MODRST_I2C1 0x00000200 66 #define RSTMGR_PER1MODRST_I2C2 0x00000400 67 #define RSTMGR_PER1MODRST_I2C3 0x00000800 68 #define RSTMGR_PER1MODRST_I2C4 0x00001000 69 #define RSTMGR_PER1MODRST_UART0 0x00010000 70 #define RSTMGR_PER1MODRST_UART1 0x00020000 71 #define RSTMGR_PER1MODRST_GPIO0 0x01000000 72 #define RSTMGR_PER1MODRST_GPIO1 0x02000000 73 74 #define RSTMGR_HDSKEN_FPGAHSEN 0x00000004 75 #define RSTMGR_HDSKEN_ETRSTALLEN 0x00000008 76 #define RSTMGR_HDSKEN_L2FLUSHEN 0x00000100 77 #define RSTMGR_HDSKEN_L3NOC_DBG 0x00010000 78 #define RSTMGR_HDSKEN_DEBUG_L3NOC 0x00020000 79 #define RSTMGR_HDSKEN_SDRSELFREFEN 0x00000001 80 81 #define RSTMGR_BRGMODRST_SOC2FPGA 0x1 82 #define RSTMGR_BRGMODRST_LWHPS2FPGA 0x2 83 #define RSTMGR_BRGMODRST_FPGA2SOC 0x4 84 #define RSTMGR_BRGMODRST_F2SSDRAM1 0x10 85 #define RSTMGR_BRGMODRST_F2SSDRAM2 0x20 86 #define RSTMGR_BRGMODRST_MPFE 0x40 87 #define RSTMGR_BRGMODRST_DDRSCH 0x40 88 89 /* Definitions */ 90 91 #define RSTMGR_L2_MODRST 0x0100 92 #define RSTMGR_HDSKEN_SET 0x010D 93 94 /* Macros */ 95 96 #define SOCFPGA_RSTMGR(_reg) (SOCFPGA_RSTMGR_REG_BASE \ 97 + (SOCFPGA_RSTMGR_##_reg)) 98 #define RSTMGR_FIELD(_reg, _field) (RSTMGR_##_reg##MODRST_##_field) 99 100 /* Function Declarations */ 101 102 void deassert_peripheral_reset(void); 103 void config_hps_hs_before_warm_reset(void); 104 105 int socfpga_bridges_enable(void); 106 int socfpga_bridges_disable(void); 107 108 #endif /* SOCFPGA_RESETMANAGER_H */ 109