1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /********************************************************************** 3 * Copyright (C) 2012-2018 Cadence Design Systems, Inc. 4 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ 5 ********************************************************************** 6 * Cadence Core Driver for LPDDR4. 7 ********************************************************************** 8 */ 9 10 #ifndef LPDDR4_PRIV_H 11 #define LPDDR4_PRIV_H 12 13 #define PRODUCT_ID (0x1046U) 14 #define VERSION_0 (0x54d5da40U) 15 #define VERSION_1 (0xc1865a1U) 16 17 #define LPDDR4_BIT_MASK (0x1U) 18 #define BYTE_MASK (0xffU) 19 #define NIBBLE_MASK (0xfU) 20 21 #define WORD_SHIFT (32U) 22 #define WORD_MASK (0xffffffffU) 23 #define SLICE_WIDTH (0x100) 24 /* Number of Data slices */ 25 #define DSLICE_NUM (4U) 26 /*Number of Address Slices */ 27 #define ASLICE_NUM (1U) 28 29 /* Number of accessible registers in each slice */ 30 #define DSLICE0_REG_COUNT (140U) 31 #define DSLICE1_REG_COUNT (140U) 32 #define DSLICE2_REG_COUNT (140U) 33 #define DSLICE3_REG_COUNT (140U) 34 #define ASLICE0_REG_COUNT (52U) 35 #define PHY_CORE_REG_COUNT (140U) 36 37 #define CTL_OFFSET 0 38 #define PI_OFFSET (((uint32_t)1) << 11) 39 #define PHY_OFFSET (((uint32_t)1) << 12) 40 41 /* BIT[17] on INT_MASK_1 register. */ 42 #define CTL_INT_MASK_ALL ((uint32_t)LPDDR4_LOR_BITS - WORD_SHIFT) 43 44 /* Init Error information bits */ 45 #define PLL_READY (0x3U) 46 #define IO_CALIB_DONE ((uint32_t)0x1U << 23U) 47 #define IO_CALIB_FIELD ((uint32_t)NIBBLE_MASK << 28U) 48 #define IO_CALIB_STATE ((uint32_t)0xBU << 28U) 49 #define RX_CAL_DONE ((uint32_t)LPDDR4_BIT_MASK << 4U) 50 #define CA_TRAIN_RL (((uint32_t)LPDDR4_BIT_MASK << 5U) | \ 51 ((uint32_t)LPDDR4_BIT_MASK << 4U)) 52 #define WR_LVL_STATE (((uint32_t)NIBBLE_MASK) << 13U) 53 #define GATE_LVL_ERROR_FIELDS (((uint32_t)LPDDR4_BIT_MASK << 7U) | \ 54 ((uint32_t)LPDDR4_BIT_MASK << 6U)) 55 #define READ_LVL_ERROR_FIELDS ((((uint32_t)NIBBLE_MASK) << 28U) | \ 56 (((uint32_t)BYTE_MASK) << 16U)) 57 #define DQ_LVL_STATUS (((uint32_t)LPDDR4_BIT_MASK << 26U) | \ 58 (((uint32_t)BYTE_MASK) << 18U)) 59 60 #endif /* LPDDR4_PRIV_H */ 61