1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __ASM_ARCH_LS102XA_IMMAP_H_ 7 #define __ASM_ARCH_LS102XA_IMMAP_H_ 8 #include <fsl_immap.h> 9 10 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) 11 #define SVR_MIN(svr) (((svr) >> 0) & 0xf) 12 #define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff) 13 #define IS_E_PROCESSOR(svr) (svr & 0x80000) 14 #define IS_SVR_REV(svr, maj, min) \ 15 ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min)) 16 17 #define SOC_VER_SLS1020 0x00 18 #define SOC_VER_LS1020 0x10 19 #define SOC_VER_LS1021 0x11 20 #define SOC_VER_LS1022 0x12 21 22 #define SOC_MAJOR_VER_1_0 0x1 23 #define SOC_MAJOR_VER_2_0 0x2 24 25 #define CCSR_BRR_OFFSET 0xe4 26 #define CCSR_SCRATCHRW1_OFFSET 0x200 27 28 #define RCWSR0_SYS_PLL_RAT_SHIFT 25 29 #define RCWSR0_SYS_PLL_RAT_MASK 0x1f 30 #define RCWSR0_MEM_PLL_RAT_SHIFT 16 31 #define RCWSR0_MEM_PLL_RAT_MASK 0x3f 32 33 #define RCWSR4_SRDS1_PRTCL_SHIFT 24 34 #define RCWSR4_SRDS1_PRTCL_MASK 0xff000000 35 36 #define TIMER_COMP_VAL 0xffffffffffffffffull 37 #define ARCH_TIMER_CTRL_ENABLE (1 << 0) 38 #define SYS_COUNTER_CTRL_ENABLE (1 << 24) 39 40 #define DCFG_CCSR_PORSR1_RCW_MASK 0xff800000 41 #define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x24800000 42 43 #define DCFG_DCSR_PORCR1 0 44 45 /* 46 * Define default values for some CCSR macros to make header files cleaner 47 * 48 * To completely disable CCSR relocation in a board header file, define 49 * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS 50 * to a value that is the same as CONFIG_SYS_CCSRBAR. 51 */ 52 53 #ifdef CONFIG_SYS_CCSRBAR_PHYS 54 #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly." 55 #endif 56 57 #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE 58 #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH 59 #undef CONFIG_SYS_CCSRBAR_PHYS_LOW 60 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 61 #endif 62 63 #ifndef CONFIG_SYS_CCSRBAR 64 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR 65 #endif 66 67 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH 68 #ifdef CONFIG_PHYS_64BIT 69 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf 70 #else 71 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 72 #endif 73 #endif 74 75 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW 76 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR 77 #endif 78 79 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ 80 CONFIG_SYS_CCSRBAR_PHYS_LOW) 81 82 struct sys_info { 83 unsigned long freq_processor[CONFIG_MAX_CPUS]; 84 unsigned long freq_systembus; 85 unsigned long freq_ddrbus; 86 unsigned long freq_localbus; 87 }; 88 89 #define CCSR_DEVDISR1_QE 0x00000001 90 91 /* Device Configuration and Pin Control */ 92 struct ccsr_gur { 93 u32 porsr1; /* POR status 1 */ 94 u32 porsr2; /* POR status 2 */ 95 u8 res_008[0x20-0x8]; 96 u32 gpporcr1; /* General-purpose POR configuration */ 97 u32 gpporcr2; 98 u32 dcfg_fusesr; /* Fuse status register */ 99 u8 res_02c[0x70-0x2c]; 100 u32 devdisr; /* Device disable control */ 101 u32 devdisr2; /* Device disable control 2 */ 102 u32 devdisr3; /* Device disable control 3 */ 103 u32 devdisr4; /* Device disable control 4 */ 104 u32 devdisr5; /* Device disable control 5 */ 105 u8 res_084[0x94-0x84]; 106 u32 coredisru; /* uppper portion for support of 64 cores */ 107 u32 coredisrl; /* lower portion for support of 64 cores */ 108 u8 res_09c[0xa4-0x9c]; 109 u32 svr; /* System version */ 110 u8 res_0a8[0xb0-0xa8]; 111 u32 rstcr; /* Reset control */ 112 u32 rstrqpblsr; /* Reset request preboot loader status */ 113 u8 res_0b8[0xc0-0xb8]; 114 u32 rstrqmr1; /* Reset request mask */ 115 u8 res_0c4[0xc8-0xc4]; 116 u32 rstrqsr1; /* Reset request status */ 117 u8 res_0cc[0xd4-0xcc]; 118 u32 rstrqwdtmrl; /* Reset request WDT mask */ 119 u8 res_0d8[0xdc-0xd8]; 120 u32 rstrqwdtsrl; /* Reset request WDT status */ 121 u8 res_0e0[0xe4-0xe0]; 122 u32 brrl; /* Boot release */ 123 u8 res_0e8[0x100-0xe8]; 124 u32 rcwsr[16]; /* Reset control word status */ 125 #define RCW_SB_EN_REG_INDEX 7 126 #define RCW_SB_EN_MASK 0x00200000 127 u8 res_140[0x200-0x140]; 128 u32 scratchrw[4]; /* Scratch Read/Write */ 129 u8 res_210[0x300-0x210]; 130 u32 scratchw1r[4]; /* Scratch Read (Write once) */ 131 u8 res_310[0x400-0x310]; 132 u32 crstsr; 133 u8 res_404[0x550-0x404]; 134 u32 sataliodnr; 135 u8 res_554[0x604-0x554]; 136 u32 pamubypenr; 137 u32 dmacr1; 138 u8 res_60c[0x740-0x60c]; /* add more registers when needed */ 139 u32 tp_ityp[64]; /* Topology Initiator Type Register */ 140 struct { 141 u32 upper; 142 u32 lower; 143 } tp_cluster[1]; /* Core Cluster n Topology Register */ 144 u8 res_848[0xe60-0x848]; 145 u32 ddrclkdr; 146 u8 res_e60[0xe68-0xe64]; 147 u32 ifcclkdr; 148 u8 res_e68[0xe80-0xe6c]; 149 u32 sdhcpcr; 150 }; 151 152 #define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00 153 #define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 154 #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 155 #define SCFG_ETSECCMCR_GE0_CLK125 0x00000000 156 #define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 157 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 158 #define SCFG_QSPI_CLKSEL 0x50100000 159 #define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 160 #define SCFG_SNPCNFGCR_DCU_RD_WR 0x03000000 161 #define SCFG_SNPCNFGCR_SATA_RD_WR 0x00c00000 162 #define SCFG_SNPCNFGCR_USB3_RD_WR 0x00300000 163 #define SCFG_SNPCNFGCR_DBG_RD_WR 0x000c0000 164 #define SCFG_SNPCNFGCR_EDMA_SNP 0x00020000 165 #define SCFG_ENDIANCR_LE 0x80000000 166 #define SCFG_DPSLPCR_WDRR_EN 0x00000001 167 #define SCFG_PMCINTECR_LPUART 0x40000000 168 #define SCFG_PMCINTECR_FTM 0x20000000 169 #define SCFG_PMCINTECR_GPIO 0x10000000 170 #define SCFG_PMCINTECR_IRQ0 0x08000000 171 #define SCFG_PMCINTECR_IRQ1 0x04000000 172 #define SCFG_PMCINTECR_ETSECRXG0 0x00800000 173 #define SCFG_PMCINTECR_ETSECRXG1 0x00400000 174 #define SCFG_PMCINTECR_ETSECERRG0 0x00080000 175 #define SCFG_PMCINTECR_ETSECERRG1 0x00040000 176 #define SCFG_CLUSTERPMCR_WFIL2EN 0x80000000 177 178 #define SCFG_BASE 0x01570000 179 #define SCFG_USB3PRM1CR 0x070 180 #define SCFG_USB_TXVREFTUNE 0x9 181 #define SCFG_USB_SQRXTUNE_MASK 0x7 182 #define SCFG_USB3PRM2CR 0x074 183 #define SCFG_USB_PCSTXSWINGFULL_MASK 0x0000FE00 184 #define SCFG_USB_PCSTXSWINGFULL_VAL 0x00008E00 185 186 #define USB_PHY_BASE 0x08510000 187 #define USB_PHY_RX_OVRD_IN_HI 0x200c 188 #define USB_PHY_RX_EQ_VAL_1 0x0000 189 #define USB_PHY_RX_EQ_VAL_2 0x8000 190 #define USB_PHY_RX_EQ_VAL_3 0x8004 191 #define USB_PHY_RX_EQ_VAL_4 0x800C 192 193 /* Supplemental Configuration Unit */ 194 struct ccsr_scfg { 195 u32 dpslpcr; 196 u32 resv0[2]; 197 u32 etsecclkdpslpcr; 198 u32 resv1[5]; 199 u32 fuseovrdcr; 200 u32 pixclkcr; 201 u32 resv2[5]; 202 u32 spimsicr; 203 u32 resv3[6]; 204 u32 pex1pmwrcr; 205 u32 pex1pmrdsr; 206 u32 resv4[3]; 207 u32 usb3prm1cr; 208 u32 usb4prm2cr; 209 u32 pex1rdmsgpldlsbsr; 210 u32 pex1rdmsgpldmsbsr; 211 u32 pex2rdmsgpldlsbsr; 212 u32 pex2rdmsgpldmsbsr; 213 u32 pex1rdmmsgrqsr; 214 u32 pex2rdmmsgrqsr; 215 u32 spimsiclrcr; 216 u32 pexmscportsr[2]; 217 u32 pex2pmwrcr; 218 u32 resv5[24]; 219 u32 mac1_streamid; 220 u32 mac2_streamid; 221 u32 mac3_streamid; 222 u32 pex1_streamid; 223 u32 pex2_streamid; 224 u32 dma_streamid; 225 u32 sata_streamid; 226 u32 usb3_streamid; 227 u32 qe_streamid; 228 u32 sdhc_streamid; 229 u32 adma_streamid; 230 u32 letechsftrstcr; 231 u32 core0_sft_rst; 232 u32 core1_sft_rst; 233 u32 resv6[1]; 234 u32 usb_hi_addr; 235 u32 etsecclkadjcr; 236 u32 sai_clk; 237 u32 resv7[1]; 238 u32 dcu_streamid; 239 u32 usb2_streamid; 240 u32 ftm_reset; 241 u32 altcbar; 242 u32 qspi_cfg; 243 u32 pmcintecr; 244 u32 pmcintlecr; 245 u32 pmcintsr; 246 u32 qos1; 247 u32 qos2; 248 u32 qos3; 249 u32 cci_cfg; 250 u32 endiancr; 251 u32 etsecdmamcr; 252 u32 usb3prm3cr; 253 u32 resv9[1]; 254 u32 debug_streamid; 255 u32 resv10[5]; 256 u32 snpcnfgcr; 257 u32 hrstcr; 258 u32 intpcr; 259 u32 resv12[20]; 260 u32 scfgrevcr; 261 u32 coresrencr; 262 u32 pex2pmrdsr; 263 u32 eddrtqcfg; 264 u32 ddrc2cr; 265 u32 ddrc3cr; 266 u32 ddrc4cr; 267 u32 ddrgcr; 268 u32 resv13[120]; 269 u32 qeioclkcr; 270 u32 etsecmcr; 271 u32 sdhciovserlcr; 272 u32 resv14[61]; 273 u32 sparecr[8]; 274 u32 resv15[248]; 275 u32 core0sftrstsr; 276 u32 clusterpmcr; 277 }; 278 279 /* Clocking */ 280 struct ccsr_clk { 281 struct { 282 u32 clkcncsr; /* core cluster n clock control status */ 283 u8 res_004[0x1c]; 284 } clkcsr[2]; 285 u8 res_040[0x7c0]; /* 0x100 */ 286 struct { 287 u32 pllcngsr; 288 u8 res_804[0x1c]; 289 } pllcgsr[2]; 290 u8 res_840[0x1c0]; 291 u32 clkpcsr; /* 0xa00 Platform clock domain control/status */ 292 u8 res_a04[0x1fc]; 293 u32 pllpgsr; /* 0xc00 Platform PLL General Status */ 294 u8 res_c04[0x1c]; 295 u32 plldgsr; /* 0xc20 DDR PLL General Status */ 296 u8 res_c24[0x3dc]; 297 }; 298 299 /* System Counter */ 300 struct sctr_regs { 301 u32 cntcr; 302 u32 cntsr; 303 u32 cntcv1; 304 u32 cntcv2; 305 u32 resv1[4]; 306 u32 cntfid0; 307 u32 cntfid1; 308 u32 resv2[1002]; 309 u32 counterid[12]; 310 }; 311 312 #define MAX_SERDES 1 313 #define SRDS_MAX_LANES 4 314 #define SRDS_MAX_BANK 2 315 316 #define SRDS_RSTCTL_RST 0x80000000 317 #define SRDS_RSTCTL_RSTDONE 0x40000000 318 #define SRDS_RSTCTL_RSTERR 0x20000000 319 #define SRDS_RSTCTL_SWRST 0x10000000 320 #define SRDS_RSTCTL_SDEN 0x00000020 321 #define SRDS_RSTCTL_SDRST_B 0x00000040 322 #define SRDS_RSTCTL_PLLRST_B 0x00000080 323 #define SRDS_PLLCR0_POFF 0x80000000 324 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 325 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 326 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 327 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 328 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 329 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 330 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 331 #define SRDS_PLLCR0_PLL_LCK 0x00800000 332 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 333 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 334 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 335 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 336 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 337 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 338 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 339 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 340 341 struct ccsr_serdes { 342 struct { 343 u32 rstctl; /* Reset Control Register */ 344 345 u32 pllcr0; /* PLL Control Register 0 */ 346 347 u32 pllcr1; /* PLL Control Register 1 */ 348 u32 res_0c; /* 0x00c */ 349 u32 pllcr3; 350 u32 pllcr4; 351 u8 res_18[0x20-0x18]; 352 } bank[2]; 353 u8 res_40[0x90-0x40]; 354 u32 srdstcalcr; /* 0x90 TX Calibration Control */ 355 u8 res_94[0xa0-0x94]; 356 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ 357 u8 res_a4[0xb0-0xa4]; 358 u32 srdsgr0; /* 0xb0 General Register 0 */ 359 u8 res_b4[0xe0-0xb4]; 360 u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */ 361 u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */ 362 u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */ 363 u32 srdspccr3; /* 0xec Protocol Converter Config 3 */ 364 u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */ 365 u8 res_f4[0x100-0xf4]; 366 struct { 367 u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */ 368 u8 res_104[0x120-0x104]; 369 } srdslnpssr[4]; 370 u8 res_180[0x300-0x180]; 371 u32 srdspexeqcr; 372 u32 srdspexeqpcr[11]; 373 u8 res_330[0x400-0x330]; 374 u32 srdspexapcr; 375 u8 res_404[0x440-0x404]; 376 u32 srdspexbpcr; 377 u8 res_444[0x800-0x444]; 378 struct { 379 u32 gcr0; /* 0x800 General Control Register 0 */ 380 u32 gcr1; /* 0x804 General Control Register 1 */ 381 u32 gcr2; /* 0x808 General Control Register 2 */ 382 u32 sscr0; 383 u32 recr0; /* 0x810 Receive Equalization Control */ 384 u32 recr1; 385 u32 tecr0; /* 0x818 Transmit Equalization Control */ 386 u32 sscr1; 387 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ 388 u8 res_824[0x83c-0x824]; 389 u32 tcsr3; 390 } lane[4]; /* Lane A, B, C, D, E, F, G, H */ 391 u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ 392 }; 393 394 #define RCPM_POWMGTCSR 0x130 395 #define RCPM_POWMGTCSR_SERDES_PW 0x80000000 396 #define RCPM_POWMGTCSR_LPM20_REQ 0x00100000 397 #define RCPM_POWMGTCSR_LPM20_ST 0x00000200 398 #define RCPM_POWMGTCSR_P_LPM20_ST 0x00000100 399 #define RCPM_IPPDEXPCR0 0x140 400 #define RCPM_IPPDEXPCR0_ETSEC 0x80000000 401 #define RCPM_IPPDEXPCR0_GPIO 0x00000040 402 #define RCPM_IPPDEXPCR1 0x144 403 #define RCPM_IPPDEXPCR1_LPUART 0x40000000 404 #define RCPM_IPPDEXPCR1_FLEXTIMER 0x20000000 405 #define RCPM_IPPDEXPCR1_OCRAM1 0x10000000 406 #define RCPM_NFIQOUTR 0x15c 407 #define RCPM_NIRQOUTR 0x16c 408 #define RCPM_DSIMSKR 0x18c 409 #define RCPM_CLPCL10SETR 0x1c4 410 #define RCPM_CLPCL10SETR_C0 0x00000001 411 412 struct ccsr_rcpm { 413 u8 rev1[0x4c]; 414 u32 twaitsr; 415 u8 rev2[0xe0]; 416 u32 powmgtcsr; 417 u8 rev3[0xc]; 418 u32 ippdexpcr0; 419 u32 ippdexpcr1; 420 u8 rev4[0x14]; 421 u32 nfiqoutr; 422 u8 rev5[0xc]; 423 u32 nirqoutr; 424 u8 rev6[0x1c]; 425 u32 dsimskr; 426 u8 rev7[0x34]; 427 u32 clpcl10setr; 428 }; 429 430 uint get_svr(void); 431 432 #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */ 433