1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /*
3  * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved.
4  * Copyright (c) 2019, Linaro Limited
5  */
6 
7 #ifndef SCMI_MSG_CLOCK_H
8 #define SCMI_MSG_CLOCK_H
9 
10 #include <stdint.h>
11 
12 #include <lib/utils_def.h>
13 
14 #define SCMI_PROTOCOL_VERSION_CLOCK	0x20000U
15 
16 /*
17  * Identifiers of the SCMI Clock Management Protocol commands
18  */
19 enum scmi_clock_command_id {
20 	SCMI_CLOCK_ATTRIBUTES = 0x003,
21 	SCMI_CLOCK_DESCRIBE_RATES = 0x004,
22 	SCMI_CLOCK_RATE_SET = 0x005,
23 	SCMI_CLOCK_RATE_GET = 0x006,
24 	SCMI_CLOCK_CONFIG_SET = 0x007,
25 };
26 
27 /* Protocol attributes */
28 #define SCMI_CLOCK_CLOCK_COUNT_MASK			GENMASK(15, 0)
29 #define SCMI_CLOCK_MAX_PENDING_TRANSITIONS_MASK		GENMASK(23, 16)
30 
31 #define SCMI_CLOCK_PROTOCOL_ATTRIBUTES(_max_pending, _clk_count) \
32 	((((_max_pending) << 16) & SCMI_CLOCK_MAX_PENDING_TRANSITIONS_MASK) | \
33 	 (((_clk_count) & SCMI_CLOCK_CLOCK_COUNT_MASK)))
34 
35 struct scmi_clock_attributes_a2p {
36 	uint32_t clock_id;
37 };
38 
39 #define SCMI_CLOCK_NAME_LENGTH_MAX	16U
40 
41 struct scmi_clock_attributes_p2a {
42 	int32_t status;
43 	uint32_t attributes;
44 	char clock_name[SCMI_CLOCK_NAME_LENGTH_MAX];
45 };
46 
47 /*
48  * Clock Rate Get
49  */
50 
51 struct scmi_clock_rate_get_a2p {
52 	uint32_t clock_id;
53 };
54 
55 struct scmi_clock_rate_get_p2a {
56 	int32_t status;
57 	uint32_t rate[2];
58 };
59 
60 /*
61  * Clock Rate Set
62  */
63 
64 /* If set, set the new clock rate asynchronously */
65 #define SCMI_CLOCK_RATE_SET_ASYNC_POS			0
66 /* If set, do not send a delayed asynchronous response */
67 #define SCMI_CLOCK_RATE_SET_NO_DELAYED_RESPONSE_POS	1
68 /* Round up, if set, otherwise round down */
69 #define SCMI_CLOCK_RATE_SET_ROUND_UP_POS		2
70 /* If set, the platform chooses the appropriate rounding mode */
71 #define SCMI_CLOCK_RATE_SET_ROUND_AUTO_POS		3
72 
73 #define SCMI_CLOCK_RATE_SET_ASYNC_MASK \
74 		BIT(SCMI_CLOCK_RATE_SET_ASYNC_POS)
75 #define SCMI_CLOCK_RATE_SET_NO_DELAYED_RESPONSE_MASK \
76 		BIT(SCMI_CLOCK_RATE_SET_NO_DELAYED_RESPONSE_POS)
77 #define SCMI_CLOCK_RATE_SET_ROUND_UP_MASK \
78 		BIT(SCMI_CLOCK_RATE_SET_ROUND_UP_POS)
79 #define SCMI_CLOCK_RATE_SET_ROUND_AUTO_MASK \
80 		BIT(SCMI_CLOCK_RATE_SET_ROUND_AUTO_POS)
81 
82 struct scmi_clock_rate_set_a2p {
83 	uint32_t flags;
84 	uint32_t clock_id;
85 	uint32_t rate[2];
86 };
87 
88 struct scmi_clock_rate_set_p2a {
89 	int32_t status;
90 };
91 
92 /*
93  * Clock Config Set
94  */
95 
96 #define SCMI_CLOCK_CONFIG_SET_ENABLE_POS	0
97 
98 #define SCMI_CLOCK_CONFIG_SET_ENABLE_MASK \
99 	BIT(SCMI_CLOCK_CONFIG_SET_ENABLE_POS)
100 
101 struct scmi_clock_config_set_a2p {
102 	uint32_t clock_id;
103 	uint32_t attributes;
104 };
105 
106 struct scmi_clock_config_set_p2a {
107 	int32_t status;
108 };
109 
110 /*
111  * Clock Describe Rates
112  */
113 
114 #define SCMI_CLOCK_RATE_FORMAT_RANGE			1U
115 #define SCMI_CLOCK_RATE_FORMAT_LIST			0U
116 
117 #define SCMI_CLOCK_DESCRIBE_RATES_REMAINING_MASK	GENMASK_32(31, 16)
118 #define SCMI_CLOCK_DESCRIBE_RATES_REMAINING_POS		16
119 
120 #define SCMI_CLOCK_DESCRIBE_RATES_FORMAT_MASK		BIT(12)
121 #define SCMI_CLOCK_DESCRIBE_RATES_FORMAT_POS		12
122 
123 #define SCMI_CLOCK_DESCRIBE_RATES_COUNT_MASK		GENMASK_32(11, 0)
124 
125 #define SCMI_CLOCK_DESCRIBE_RATES_NUM_RATES_FLAGS(_count, _fmt, _rem_rates) \
126 	( \
127 		((_count) & SCMI_CLOCK_DESCRIBE_RATES_COUNT_MASK) | \
128 		(((_rem_rates) << SCMI_CLOCK_DESCRIBE_RATES_REMAINING_POS) & \
129 		 SCMI_CLOCK_DESCRIBE_RATES_REMAINING_MASK) | \
130 		(((_fmt) << SCMI_CLOCK_DESCRIBE_RATES_FORMAT_POS) & \
131 		 SCMI_CLOCK_DESCRIBE_RATES_FORMAT_MASK) \
132 	)
133 
134 struct scmi_clock_rate {
135 	uint32_t low;
136 	uint32_t high;
137 };
138 
139 struct scmi_clock_describe_rates_a2p {
140 	uint32_t clock_id;
141 	uint32_t rate_index;
142 };
143 
144 struct scmi_clock_describe_rates_p2a {
145 	int32_t status;
146 	uint32_t num_rates_flags;
147 	struct scmi_clock_rate rates[];
148 };
149 
150 #endif /* SCMI_MSG_CLOCK_H */
151