1 /* 2 * xen/include/asm-arm/scif-uart.h 3 * 4 * Common constant definition between early printk and the UART driver 5 * for the SCIF(A) compatible UART. 6 * 7 * Oleksandr Tyshchenko <oleksandr.tyshchenko@globallogic.com> 8 * Copyright (C) 2014, Globallogic. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 */ 20 21 #ifndef __ASM_ARM_SCIF_UART_H 22 #define __ASM_ARM_SCIF_UART_H 23 24 /* Register offsets (SCIF) */ 25 #define SCIF_SCSMR (0x00) /* Serial mode register */ 26 #define SCIF_SCBRR (0x04) /* Bit rate register */ 27 #define SCIF_SCSCR (0x08) /* Serial control register */ 28 #define SCIF_SCFTDR (0x0C) /* Transmit FIFO data register */ 29 #define SCIF_SCFSR (0x10) /* Serial status register */ 30 #define SCIF_SCFRDR (0x14) /* Receive FIFO data register */ 31 #define SCIF_SCFCR (0x18) /* FIFO control register */ 32 #define SCIF_SCFDR (0x1C) /* FIFO data count register */ 33 #define SCIF_SCSPTR (0x20) /* Serial port register */ 34 #define SCIF_SCLSR (0x24) /* Line status register */ 35 #define SCIF_DL (0x30) /* Frequency division register */ 36 #define SCIF_CKS (0x34) /* Clock Select register */ 37 38 /* Serial Control Register (SCSCR) */ 39 #define SCSCR_TIE (1 << 7) /* Transmit Interrupt Enable */ 40 #define SCSCR_RIE (1 << 6) /* Receive Interrupt Enable */ 41 #define SCSCR_TE (1 << 5) /* Transmit Enable */ 42 #define SCSCR_RE (1 << 4) /* Receive Enable */ 43 #define SCSCR_REIE (1 << 3) /* Receive Error Interrupt Enable */ 44 #define SCSCR_TOIE (1 << 2) /* Timeout Interrupt Enable */ 45 #define SCSCR_CKE1 (1 << 1) /* Clock Enable 1 */ 46 #define SCSCR_CKE0 (1 << 0) /* Clock Enable 0 */ 47 48 /* Serial Status Register (SCFSR) */ 49 #define SCFSR_ER (1 << 7) /* Receive Error */ 50 #define SCFSR_TEND (1 << 6) /* Transmission End */ 51 #define SCFSR_TDFE (1 << 5) /* Transmit FIFO Data Empty */ 52 #define SCFSR_BRK (1 << 4) /* Break Detect */ 53 #define SCFSR_FER (1 << 3) /* Framing Error */ 54 #define SCFSR_PER (1 << 2) /* Parity Error */ 55 #define SCFSR_RDF (1 << 1) /* Receive FIFO Data Full */ 56 #define SCFSR_DR (1 << 0) /* Receive Data Ready */ 57 58 /* Line Status Register (SCLSR) */ 59 #define SCLSR_TO (1 << 2) /* Timeout */ 60 #define SCLSR_ORER (1 << 0) /* Overrun Error */ 61 62 /* FIFO Control Register (SCFCR) */ 63 #define SCFCR_RTRG1 (1 << 7) /* Receive FIFO Data Count Trigger 1 */ 64 #define SCFCR_RTRG0 (1 << 6) /* Receive FIFO Data Count Trigger 0 */ 65 #define SCFCR_TTRG1 (1 << 5) /* Transmit FIFO Data Count Trigger 1 */ 66 #define SCFCR_TTRG0 (1 << 4) /* Transmit FIFO Data Count Trigger 0 */ 67 #define SCFCR_MCE (1 << 3) /* Modem Control Enable */ 68 #define SCFCR_TFRST (1 << 2) /* Transmit FIFO Data Register Reset */ 69 #define SCFCR_RFRST (1 << 1) /* Receive FIFO Data Register Reset */ 70 #define SCFCR_LOOP (1 << 0) /* Loopback Test */ 71 72 #define SCFCR_RTRG00 (0) 73 #define SCFCR_RTRG01 (SCFCR_RTRG0) 74 #define SCFCR_RTRG10 (SCFCR_RTRG1) 75 #define SCFCR_RTRG11 (SCFCR_RTRG1 | SCFCR_RTRG0) 76 77 #define SCFCR_TTRG00 (0) 78 #define SCFCR_TTRG01 (SCFCR_TTRG0) 79 #define SCFCR_TTRG10 (SCFCR_TTRG1) 80 #define SCFCR_TTRG11 (SCFCR_TTRG1 | SCFCR_TTRG0) 81 82 /* Register offsets (SCIFA) */ 83 #define SCIFA_SCASMR (0x00) /* Serial mode register */ 84 #define SCIFA_SCABRR (0x04) /* Bit rate register */ 85 #define SCIFA_SCASCR (0x08) /* Serial control register */ 86 #define SCIFA_SCATDSR (0x0C) /* Transmit data stop register */ 87 #define SCIFA_SCAFER (0x10) /* FIFO error count register */ 88 #define SCIFA_SCASSR (0x14) /* Serial status register */ 89 #define SCIFA_SCAFCR (0x18) /* FIFO control register */ 90 #define SCIFA_SCAFDR (0x1C) /* FIFO data count register */ 91 #define SCIFA_SCAFTDR (0x20) /* Transmit FIFO data register */ 92 #define SCIFA_SCAFRDR (0x24) /* Receive FIFO data register */ 93 #define SCIFA_SCAPCR (0x30) /* Serial port control register */ 94 #define SCIFA_SCAPDR (0x34) /* Serial port data register */ 95 96 /* Serial Control Register (SCASCR) */ 97 #define SCASCR_ERIE (1 << 10) /* Receive Error Interrupt Enable */ 98 #define SCASCR_BRIE (1 << 9) /* Break Interrupt Enable */ 99 #define SCASCR_DRIE (1 << 8) /* Receive Data Ready Interrupt Enable */ 100 #define SCASCR_TIE (1 << 7) /* Transmit Interrupt Enable */ 101 #define SCASCR_RIE (1 << 6) /* Receive Interrupt Enable */ 102 #define SCASCR_TE (1 << 5) /* Transmit Enable */ 103 #define SCASCR_RE (1 << 4) /* Receive Enable */ 104 #define SCASCR_CKE0 (1 << 0) /* Clock Enable 0 */ 105 106 /* Serial Status Register (SCASSR) */ 107 #define SCASSR_ORER (1 << 9) /* Overrun Error */ 108 #define SCASSR_TSF (1 << 8) /* Transmit Data Stop */ 109 #define SCASSR_ER (1 << 7) /* Receive Error */ 110 #define SCASSR_TEND (1 << 6) /* Transmission End */ 111 #define SCASSR_TDFE (1 << 5) /* Transmit FIFO Data Empty */ 112 #define SCASSR_BRK (1 << 4) /* Break Detect */ 113 #define SCASSR_FER (1 << 3) /* Framing Error */ 114 #define SCASSR_PER (1 << 2) /* Parity Error */ 115 #define SCASSR_RDF (1 << 1) /* Receive FIFO Data Full */ 116 #define SCASSR_DR (1 << 0) /* Receive Data Ready */ 117 118 #endif /* __ASM_ARM_SCIF_UART_H */ 119 120 /* 121 * Local variables: 122 * mode: C 123 * c-file-style: "BSD" 124 * c-basic-offset: 4 125 * indent-tabs-mode: nil 126 * End: 127 */ 128