1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (c) Aspeed Technology Inc. 4 */ 5 #ifndef _ASM_ARCH_SCU_AST2600_H 6 #define _ASM_ARCH_SCU_AST2600_H 7 8 #define SCU_UNLOCK_KEY 0x1688a8a8 9 10 #define SCU_CLKGATE1_EMMC BIT(27) 11 #define SCU_CLKGATE1_MAC2 BIT(21) 12 #define SCU_CLKGATE1_MAC1 BIT(20) 13 #define SCU_CLKGATE1_USB_HUB BIT(14) 14 #define SCU_CLKGATE1_USB_HOST2 BIT(7) 15 16 #define SCU_CLKGATE2_FSI BIT(30) 17 #define SCU_CLKGATE2_MAC4 BIT(21) 18 #define SCU_CLKGATE2_MAC3 BIT(20) 19 #define SCU_CLKGATE2_SDIO BIT(4) 20 21 #define SCU_DRAM_HDSHK_SOC_INIT BIT(7) 22 #define SCU_DRAM_HDSHK_RDY BIT(6) 23 24 #define SCU_CLKSRC1_ECC_RSA_DIV_MASK GENMASK(27, 26) 25 #define SCU_CLKSRC1_ECC_RSA_DIV_SHIFT 26 26 #define SCU_CLKSRC1_PCLK_DIV_MASK GENMASK(25, 23) 27 #define SCU_CLKSRC1_PCLK_DIV_SHIFT 23 28 #define SCU_CLKSRC1_BCLK_DIV_MASK GENMASK(22, 20) 29 #define SCU_CLKSRC1_BCLK_DIV_SHIFT 20 30 #define SCU_CLKSRC1_ECC_RSA BIT(19) 31 #define SCU_CLKSRC1_MAC_DIV_MASK GENMASK(18, 16) 32 #define SCU_CLKSRC1_MAC_DIV_SHIFT 16 33 #define SCU_CLKSRC1_EMMC_EN BIT(15) 34 #define SCU_CLKSRC1_EMMC_DIV_MASK GENMASK(14, 12) 35 #define SCU_CLKSRC1_EMMC_DIV_SHIFT 12 36 #define SCU_CLKSRC1_EMMC BIT(11) 37 38 #define SCU_CLKSRC2_RMII12 BIT(19) 39 #define SCU_CLKSRC2_RMII12_DIV_MASK GENMASK(18, 16) 40 #define SCU_CLKSRC2_RMII12_DIV_SHIFT 16 41 #define SCU_CLKSRC2_UART5 BIT(14) 42 43 #define SCU_CLKSRC4_SDIO_EN BIT(31) 44 #define SCU_CLKSRC4_SDIO_DIV_MASK GENMASK(30, 28) 45 #define SCU_CLKSRC4_SDIO_DIV_SHIFT 28 46 #define SCU_CLKSRC4_MAC_DIV_MASK GENMASK(26, 24) 47 #define SCU_CLKSRC4_MAC_DIV_SHIFT 24 48 #define SCU_CLKSRC4_RMII34_DIV_MASK GENMASK(18, 16) 49 #define SCU_CLKSRC4_RMII34_DIV_SHIFT 16 50 #define SCU_CLKSRC4_PCLK_DIV_MASK GENMASK(11, 9) 51 #define SCU_CLKSRC4_PCLK_DIV_SHIFT 9 52 #define SCU_CLKSRC4_SDIO BIT(8) 53 #define SCU_CLKSRC4_UART6 BIT(5) 54 #define SCU_CLKSRC4_UART4 BIT(3) 55 #define SCU_CLKSRC4_UART3 BIT(2) 56 #define SCU_CLKSRC4_UART2 BIT(1) 57 #define SCU_CLKSRC4_UART1 BIT(0) 58 59 #define SCU_CLKSRC5_UART13 BIT(12) 60 #define SCU_CLKSRC5_UART12 BIT(11) 61 #define SCU_CLKSRC5_UART11 BIT(10) 62 #define SCU_CLKSRC5_UART10 BIT(9) 63 #define SCU_CLKSRC5_UART9 BIT(8) 64 #define SCU_CLKSRC5_UART8 BIT(7) 65 #define SCU_CLKSRC5_UART7 BIT(6) 66 #define SCU_CLKSRC5_HUXCLK_MASK GENMASK(5, 3) 67 #define SCU_CLKSRC5_HUXCLK_SHIFT 3 68 #define SCU_CLKSRC5_UXCLK_MASK GENMASK(2, 0) 69 #define SCU_CLKSRC5_UXCLK_SHIFT 0 70 71 #define SCU_PINCTRL1_EMMC_MASK GENMASK(31, 24) 72 #define SCU_PINCTRL1_EMMC_SHIFT 24 73 74 #define SCU_PINCTRL16_MAC4_DRIVING_MASK GENMASK(3, 2) 75 #define SCU_PINCTRL16_MAC4_DRIVING_SHIFT 2 76 #define SCU_PINCTRL16_MAC3_DRIVING_MASK GENMASK(1, 0) 77 #define SCU_PINCTRL16_MAC3_DRIVING_SHIFT 0 78 79 #define SCU_HWSTRAP1_CPU_AXI_CLK_RATIO BIT(16) 80 #define SCU_HWSTRAP1_VGA_MEM_MASK GENMASK(14, 13) 81 #define SCU_HWSTRAP1_VGA_MEM_SHIFT 13 82 #define SCU_HWSTRAP1_AXI_AHB_CLK_RATIO_MASK GENMASK(12, 11) 83 #define SCU_HWSTRAP1_AXI_AHB_CLK_RATIO_SHIFT 11 84 #define SCU_HWSTRAP1_CPU_FREQ_MASK GENMASK(10, 8) 85 #define SCU_HWSTRAP1_CPU_FREQ_SHIFT 8 86 #define SCU_HWSTRAP1_MAC2_INTF BIT(7) 87 #define SCU_HWSTRAP1_MAC1_INTF BIT(6) 88 89 #define SCU_EFUSE_DIS_DP BIT(17) 90 #define SCU_EFUSE_DIS_VGA BIT(14) 91 #define SCU_EFUSE_DIS_PCIE_EP BIT(13) 92 #define SCU_EFUSE_DIS_USB BIT(12) 93 #define SCU_EFUSE_DIS_RVAS BIT(10) 94 #define SCU_EFUSE_DIS_VIDEO_DEC BIT(9) 95 #define SCU_EFUSE_DIS_VIDEO BIT(8) 96 #define SCU_EFUSE_DIS_PCIE_RC BIT(7) 97 #define SCU_EFUSE_DIS_CM3 BIT(6) 98 #define SCU_EFUSE_DIS_CA7 BIT(5) 99 100 #define SCU_PLL_RST BIT(25) 101 #define SCU_PLL_BYPASS BIT(24) 102 #define SCU_PLL_OFF BIT(23) 103 #define SCU_PLL_DIV_MASK GENMASK(22, 19) 104 #define SCU_PLL_DIV_SHIFT 19 105 #define SCU_PLL_DENUM_MASK GENMASK(18, 13) 106 #define SCU_PLL_DENUM_SHIFT 13 107 #define SCU_PLL_NUM_MASK GENMASK(12, 0) 108 #define SCU_PLL_NUM_SHIFT 0 109 110 #define SCU_UART_CLKGEN_N_MASK GENMASK(17, 8) 111 #define SCU_UART_CLKGEN_N_SHIFT 8 112 #define SCU_UART_CLKGEN_R_MASK GENMASK(7, 0) 113 #define SCU_UART_CLKGEN_R_SHIFT 0 114 115 #define SCU_HUART_CLKGEN_N_MASK GENMASK(17, 8) 116 #define SCU_HUART_CLKGEN_N_SHIFT 8 117 #define SCU_HUART_CLKGEN_R_MASK GENMASK(7, 0) 118 #define SCU_HUART_CLKGEN_R_SHIFT 0 119 120 #define SCU_MISC_CTRL1_UART5_DIV BIT(12) 121 122 #ifndef __ASSEMBLY__ 123 struct ast2600_scu { 124 uint32_t prot_key1; /* 0x000 */ 125 uint32_t chip_id1; /* 0x004 */ 126 uint32_t rsv_0x08; /* 0x008 */ 127 uint32_t rsv_0x0c; /* 0x00C */ 128 uint32_t prot_key2; /* 0x010 */ 129 uint32_t chip_id2; /* 0x014 */ 130 uint32_t rsv_0x18[10]; /* 0x018 ~ 0x03C */ 131 uint32_t modrst_ctrl1; /* 0x040 */ 132 uint32_t modrst_clr1; /* 0x044 */ 133 uint32_t rsv_0x48; /* 0x048 */ 134 uint32_t rsv_0x4C; /* 0x04C */ 135 uint32_t modrst_ctrl2; /* 0x050 */ 136 uint32_t modrst_clr2; /* 0x054 */ 137 uint32_t rsv_0x58; /* 0x058 */ 138 uint32_t rsv_0x5C; /* 0x05C */ 139 uint32_t extrst_sel1; /* 0x060 */ 140 uint32_t sysrst_sts1_1; /* 0x064 */ 141 uint32_t sysrst_sts1_2; /* 0x068 */ 142 uint32_t sysrst_sts1_3; /* 0x06C */ 143 uint32_t extrst_sel2; /* 0x070 */ 144 uint32_t sysrst_sts2_1; /* 0x074 */ 145 uint32_t sysrst_sts2_2; /* 0x078 */ 146 uint32_t stsrst_sts3_2; /* 0x07C */ 147 uint32_t clkgate_ctrl1; /* 0x080 */ 148 uint32_t clkgate_clr1; /* 0x084 */ 149 uint32_t rsv_0x88; /* 0x088 */ 150 uint32_t rsv_0x8C; /* 0x08C */ 151 uint32_t clkgate_ctrl2; /* 0x090 */ 152 uint32_t clkgate_clr2; /* 0x094 */ 153 uint32_t rsv_0x98[10]; /* 0x098 ~ 0x0BC */ 154 uint32_t misc_ctrl1; /* 0x0C0 */ 155 uint32_t misc_ctrl2; /* 0x0C4 */ 156 uint32_t debug_ctrl1; /* 0x0C8 */ 157 uint32_t rsv_0xCC; /* 0x0CC */ 158 uint32_t misc_ctrl3; /* 0x0D0 */ 159 uint32_t misc_ctrl4; /* 0x0D4 */ 160 uint32_t debug_ctrl2; /* 0x0D8 */ 161 uint32_t rsv_0xdc[9]; /* 0x0DC ~ 0x0FC */ 162 uint32_t dram_hdshk; /* 0x100 */ 163 uint32_t soc_scratch[3]; /* 0x104 ~ 0x10C */ 164 uint32_t rsv_0x110[4]; /* 0x110 ~ 0x11C*/ 165 uint32_t cpu_scratch_wp; /* 0x120 */ 166 uint32_t rsv_0x124[23]; /* 0x124 */ 167 uint32_t smp_boot[12]; /* 0x180 */ 168 uint32_t cpu_scratch[20]; /* 0x1b0 */ 169 uint32_t hpll; /* 0x200 */ 170 uint32_t hpll_ext; /* 0x204 */ 171 uint32_t rsv_0x208[2]; /* 0x208 ~ 0x20C */ 172 uint32_t apll; /* 0x210 */ 173 uint32_t apll_ext; /* 0x214 */ 174 uint32_t rsv_0x218[2]; /* 0x218 ~ 0x21C */ 175 uint32_t mpll; /* 0x220 */ 176 uint32_t mpll_ext; /* 0x224 */ 177 uint32_t rsv_0x228[6]; /* 0x228 ~ 0x23C */ 178 uint32_t epll; /* 0x240 */ 179 uint32_t epll_ext; /* 0x244 */ 180 uint32_t rsv_0x248[6]; /* 0x248 ~ 0x25C */ 181 uint32_t dpll; /* 0x260 */ 182 uint32_t dpll_ext; /* 0x264 */ 183 uint32_t rsv_0x268[38]; /* 0x268 ~ 0x2FC */ 184 uint32_t clksrc1; /* 0x300 */ 185 uint32_t clksrc2; /* 0x304 */ 186 uint32_t clksrc3; /* 0x308 */ 187 uint32_t rsv_0x30c; /* 0x30C */ 188 uint32_t clksrc4; /* 0x310 */ 189 uint32_t clksrc5; /* 0x314 */ 190 uint32_t rsv_0x318[2]; /* 0x318 ~ 0x31C */ 191 uint32_t freq_counter_ctrl1; /* 0x320 */ 192 uint32_t freq_counter_cmp1; /* 0x324 */ 193 uint32_t rsv_0x328[2]; /* 0x328 ~ 0x32C */ 194 uint32_t freq_counter_ctrl2; /* 0x330 */ 195 uint32_t freq_counter_cmp2; /* 0x334 */ 196 uint32_t uart_clkgen; /* 0x338 */ 197 uint32_t huart_clkgen; /* 0x33C */ 198 uint32_t mac12_clk_delay; /* 0x340 */ 199 uint32_t rsv_0x344; /* 0x344 */ 200 uint32_t mac12_clk_delay_100M; /* 0x348 */ 201 uint32_t mac12_clk_delay_10M; /* 0x34C */ 202 uint32_t mac34_clk_delay; /* 0x350 */ 203 uint32_t rsv_0x354; /* 0x354 */ 204 uint32_t mac34_clk_delay_100M; /* 0x358 */ 205 uint32_t mac34_clk_delay_10M; /* 0x35C */ 206 uint32_t clkduty_meas_ctrl; /* 0x360 */ 207 uint32_t clkduty1; /* 0x364 */ 208 uint32_t clkduty2; /* 0x368 */ 209 uint32_t clkduty_meas_res; /* 0x36C */ 210 uint32_t clkduty_meas_ctrl2; /* 0x370 */ 211 uint32_t clkduty3; /* 0x374 */ 212 uint32_t rsv_0x378[34]; /* 0x378 ~ 0x3FC */ 213 uint32_t pinmux1; /* 0x400 */ 214 uint32_t pinmux2; /* 0x404 */ 215 uint32_t rsv_0x408; /* 0x408 */ 216 uint32_t pinmux3; /* 0x40C */ 217 uint32_t pinmux4; /* 0x410 */ 218 uint32_t pinmux5; /* 0x414 */ 219 uint32_t pinmux6; /* 0x418 */ 220 uint32_t pinmux7; /* 0x41C */ 221 uint32_t rsv_0x420[4]; /* 0x420 ~ 0x42C */ 222 uint32_t pinmux8; /* 0x430 */ 223 uint32_t pinmux9; /* 0x434 */ 224 uint32_t pinmux10; /* 0x438 */ 225 uint32_t rsv_0x43c; /* 0x43C */ 226 uint32_t pinmux12; /* 0x440 */ 227 uint32_t pinmux13; /* 0x444 */ 228 uint32_t rsv_0x448[2]; /* 0x448 ~ 0x44C */ 229 uint32_t pinmux14; /* 0x450 */ 230 uint32_t pinmux15; /* 0x454 */ 231 uint32_t pinmux16; /* 0x458 */ 232 uint32_t rsv_0x45c[21]; /* 0x45C ~ 0x4AC */ 233 uint32_t pinmux17; /* 0x4B0 */ 234 uint32_t pinmux18; /* 0x4B4 */ 235 uint32_t pinmux19; /* 0x4B8 */ 236 uint32_t pinmux20; /* 0x4BC */ 237 uint32_t rsv_0x4c0[5]; /* 0x4C0 ~ 0x4D0 */ 238 uint32_t pinmux22; /* 0x4D4 */ 239 uint32_t pinmux23; /* 0x4D8 */ 240 uint32_t rsv_0x4dc[9]; /* 0x4DC ~ 0x4FC */ 241 uint32_t hwstrap1; /* 0x500 */ 242 uint32_t hwstrap_clr1; /* 0x504 */ 243 uint32_t hwstrap_prot1; /* 0x508 */ 244 uint32_t rsv_0x50c; /* 0x50C */ 245 uint32_t hwstrap2; /* 0x510 */ 246 uint32_t hwstrap_clr2; /* 0x514 */ 247 uint32_t hwstrap_prot2; /* 0x518 */ 248 uint32_t rsv_0x51c; /* 0x51C */ 249 uint32_t rng_ctrl; /* 0x520 */ 250 uint32_t rng_data; /* 0x524 */ 251 uint32_t rsv_0x528[6]; /* 0x528 ~ 0x53C */ 252 uint32_t pwr_save_wakeup_en1; /* 0x540 */ 253 uint32_t pwr_save_wakeup_ctrl1; /* 0x544 */ 254 uint32_t rsv_0x548[2]; /* 0x548 */ 255 uint32_t pwr_save_wakeup_en2; /* 0x550 */ 256 uint32_t pwr_save_wakeup_ctrl2; /* 0x554 */ 257 uint32_t rsv_0x558[2]; /* 0x558 */ 258 uint32_t intr1_ctrl_sts; /* 0x560 */ 259 uint32_t rsv_0x564[3]; /* 0x564 */ 260 uint32_t intr2_ctrl_sts; /* 0x570 */ 261 uint32_t rsv_0x574[7]; /* 0x574 ~ 0x58C */ 262 uint32_t otp_ctrl; /* 0x590 */ 263 uint32_t efuse; /* 0x594 */ 264 uint32_t rsv_0x598[6]; /* 0x598 */ 265 uint32_t chip_unique_id[8]; /* 0x5B0 */ 266 uint32_t rsv_0x5e0[8]; /* 0x5E0 ~ 0x5FC */ 267 uint32_t disgpio_in_pull_down0; /* 0x610 */ 268 uint32_t disgpio_in_pull_down1; /* 0x614 */ 269 uint32_t disgpio_in_pull_down2; /* 0x618 */ 270 uint32_t disgpio_in_pull_down3; /* 0x61C */ 271 uint32_t rsv_0x620[4]; /* 0x620 ~ 0x62C */ 272 uint32_t disgpio_in_pull_down4; /* 0x630 */ 273 uint32_t disgpio_in_pull_down5; /* 0x634 */ 274 uint32_t disgpio_in_pull_down6; /* 0x638 */ 275 uint32_t rsv_0x63c[5]; /* 0x63C ~ 0x64C */ 276 uint32_t sli_driving_strength; /* 0x650 */ 277 uint32_t rsv_0x654[107]; /* 0x654 ~ 0x7FC */ 278 uint32_t ca7_ctrl1; /* 0x800 */ 279 uint32_t ca7_ctrl2; /* 0x804 */ 280 uint32_t ca7_ctrl3; /* 0x808 */ 281 uint32_t ca7_ctrl4; /* 0x80C */ 282 uint32_t rsv_0x810[4]; /* 0x810 ~ 0x81C */ 283 uint32_t ca7_parity_chk; /* 0x820 */ 284 uint32_t ca7_parity_clr; /* 0x824 */ 285 uint32_t rsv_0x828[118]; /* 0x828 ~ 0x9FC */ 286 uint32_t cm3_ctrl; /* 0xA00 */ 287 uint32_t cm3_base; /* 0xA04 */ 288 uint32_t cm3_imem_addr; /* 0xA08 */ 289 uint32_t cm3_dmem_addr; /* 0xA0C */ 290 uint32_t rsv_0xa10[12]; /* 0xA10 ~ 0xA3C */ 291 uint32_t cm3_cache_area; /* 0xA40 */ 292 uint32_t cm3_cache_invd_ctrl; /* 0xA44 */ 293 uint32_t cm3_cache_func_ctrl; /* 0xA48 */ 294 uint32_t rsv_0xa4c[108]; /* 0xA4C ~ 0xBFC */ 295 uint32_t pci_cfg[3]; /* 0xC00 */ 296 uint32_t rsv_0xc0c[5]; /* 0xC0C ~ 0xC1C */ 297 uint32_t pcie_cfg; /* 0xC20 */ 298 uint32_t mmio_decode; /* 0xC24 */ 299 uint32_t reloc_ctrl_decode[2]; /* 0xC28 */ 300 uint32_t rsv_0xc30[4]; /* 0xC30 ~ 0xC3C */ 301 uint32_t mbox_decode; /* 0xC40 */ 302 uint32_t shared_sram_decode[2]; /* 0xC44 */ 303 uint32_t bmc_rev_id; /* 0xC4C */ 304 uint32_t rsv_0xc50[5]; /* 0xC50 ~ 0xC60 */ 305 uint32_t bmc_device_id; /* 0xC64 */ 306 uint32_t rsv_0xc68[102]; /* 0xC68 ~ 0xDFC */ 307 uint32_t vga_scratch1; /* 0xE00 */ 308 uint32_t vga_scratch2; /* 0xE04 */ 309 uint32_t vga_scratch3; /* 0xE08 */ 310 uint32_t vga_scratch4; /* 0xE0C */ 311 uint32_t rsv_0xe10[4]; /* 0xE10 ~ 0xE1C */ 312 uint32_t vga_scratch5; /* 0xE20 */ 313 uint32_t vga_scratch6; /* 0xE24 */ 314 uint32_t vga_scratch7; /* 0xE28 */ 315 uint32_t vga_scratch8; /* 0xE2C */ 316 uint32_t rsv_0xe30[52]; /* 0xE30 ~ 0xEFC */ 317 uint32_t wr_prot1; /* 0xF00 */ 318 uint32_t wr_prot2; /* 0xF04 */ 319 uint32_t wr_prot3; /* 0xF08 */ 320 uint32_t wr_prot4; /* 0xF0C */ 321 uint32_t wr_prot5; /* 0xF10 */ 322 uint32_t wr_prot6; /* 0xF18 */ 323 uint32_t wr_prot7; /* 0xF1C */ 324 uint32_t wr_prot8; /* 0xF20 */ 325 uint32_t wr_prot9; /* 0xF24 */ 326 uint32_t rsv_0xf28[2]; /* 0xF28 ~ 0xF2C */ 327 uint32_t wr_prot10; /* 0xF30 */ 328 uint32_t wr_prot11; /* 0xF34 */ 329 uint32_t wr_prot12; /* 0xF38 */ 330 uint32_t wr_prot13; /* 0xF3C */ 331 uint32_t wr_prot14; /* 0xF40 */ 332 uint32_t rsv_0xf44; /* 0xF44 */ 333 uint32_t wr_prot15; /* 0xF48 */ 334 uint32_t rsv_0xf4c[5]; /* 0xF4C ~ 0xF5C */ 335 uint32_t wr_prot16; /* 0xF60 */ 336 }; 337 #endif 338 #endif 339