1 /* 2 * Copyright (c) 2019-2020, Broadcom 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SDIO_H 8 #define SDIO_H 9 10 #include <stdbool.h> 11 12 #define SR_IPROC_SDIO0_CFG_BASE 0x689006e4 13 #define SR_IPROC_SDIO0_SID_BASE 0x68900b00 14 #define SR_IPROC_SDIO0_PAD_BASE 0x68a4017c 15 #define SR_IPROC_SDIO0_IOCTRL_BASE 0x68e02408 16 17 #define SR_IPROC_SDIO1_CFG_BASE 0x68900734 18 #define SR_IPROC_SDIO1_SID_BASE 0x68900b08 19 #define SR_IPROC_SDIO1_PAD_BASE 0x68a401b4 20 #define SR_IPROC_SDIO1_IOCTRL_BASE 0x68e03408 21 22 #define NS3Z_IPROC_SDIO0_CFG_BASE 0x68a20540 23 #define NS3Z_IPROC_SDIO0_SID_BASE 0x68900b00 24 #define NS3Z_IPROC_SDIO0_TP_OUT_SEL 0x68a20308 25 #define NS3Z_IPROC_SDIO0_PAD_BASE 0x68a20500 26 #define NS3Z_IPROC_SDIO0_IOCTRL_BASE 0x68e02408 27 28 #define PHY_BYPASS BIT(14) 29 #define LEGACY_EN BIT(31) 30 #define PHY_DISABLE (LEGACY_EN | PHY_BYPASS) 31 32 #define NS3Z_IPROC_SDIO1_CFG_BASE 0x68a30540 33 #define NS3Z_IPROC_SDIO1_SID_BASE 0x68900b08 34 #define NS3Z_IPROC_SDIO1_PAD_BASE 0x68a30500 35 #define NS3Z_IPROC_SDIO1_IOCTRL_BASE 0x68e03408 36 37 #define ICFG_SDIO_CAP0 0x10 38 #define ICFG_SDIO_CAP1 0x14 39 #define ICFG_SDIO_STRAPSTATUS_0 0x0 40 #define ICFG_SDIO_STRAPSTATUS_1 0x4 41 #define ICFG_SDIO_STRAPSTATUS_2 0x8 42 #define ICFG_SDIO_STRAPSTATUS_3 0xc 43 #define ICFG_SDIO_STRAPSTATUS_4 0x18 44 45 #define ICFG_SDIO_SID_ARADDR 0x0 46 #define ICFG_SDIO_SID_AWADDR 0x4 47 48 #define ICFG_SDIOx_CAP0__SLOT_TYPE_MASK 0x3 49 #define ICFG_SDIOx_CAP0__SLOT_TYPE_SHIFT 27 50 #define ICFG_SDIOx_CAP0__INT_MODE_SHIFT 26 51 #define ICFG_SDIOx_CAP0__SYS_BUS_64BIT_SHIFT 25 52 #define ICFG_SDIOx_CAP0__VOLTAGE_1P8V_SHIFT 24 53 #define ICFG_SDIOx_CAP0__VOLTAGE_3P0V_SHIFT 23 54 #define ICFG_SDIOx_CAP0__VOLTAGE_3P3V_SHIFT 22 55 #define ICFG_SDIOx_CAP0__SUSPEND_RESUME_SHIFT 21 56 #define ICFG_SDIOx_CAP0__SDMA_SHIFT 20 57 #define ICFG_SDIOx_CAP0__HIGH_SPEED_SHIFT 19 58 #define ICFG_SDIOx_CAP0__ADMA2_SHIFT 18 59 #define ICFG_SDIOx_CAP0__EXTENDED_MEDIA_SHIFT 17 60 #define ICFG_SDIOx_CAP0__MAX_BLOCK_LEN_MASK 0x3 61 #define ICFG_SDIOx_CAP0__MAX_BLOCK_LEN_SHIFT 15 62 #define ICFG_SDIOx_CAP0__BASE_CLK_FREQ_MASK 0xff 63 #define ICFG_SDIOx_CAP0__BASE_CLK_FREQ_SHIFT 7 64 #define ICFG_SDIOx_CAP0__TIMEOUT_UNIT_SHIFT 6 65 #define ICFG_SDIOx_CAP0__TIMEOUT_CLK_FREQ_MASK 0x3f 66 #define ICFG_SDIOx_CAP0__TIMEOUT_CLK_FREQ_SHIFT 0 67 68 #define ICFG_SDIOx_CAP1__SPI_BLOCK_MODE_SHIFT 22 69 #define ICFG_SDIOx_CAP1__SPI_MODE_SHIFT 21 70 #define ICFG_SDIOx_CAP1__CLK_MULT_MASK 0xff 71 #define ICFG_SDIOx_CAP1__CLK_MULT_SHIFT 13 72 #define ICFG_SDIOx_CAP1__RETUNING_MODE_MASK 0x3 73 #define ICFG_SDIOx_CAP1__RETUNING_MODE_SHIFT 11 74 #define ICFG_SDIOx_CAP1__TUNE_SDR50_SHIFT 10 75 #define ICFG_SDIOx_CAP1__TIME_RETUNE_MASK 0xf 76 #define ICFG_SDIOx_CAP1__TIME_RETUNE_SHIFT 6 77 #define ICFG_SDIOx_CAP1__DRIVER_D_SHIFT 5 78 #define ICFG_SDIOx_CAP1__DRIVER_C_SHIFT 4 79 #define ICFG_SDIOx_CAP1__DRIVER_A_SHIFT 3 80 #define ICFG_SDIOx_CAP1__DDR50_SHIFT 2 81 #define ICFG_SDIOx_CAP1__SDR104_SHIFT 1 82 #define ICFG_SDIOx_CAP1__SDR50_SHIFT 0 83 84 #ifdef USE_DDR 85 #define SDIO_DMA 1 86 #else 87 #define SDIO_DMA 0 88 #endif 89 90 #define SDIO0_CAP0_CFG \ 91 (0x1 << ICFG_SDIOx_CAP0__SLOT_TYPE_SHIFT) \ 92 | (0x0 << ICFG_SDIOx_CAP0__INT_MODE_SHIFT) \ 93 | (0x0 << ICFG_SDIOx_CAP0__SYS_BUS_64BIT_SHIFT) \ 94 | (0x1 << ICFG_SDIOx_CAP0__VOLTAGE_1P8V_SHIFT) \ 95 | (0x1 << ICFG_SDIOx_CAP0__VOLTAGE_3P0V_SHIFT) \ 96 | (0x1 << ICFG_SDIOx_CAP0__VOLTAGE_3P3V_SHIFT) \ 97 | (0x1 << ICFG_SDIOx_CAP0__SUSPEND_RESUME_SHIFT) \ 98 | (SDIO_DMA << ICFG_SDIOx_CAP0__SDMA_SHIFT) \ 99 | (SDIO_DMA << ICFG_SDIOx_CAP0__ADMA2_SHIFT) \ 100 | (0x1 << ICFG_SDIOx_CAP0__HIGH_SPEED_SHIFT) \ 101 | (0x1 << ICFG_SDIOx_CAP0__EXTENDED_MEDIA_SHIFT) \ 102 | (0x2 << ICFG_SDIOx_CAP0__MAX_BLOCK_LEN_SHIFT) \ 103 | (0xc8 << ICFG_SDIOx_CAP0__BASE_CLK_FREQ_SHIFT) \ 104 | (0x1 << ICFG_SDIOx_CAP0__TIMEOUT_UNIT_SHIFT) \ 105 | (0x30 << ICFG_SDIOx_CAP0__TIMEOUT_CLK_FREQ_SHIFT) 106 107 #define SDIO0_CAP1_CFG \ 108 (0x1 << ICFG_SDIOx_CAP1__SPI_BLOCK_MODE_SHIFT)\ 109 | (0x1 << ICFG_SDIOx_CAP1__SPI_MODE_SHIFT)\ 110 | (0x0 << ICFG_SDIOx_CAP1__CLK_MULT_SHIFT)\ 111 | (0x2 << ICFG_SDIOx_CAP1__RETUNING_MODE_SHIFT)\ 112 | (0x1 << ICFG_SDIOx_CAP1__TUNE_SDR50_SHIFT)\ 113 | (0x0 << ICFG_SDIOx_CAP1__DRIVER_D_SHIFT)\ 114 | (0x0 << ICFG_SDIOx_CAP1__DRIVER_C_SHIFT)\ 115 | (0x1 << ICFG_SDIOx_CAP1__DRIVER_A_SHIFT)\ 116 | (0x1 << ICFG_SDIOx_CAP1__DDR50_SHIFT)\ 117 | (0x1 << ICFG_SDIOx_CAP1__SDR104_SHIFT)\ 118 | (0x1 << ICFG_SDIOx_CAP1__SDR50_SHIFT) 119 120 #define SDIO1_CAP0_CFG \ 121 (0x0 << ICFG_SDIOx_CAP0__SLOT_TYPE_SHIFT) \ 122 | (0x0 << ICFG_SDIOx_CAP0__INT_MODE_SHIFT) \ 123 | (0x0 << ICFG_SDIOx_CAP0__SYS_BUS_64BIT_SHIFT) \ 124 | (0x1 << ICFG_SDIOx_CAP0__VOLTAGE_1P8V_SHIFT) \ 125 | (0x1 << ICFG_SDIOx_CAP0__VOLTAGE_3P0V_SHIFT) \ 126 | (0x1 << ICFG_SDIOx_CAP0__VOLTAGE_3P3V_SHIFT) \ 127 | (0x1 << ICFG_SDIOx_CAP0__SUSPEND_RESUME_SHIFT) \ 128 | (SDIO_DMA << ICFG_SDIOx_CAP0__SDMA_SHIFT) \ 129 | (SDIO_DMA << ICFG_SDIOx_CAP0__ADMA2_SHIFT) \ 130 | (0x1 << ICFG_SDIOx_CAP0__HIGH_SPEED_SHIFT) \ 131 | (0x1 << ICFG_SDIOx_CAP0__EXTENDED_MEDIA_SHIFT) \ 132 | (0x2 << ICFG_SDIOx_CAP0__MAX_BLOCK_LEN_SHIFT) \ 133 | (0xc8 << ICFG_SDIOx_CAP0__BASE_CLK_FREQ_SHIFT) \ 134 | (0x1 << ICFG_SDIOx_CAP0__TIMEOUT_UNIT_SHIFT) \ 135 | (0x30 << ICFG_SDIOx_CAP0__TIMEOUT_CLK_FREQ_SHIFT) 136 137 #define SDIO1_CAP1_CFG \ 138 (0x1 << ICFG_SDIOx_CAP1__SPI_BLOCK_MODE_SHIFT)\ 139 | (0x1 << ICFG_SDIOx_CAP1__SPI_MODE_SHIFT)\ 140 | (0x0 << ICFG_SDIOx_CAP1__CLK_MULT_SHIFT)\ 141 | (0x2 << ICFG_SDIOx_CAP1__RETUNING_MODE_SHIFT)\ 142 | (0x1 << ICFG_SDIOx_CAP1__TUNE_SDR50_SHIFT)\ 143 | (0x0 << ICFG_SDIOx_CAP1__DRIVER_D_SHIFT)\ 144 | (0x0 << ICFG_SDIOx_CAP1__DRIVER_C_SHIFT)\ 145 | (0x1 << ICFG_SDIOx_CAP1__DRIVER_A_SHIFT)\ 146 | (0x1 << ICFG_SDIOx_CAP1__DDR50_SHIFT)\ 147 | (0x1 << ICFG_SDIOx_CAP1__SDR104_SHIFT)\ 148 | (0x1 << ICFG_SDIOx_CAP1__SDR50_SHIFT) 149 150 #define PAD_SDIO_CLK 0x4 151 #define PAD_SDIO_DATA0 0x8 152 #define PAD_SDIO_DATA1 0xc 153 #define PAD_SDIO_DATA2 0x10 154 #define PAD_SDIO_DATA3 0x14 155 #define PAD_SDIO_DATA4 0x18 156 #define PAD_SDIO_DATA5 0x1c 157 #define PAD_SDIO_DATA6 0x20 158 #define PAD_SDIO_DATA7 0x24 159 #define PAD_SDIO_CMD 0x28 160 161 /* 12mA Drive strength*/ 162 #define PAD_SDIO_SELX (0x5 << 1) 163 #define PAD_SDIO_SRC (1 << 0) 164 #define PAD_SDIO_MASK (0xF << 0) 165 #define PAD_SDIO_VALUE (PAD_SDIO_SELX | PAD_SDIO_SRC) 166 167 /* 168 * SDIO_PRESETVAL0 169 * 170 * Each 13 Bit filed consists: 171 * drivestrength - 12:11 172 * clkgensel - b10 173 * sdkclkfreqsel - 9:0 174 * Field Bit(s) Description 175 * ============================================================ 176 * SDR25_PRESET 25:13 Preset Value for SDR25 177 * SDR50_PRESET 12:0 Preset Value for SDR50 178 */ 179 #define SDIO_PRESETVAL0 0x01005001 180 181 /* 182 * SDIO_PRESETVAL1 183 * 184 * Each 13 Bit filed consists: 185 * drivestrength - 12:11 186 * clkgensel - b10 187 * sdkclkfreqsel - 9:0 188 * Field Bit(s) Description 189 * ============================================================ 190 * SDR104_PRESET 25:13 Preset Value for SDR104 191 * SDR12_PRESET 12:0 Preset Value for SDR12 192 */ 193 #define SDIO_PRESETVAL1 0x03000004 194 195 /* 196 * SDIO_PRESETVAL2 197 * 198 * Each 13 Bit filed consists: 199 * drivestrength - 12:11 200 * clkgensel - b10 201 * sdkclkfreqsel - 9:0 202 * Field Bit(s) Description 203 * ============================================================ 204 * HIGH_SPEED_PRESET 25:13 Preset Value for High Speed 205 * INIT_PRESET 12:0 Preset Value for Initialization 206 */ 207 #define SDIO_PRESETVAL2 0x010040FA 208 209 /* 210 * SDIO_PRESETVAL3 211 * 212 * Each 13 Bit filed consists: 213 * drivestrength - 12:11 214 * clkgensel - b10 215 * sdkclkfreqsel - 9:0 216 * Field Bit(s) Description 217 * ============================================================ 218 * DDR50_PRESET 25:13 Preset Value for DDR50 219 * DEFAULT_PRESET 12:0 Preset Value for Default Speed 220 */ 221 #define SDIO_PRESETVAL3 0x01004004 222 223 /* 224 * SDIO_PRESETVAL4 225 * 226 * Field Bit(s) Description 227 * ============================================================ 228 * FORCE_USE_IP_TUNE_CLK 30 Force use IP clock 229 * TUNING_COUNT 29:24 Tuning count 230 * OVERRIDE_1P8V 23:16 231 * OVERRIDE_3P3V 15:8 232 * OVERRIDE_3P0V 7:0 233 */ 234 #define SDIO_PRESETVAL4 0x20010101 235 236 #define SDIO_SID_SHIFT 5 237 238 typedef struct { 239 uintptr_t cfg_base; 240 uintptr_t sid_base; 241 uintptr_t io_ctrl_base; 242 uintptr_t pad_base; 243 } SDIO_CFG; 244 245 void brcm_stingray_sdio_init(void); 246 247 #endif /* SDIO_H */ 248