1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* Copyright(c) 2015-17 Intel Corporation. */ 3 4 #ifndef __SDW_REGISTERS_H 5 #define __SDW_REGISTERS_H 6 7 /* 8 * SDW registers as defined by MIPI 1.2 Spec 9 */ 10 #define SDW_REGADDR GENMASK(14, 0) 11 #define SDW_SCP_ADDRPAGE2_MASK GENMASK(22, 15) 12 #define SDW_SCP_ADDRPAGE1_MASK GENMASK(30, 23) 13 14 #define SDW_REG_NO_PAGE 0x00008000 15 #define SDW_REG_OPTIONAL_PAGE 0x00010000 16 #define SDW_REG_MAX 0x80000000 17 18 #define SDW_DPN_SIZE 0x100 19 #define SDW_BANK1_OFFSET 0x10 20 21 /* 22 * DP0 Interrupt register & bits 23 * 24 * Spec treats Status (RO) and Clear (WC) as separate but they are same 25 * address, so treat as same register with WC. 26 */ 27 28 /* both INT and STATUS register are same */ 29 #define SDW_DP0_INT 0x0 30 #define SDW_DP0_INTMASK 0x1 31 #define SDW_DP0_PORTCTRL 0x2 32 #define SDW_DP0_BLOCKCTRL1 0x3 33 #define SDW_DP0_PREPARESTATUS 0x4 34 #define SDW_DP0_PREPARECTRL 0x5 35 36 #define SDW_DP0_INT_TEST_FAIL BIT(0) 37 #define SDW_DP0_INT_PORT_READY BIT(1) 38 #define SDW_DP0_INT_BRA_FAILURE BIT(2) 39 #define SDW_DP0_SDCA_CASCADE BIT(3) 40 /* BIT(4) not allocated in SoundWire specification 1.2 */ 41 #define SDW_DP0_INT_IMPDEF1 BIT(5) 42 #define SDW_DP0_INT_IMPDEF2 BIT(6) 43 #define SDW_DP0_INT_IMPDEF3 BIT(7) 44 #define SDW_DP0_INTERRUPTS (SDW_DP0_INT_TEST_FAIL | \ 45 SDW_DP0_INT_PORT_READY | \ 46 SDW_DP0_INT_BRA_FAILURE | \ 47 SDW_DP0_INT_IMPDEF1 | \ 48 SDW_DP0_INT_IMPDEF2 | \ 49 SDW_DP0_INT_IMPDEF3) 50 51 #define SDW_DP0_PORTCTRL_DATAMODE GENMASK(3, 2) 52 #define SDW_DP0_PORTCTRL_NXTINVBANK BIT(4) 53 #define SDW_DP0_PORTCTRL_BPT_PAYLD GENMASK(7, 6) 54 55 #define SDW_DP0_CHANNELEN 0x20 56 #define SDW_DP0_SAMPLECTRL1 0x22 57 #define SDW_DP0_SAMPLECTRL2 0x23 58 #define SDW_DP0_OFFSETCTRL1 0x24 59 #define SDW_DP0_OFFSETCTRL2 0x25 60 #define SDW_DP0_HCTRL 0x26 61 #define SDW_DP0_LANECTRL 0x28 62 63 /* Both INT and STATUS register are same */ 64 #define SDW_SCP_INT1 0x40 65 #define SDW_SCP_INTMASK1 0x41 66 67 #define SDW_SCP_INT1_PARITY BIT(0) 68 #define SDW_SCP_INT1_BUS_CLASH BIT(1) 69 #define SDW_SCP_INT1_IMPL_DEF BIT(2) 70 #define SDW_SCP_INT1_SCP2_CASCADE BIT(7) 71 #define SDW_SCP_INT1_PORT0_3 GENMASK(6, 3) 72 73 #define SDW_SCP_INTSTAT2 0x42 74 #define SDW_SCP_INTSTAT2_SCP3_CASCADE BIT(7) 75 #define SDW_SCP_INTSTAT2_PORT4_10 GENMASK(6, 0) 76 77 #define SDW_SCP_INTSTAT3 0x43 78 #define SDW_SCP_INTSTAT3_PORT11_14 GENMASK(3, 0) 79 80 /* Number of interrupt status registers */ 81 #define SDW_NUM_INT_STAT_REGISTERS 3 82 83 /* Number of interrupt clear registers */ 84 #define SDW_NUM_INT_CLEAR_REGISTERS 1 85 86 #define SDW_SCP_CTRL 0x44 87 #define SDW_SCP_CTRL_CLK_STP_NOW BIT(1) 88 #define SDW_SCP_CTRL_FORCE_RESET BIT(7) 89 90 #define SDW_SCP_STAT 0x44 91 #define SDW_SCP_STAT_CLK_STP_NF BIT(0) 92 #define SDW_SCP_STAT_HPHY_NOK BIT(5) 93 #define SDW_SCP_STAT_CURR_BANK BIT(6) 94 95 #define SDW_SCP_SYSTEMCTRL 0x45 96 #define SDW_SCP_SYSTEMCTRL_CLK_STP_PREP BIT(0) 97 #define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE BIT(2) 98 #define SDW_SCP_SYSTEMCTRL_WAKE_UP_EN BIT(3) 99 #define SDW_SCP_SYSTEMCTRL_HIGH_PHY BIT(4) 100 101 #define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE0 0 102 #define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE1 BIT(2) 103 104 #define SDW_SCP_DEVNUMBER 0x46 105 #define SDW_SCP_HIGH_PHY_CHECK 0x47 106 #define SDW_SCP_ADDRPAGE1 0x48 107 #define SDW_SCP_ADDRPAGE2 0x49 108 #define SDW_SCP_KEEPEREN 0x4A 109 #define SDW_SCP_BANKDELAY 0x4B 110 #define SDW_SCP_COMMIT 0x4C 111 112 #define SDW_SCP_BUS_CLOCK_BASE 0x4D 113 #define SDW_SCP_BASE_CLOCK_FREQ GENMASK(2, 0) 114 #define SDW_SCP_BASE_CLOCK_UNKNOWN 0x0 115 #define SDW_SCP_BASE_CLOCK_19200000_HZ 0x1 116 #define SDW_SCP_BASE_CLOCK_24000000_HZ 0x2 117 #define SDW_SCP_BASE_CLOCK_24576000_HZ 0x3 118 #define SDW_SCP_BASE_CLOCK_22579200_HZ 0x4 119 #define SDW_SCP_BASE_CLOCK_32000000_HZ 0x5 120 #define SDW_SCP_BASE_CLOCK_RESERVED 0x6 121 #define SDW_SCP_BASE_CLOCK_IMP_DEF 0x7 122 123 /* 0x4E is not allocated in SoundWire specification 1.2 */ 124 #define SDW_SCP_TESTMODE 0x4F 125 #define SDW_SCP_DEVID_0 0x50 126 #define SDW_SCP_DEVID_1 0x51 127 #define SDW_SCP_DEVID_2 0x52 128 #define SDW_SCP_DEVID_3 0x53 129 #define SDW_SCP_DEVID_4 0x54 130 #define SDW_SCP_DEVID_5 0x55 131 132 /* Both INT and STATUS register are same */ 133 #define SDW_SCP_SDCA_INT1 0x58 134 #define SDW_SCP_SDCA_INT_SDCA_0 BIT(0) 135 #define SDW_SCP_SDCA_INT_SDCA_1 BIT(1) 136 #define SDW_SCP_SDCA_INT_SDCA_2 BIT(2) 137 #define SDW_SCP_SDCA_INT_SDCA_3 BIT(3) 138 #define SDW_SCP_SDCA_INT_SDCA_4 BIT(4) 139 #define SDW_SCP_SDCA_INT_SDCA_5 BIT(5) 140 #define SDW_SCP_SDCA_INT_SDCA_6 BIT(6) 141 #define SDW_SCP_SDCA_INT_SDCA_7 BIT(7) 142 143 #define SDW_SCP_SDCA_INT2 0x59 144 #define SDW_SCP_SDCA_INT_SDCA_8 BIT(0) 145 #define SDW_SCP_SDCA_INT_SDCA_9 BIT(1) 146 #define SDW_SCP_SDCA_INT_SDCA_10 BIT(2) 147 #define SDW_SCP_SDCA_INT_SDCA_11 BIT(3) 148 #define SDW_SCP_SDCA_INT_SDCA_12 BIT(4) 149 #define SDW_SCP_SDCA_INT_SDCA_13 BIT(5) 150 #define SDW_SCP_SDCA_INT_SDCA_14 BIT(6) 151 #define SDW_SCP_SDCA_INT_SDCA_15 BIT(7) 152 153 #define SDW_SCP_SDCA_INT3 0x5A 154 #define SDW_SCP_SDCA_INT_SDCA_16 BIT(0) 155 #define SDW_SCP_SDCA_INT_SDCA_17 BIT(1) 156 #define SDW_SCP_SDCA_INT_SDCA_18 BIT(2) 157 #define SDW_SCP_SDCA_INT_SDCA_19 BIT(3) 158 #define SDW_SCP_SDCA_INT_SDCA_20 BIT(4) 159 #define SDW_SCP_SDCA_INT_SDCA_21 BIT(5) 160 #define SDW_SCP_SDCA_INT_SDCA_22 BIT(6) 161 #define SDW_SCP_SDCA_INT_SDCA_23 BIT(7) 162 163 #define SDW_SCP_SDCA_INT4 0x5B 164 #define SDW_SCP_SDCA_INT_SDCA_24 BIT(0) 165 #define SDW_SCP_SDCA_INT_SDCA_25 BIT(1) 166 #define SDW_SCP_SDCA_INT_SDCA_26 BIT(2) 167 #define SDW_SCP_SDCA_INT_SDCA_27 BIT(3) 168 #define SDW_SCP_SDCA_INT_SDCA_28 BIT(4) 169 #define SDW_SCP_SDCA_INT_SDCA_29 BIT(5) 170 #define SDW_SCP_SDCA_INT_SDCA_30 BIT(6) 171 /* BIT(7) not allocated in SoundWire 1.2 specification */ 172 173 #define SDW_SCP_SDCA_INTMASK1 0x5C 174 #define SDW_SCP_SDCA_INTMASK_SDCA_0 BIT(0) 175 #define SDW_SCP_SDCA_INTMASK_SDCA_1 BIT(1) 176 #define SDW_SCP_SDCA_INTMASK_SDCA_2 BIT(2) 177 #define SDW_SCP_SDCA_INTMASK_SDCA_3 BIT(3) 178 #define SDW_SCP_SDCA_INTMASK_SDCA_4 BIT(4) 179 #define SDW_SCP_SDCA_INTMASK_SDCA_5 BIT(5) 180 #define SDW_SCP_SDCA_INTMASK_SDCA_6 BIT(6) 181 #define SDW_SCP_SDCA_INTMASK_SDCA_7 BIT(7) 182 183 #define SDW_SCP_SDCA_INTMASK2 0x5D 184 #define SDW_SCP_SDCA_INTMASK_SDCA_8 BIT(0) 185 #define SDW_SCP_SDCA_INTMASK_SDCA_9 BIT(1) 186 #define SDW_SCP_SDCA_INTMASK_SDCA_10 BIT(2) 187 #define SDW_SCP_SDCA_INTMASK_SDCA_11 BIT(3) 188 #define SDW_SCP_SDCA_INTMASK_SDCA_12 BIT(4) 189 #define SDW_SCP_SDCA_INTMASK_SDCA_13 BIT(5) 190 #define SDW_SCP_SDCA_INTMASK_SDCA_14 BIT(6) 191 #define SDW_SCP_SDCA_INTMASK_SDCA_15 BIT(7) 192 193 #define SDW_SCP_SDCA_INTMASK3 0x5E 194 #define SDW_SCP_SDCA_INTMASK_SDCA_16 BIT(0) 195 #define SDW_SCP_SDCA_INTMASK_SDCA_17 BIT(1) 196 #define SDW_SCP_SDCA_INTMASK_SDCA_18 BIT(2) 197 #define SDW_SCP_SDCA_INTMASK_SDCA_19 BIT(3) 198 #define SDW_SCP_SDCA_INTMASK_SDCA_20 BIT(4) 199 #define SDW_SCP_SDCA_INTMASK_SDCA_21 BIT(5) 200 #define SDW_SCP_SDCA_INTMASK_SDCA_22 BIT(6) 201 #define SDW_SCP_SDCA_INTMASK_SDCA_23 BIT(7) 202 203 #define SDW_SCP_SDCA_INTMASK4 0x5F 204 #define SDW_SCP_SDCA_INTMASK_SDCA_24 BIT(0) 205 #define SDW_SCP_SDCA_INTMASK_SDCA_25 BIT(1) 206 #define SDW_SCP_SDCA_INTMASK_SDCA_26 BIT(2) 207 #define SDW_SCP_SDCA_INTMASK_SDCA_27 BIT(3) 208 #define SDW_SCP_SDCA_INTMASK_SDCA_28 BIT(4) 209 #define SDW_SCP_SDCA_INTMASK_SDCA_29 BIT(5) 210 #define SDW_SCP_SDCA_INTMASK_SDCA_30 BIT(6) 211 /* BIT(7) not allocated in SoundWire 1.2 specification */ 212 213 /* Banked Registers */ 214 #define SDW_SCP_FRAMECTRL_B0 0x60 215 #define SDW_SCP_FRAMECTRL_B1 (0x60 + SDW_BANK1_OFFSET) 216 #define SDW_SCP_NEXTFRAME_B0 0x61 217 #define SDW_SCP_NEXTFRAME_B1 (0x61 + SDW_BANK1_OFFSET) 218 219 #define SDW_SCP_BUSCLOCK_SCALE_B0 0x62 220 #define SDW_SCP_BUSCLOCK_SCALE_B1 (0x62 + SDW_BANK1_OFFSET) 221 #define SDW_SCP_CLOCK_SCALE GENMASK(3, 0) 222 223 /* PHY registers - CTRL and STAT are the same address */ 224 #define SDW_SCP_PHY_OUT_CTRL_0 0x80 225 #define SDW_SCP_PHY_OUT_CTRL_1 0x81 226 #define SDW_SCP_PHY_OUT_CTRL_2 0x82 227 #define SDW_SCP_PHY_OUT_CTRL_3 0x83 228 #define SDW_SCP_PHY_OUT_CTRL_4 0x84 229 #define SDW_SCP_PHY_OUT_CTRL_5 0x85 230 #define SDW_SCP_PHY_OUT_CTRL_6 0x86 231 #define SDW_SCP_PHY_OUT_CTRL_7 0x87 232 233 #define SDW_SCP_CAP_LOAD_CTRL GENMASK(2, 0) 234 #define SDW_SCP_DRIVE_STRENGTH_CTRL GENMASK(5, 3) 235 #define SDW_SCP_SLEW_TIME_CTRL GENMASK(7, 6) 236 237 /* Both INT and STATUS register is same */ 238 #define SDW_DPN_INT(n) (0x0 + SDW_DPN_SIZE * (n)) 239 #define SDW_DPN_INTMASK(n) (0x1 + SDW_DPN_SIZE * (n)) 240 #define SDW_DPN_PORTCTRL(n) (0x2 + SDW_DPN_SIZE * (n)) 241 #define SDW_DPN_BLOCKCTRL1(n) (0x3 + SDW_DPN_SIZE * (n)) 242 #define SDW_DPN_PREPARESTATUS(n) (0x4 + SDW_DPN_SIZE * (n)) 243 #define SDW_DPN_PREPARECTRL(n) (0x5 + SDW_DPN_SIZE * (n)) 244 245 #define SDW_DPN_INT_TEST_FAIL BIT(0) 246 #define SDW_DPN_INT_PORT_READY BIT(1) 247 #define SDW_DPN_INT_IMPDEF1 BIT(5) 248 #define SDW_DPN_INT_IMPDEF2 BIT(6) 249 #define SDW_DPN_INT_IMPDEF3 BIT(7) 250 #define SDW_DPN_INTERRUPTS (SDW_DPN_INT_TEST_FAIL | \ 251 SDW_DPN_INT_PORT_READY | \ 252 SDW_DPN_INT_IMPDEF1 | \ 253 SDW_DPN_INT_IMPDEF2 | \ 254 SDW_DPN_INT_IMPDEF3) 255 256 #define SDW_DPN_PORTCTRL_FLOWMODE GENMASK(1, 0) 257 #define SDW_DPN_PORTCTRL_DATAMODE GENMASK(3, 2) 258 #define SDW_DPN_PORTCTRL_NXTINVBANK BIT(4) 259 260 #define SDW_DPN_BLOCKCTRL1_WDLEN GENMASK(5, 0) 261 262 #define SDW_DPN_PREPARECTRL_CH_PREP GENMASK(7, 0) 263 264 #define SDW_DPN_CHANNELEN_B0(n) (0x20 + SDW_DPN_SIZE * (n)) 265 #define SDW_DPN_CHANNELEN_B1(n) (0x30 + SDW_DPN_SIZE * (n)) 266 267 #define SDW_DPN_BLOCKCTRL2_B0(n) (0x21 + SDW_DPN_SIZE * (n)) 268 #define SDW_DPN_BLOCKCTRL2_B1(n) (0x31 + SDW_DPN_SIZE * (n)) 269 270 #define SDW_DPN_SAMPLECTRL1_B0(n) (0x22 + SDW_DPN_SIZE * (n)) 271 #define SDW_DPN_SAMPLECTRL1_B1(n) (0x32 + SDW_DPN_SIZE * (n)) 272 273 #define SDW_DPN_SAMPLECTRL2_B0(n) (0x23 + SDW_DPN_SIZE * (n)) 274 #define SDW_DPN_SAMPLECTRL2_B1(n) (0x33 + SDW_DPN_SIZE * (n)) 275 276 #define SDW_DPN_OFFSETCTRL1_B0(n) (0x24 + SDW_DPN_SIZE * (n)) 277 #define SDW_DPN_OFFSETCTRL1_B1(n) (0x34 + SDW_DPN_SIZE * (n)) 278 279 #define SDW_DPN_OFFSETCTRL2_B0(n) (0x25 + SDW_DPN_SIZE * (n)) 280 #define SDW_DPN_OFFSETCTRL2_B1(n) (0x35 + SDW_DPN_SIZE * (n)) 281 282 #define SDW_DPN_HCTRL_B0(n) (0x26 + SDW_DPN_SIZE * (n)) 283 #define SDW_DPN_HCTRL_B1(n) (0x36 + SDW_DPN_SIZE * (n)) 284 285 #define SDW_DPN_BLOCKCTRL3_B0(n) (0x27 + SDW_DPN_SIZE * (n)) 286 #define SDW_DPN_BLOCKCTRL3_B1(n) (0x37 + SDW_DPN_SIZE * (n)) 287 288 #define SDW_DPN_LANECTRL_B0(n) (0x28 + SDW_DPN_SIZE * (n)) 289 #define SDW_DPN_LANECTRL_B1(n) (0x38 + SDW_DPN_SIZE * (n)) 290 291 #define SDW_DPN_SAMPLECTRL_LOW GENMASK(7, 0) 292 #define SDW_DPN_SAMPLECTRL_HIGH GENMASK(15, 8) 293 294 #define SDW_DPN_HCTRL_HSTART GENMASK(7, 4) 295 #define SDW_DPN_HCTRL_HSTOP GENMASK(3, 0) 296 297 #define SDW_NUM_CASC_PORT_INTSTAT1 4 298 #define SDW_CASC_PORT_START_INTSTAT1 0 299 #define SDW_CASC_PORT_MASK_INTSTAT1 0x8 300 #define SDW_CASC_PORT_REG_OFFSET_INTSTAT1 0x0 301 302 #define SDW_NUM_CASC_PORT_INTSTAT2 7 303 #define SDW_CASC_PORT_START_INTSTAT2 4 304 #define SDW_CASC_PORT_MASK_INTSTAT2 1 305 #define SDW_CASC_PORT_REG_OFFSET_INTSTAT2 1 306 307 #define SDW_NUM_CASC_PORT_INTSTAT3 4 308 #define SDW_CASC_PORT_START_INTSTAT3 11 309 #define SDW_CASC_PORT_MASK_INTSTAT3 1 310 #define SDW_CASC_PORT_REG_OFFSET_INTSTAT3 2 311 312 /* 313 * v1.2 device - SDCA address mapping 314 * 315 * Spec definition 316 * Bits Contents 317 * 31 0 (required by addressing range) 318 * 30:26 0b10000 (Control Prefix) 319 * 25 0 (Reserved) 320 * 24:22 Function Number [2:0] 321 * 21 Entity[6] 322 * 20:19 Control Selector[5:4] 323 * 18 0 (Reserved) 324 * 17:15 Control Number[5:3] 325 * 14 Next 326 * 13 MBQ 327 * 12:7 Entity[5:0] 328 * 6:3 Control Selector[3:0] 329 * 2:0 Control Number[2:0] 330 */ 331 332 #define SDW_SDCA_CTL(fun, ent, ctl, ch) (BIT(30) | \ 333 (((fun) & 0x7) << 22) | \ 334 (((ent) & 0x40) << 15) | \ 335 (((ent) & 0x3f) << 7) | \ 336 (((ctl) & 0x30) << 15) | \ 337 (((ctl) & 0x0f) << 3) | \ 338 (((ch) & 0x38) << 12) | \ 339 ((ch) & 0x07)) 340 341 #define SDW_SDCA_MBQ_CTL(reg) ((reg) | BIT(13)) 342 #define SDW_SDCA_NEXT_CTL(reg) ((reg) | BIT(14)) 343 344 #endif /* __SDW_REGISTERS_H */ 345