1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2016, Wind River Systems. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef PLATFORM_CONFIG_H 30 #define PLATFORM_CONFIG_H 31 32 #define STACK_ALIGNMENT 64 33 34 /* For Zynq7000 board */ 35 36 #define SCU_BASE 0xF8F00000 37 #define PL310_BASE 0xF8F02000 38 #define GIC_BASE 0xF8F00000 39 #define GICC_OFFSET 0x100 40 #define GICD_OFFSET 0x1000 41 #define GIC_CPU_BASE (GIC_BASE + GICC_OFFSET) 42 #define GIC_DIST_BASE (GIC_BASE + GICD_OFFSET) 43 44 #define SLCR_BASE 0xF8000000 45 #define SLCR_LOCK 0xF8000004 46 #define SLCR_UNLOCK 0xF8000008 47 #define SLCR_TZ_DDR_RAM 0xF8000430 48 #define SLCR_TZ_DMA_NS 0xF8000440 49 #define SLCR_TZ_DMA_IRQ_NS 0xF8000444 50 #define SLCR_TZ_DMA_PERIPH_NS 0xF8000448 51 #define SLCR_TZ_GEM 0xF8000450 52 #define SLCR_TZ_SDIO 0xF8000454 53 #define SLCR_TZ_USB 0xF8000458 54 #define SLCR_L2C_RAM 0xF8000A1C 55 56 #define SLCR_LOCK_MAGIC 0x0000767B 57 #define SLCR_UNLOCK_MAGIC 0x0000DF0D 58 59 #define SECURITY2_SDIO0 0xE0200008 60 #define SECURITY3_SDIO1 0xE020000C 61 #define SECURITY4_QSPI 0xE0200010 62 #define SECURITY6_APB_SLAVES 0xE0200018 63 64 #define UART0_BASE 0xE0000000 65 #define UART1_BASE 0xE0001000 66 67 #define CONSOLE_UART_BASE UART1_BASE 68 69 #define TEE_RAM_VA_SIZE (1024 * 1024) 70 71 /* 72 * PL310 TAG RAM Control Register 73 * 74 * bit[10:8]:1 - 2 cycle of write accesses latency 75 * bit[6:4]:1 - 2 cycle of read accesses latency 76 * bit[2:0]:1 - 2 cycle of setup latency 77 */ 78 #ifndef PL310_TAG_RAM_CTRL_INIT 79 #define PL310_TAG_RAM_CTRL_INIT 0x00000111 80 #endif 81 82 /* 83 * PL310 DATA RAM Control Register 84 * 85 * bit[10:8]:2 - 3 cycle of write accesses latency 86 * bit[6:4]:2 - 3 cycle of read accesses latency 87 * bit[2:0]:2 - 3 cycle of setup latency 88 */ 89 #ifndef PL310_DATA_RAM_CTRL_INIT 90 #define PL310_DATA_RAM_CTRL_INIT 0x00000222 91 #endif 92 93 /* 94 * PL310 Auxiliary Control Register 95 * 96 * I/Dcache prefetch enabled (bit29:28=2b11) 97 * NS can access interrupts (bit27=1) 98 * NS can lockown cache lines (bit26=1) 99 * Pseudo-random replacement policy (bit25=0) 100 * Force write allocated (default) 101 * Shared attribute internally ignored (bit22=1, bit13=0) 102 * Parity disabled (bit21=0) 103 * Event monitor disabled (bit20=0) 104 * Platform fmavor specific way config: 105 * - 64kb way size (bit19:17=3b011) 106 * - 8-way associciativity (bit16=0) 107 * Store buffer device limitation enabled (bit11=1) 108 * Cacheable accesses have high prio (bit10=0) 109 * Full Line Zero (FLZ) disabled (bit0=0) 110 */ 111 #ifndef PL310_AUX_CTRL_INIT 112 #define PL310_AUX_CTRL_INIT 0x3C460800 113 #endif 114 115 /* 116 * PL310 Prefetch Control Register 117 * 118 * Double linefill disabled (bit30=0) 119 * I/D prefetch enabled (bit29:28=2b11) 120 * Prefetch drop enabled (bit24=1) 121 * Incr double linefill disable (bit23=0) 122 * Prefetch offset = 7 (bit4:0) 123 */ 124 #define PL310_PREFETCH_CTRL_INIT 0x31000007 125 126 /* 127 * PL310 Power Register 128 * 129 * Dynamic clock gating enabled 130 * Standby mode enabled 131 */ 132 #define PL310_POWER_CTRL_INIT 0x00000003 133 134 /* 135 * SCU Invalidate Register 136 * 137 * Invalidate all registers 138 */ 139 #define SCU_INV_CTRL_INIT 0xFFFFFFFF 140 141 /* 142 * SCU Access Register 143 * - both secure CPU access SCU 144 */ 145 #define SCU_SAC_CTRL_INIT 0x0000000F 146 147 /* 148 * SCU NonSecure Access Register 149 * - both nonsec cpu access SCU, private and global timer 150 */ 151 #define SCU_NSAC_CTRL_INIT 0x00000FFF 152 153 /* all bit enabled in access control register */ 154 #define ACCESS_BITS_ALL 0xFFFFFFFF 155 156 /* recommended value for setting the L2C_RAM register */ 157 #define SLCR_L2C_RAM_VALUE 0x00020202 158 159 /* place in OCRAM to write secondary entry to */ 160 #define SECONDARY_ENTRY_DROP 0xFFFFFFF0 161 162 /* define the memory areas */ 163 164 #ifdef CFG_WITH_PAGER 165 166 /* 167 * TEE/TZ RAM layout: 168 * 169 * +---------------------------------------+ <- CFG_CORE_TZSRAM_EMUL_START 170 * | TEE private highly | TEE_RAM | ^ 171 * | secure memory | | | CFG_CORE_TZSRAM_EMUL_SIZE 172 * +---------------------------------------+ v 173 * 174 * +---------------------------------------+ <- TZDRAM_BASE 175 * | TEE private secure | TA_RAM | ^ + TZDRAM_SIZE 176 * | external memory | | v 177 * +---------------------------------------+ <- TEE_SHMEM_START 178 * | Non secure | SHM | | 179 * | shared memory | | | + TEE_SHMEM_SIZE 180 * +---------------------------------------+ v 181 * 182 * TEE_RAM : default 256kByte 183 * TA_RAM : all what is left in DDR TEE reserved area 184 * PUB_RAM : default 2MByte 185 */ 186 187 /* emulated SRAM, 256K at start of secure DDR */ 188 189 #define TZSRAM_BASE 0x3E000000 190 #define TZSRAM_SIZE CFG_CORE_TZSRAM_EMUL_SIZE 191 192 /* Location of trusted dram */ 193 194 #define TEE_RAM_START TZSRAM_BASE 195 #define TEE_RAM_PH_SIZE TZSRAM_SIZE 196 197 #define TZDRAM_BASE 0x3e100000 198 #define TZDRAM_SIZE 0x01e00000 199 200 #define TEE_SHMEM_START 0x3ff00000 201 #define TEE_SHMEM_SIZE 0x00100000 202 203 #define TA_RAM_START TZDRAM_BASE 204 #define TA_RAM_SIZE TZDRAM_SIZE 205 206 #ifdef CFG_TEE_LOAD_ADDR 207 #define TEE_LOAD_ADDR CFG_TEE_LOAD_ADDR 208 #else 209 #define TEE_LOAD_ADDR TEE_RAM_START 210 #endif 211 212 #else /* CFG_WITH_PAGER */ 213 214 /* 215 * TEE/TZ RAM layout: 216 * 217 * +---------------------------------------+ <- TZDRAM_BASE 218 * | TEE private secure | TEE_RAM | ^ 219 * | external memory +------------------+ | 220 * | | TA_RAM | | 221 * +---------------------------------------+ | TZDRAM_SIZE 222 * | Non secure | SHM | | 223 * | shared memory | | | 224 * +---------------------------------------+ v 225 * 226 * TEE_RAM : 1MByte 227 * PUB_RAM : 1MByte 228 * TA_RAM : all what is left (at least 2MByte !) 229 */ 230 231 #define TZDRAM_BASE 0x3E000000 232 #define TZDRAM_SIZE (0x02000000 - TEE_SHMEM_SIZE) 233 234 #define TEE_RAM_START TZDRAM_BASE 235 #define TEE_RAM_PH_SIZE (1 * 1024 * 1024) 236 237 #define TA_RAM_START (TZDRAM_BASE + TEE_RAM_PH_SIZE) 238 #define TA_RAM_SIZE (TZDRAM_SIZE - TEE_RAM_PH_SIZE) 239 240 #define TEE_SHMEM_START (TZDRAM_BASE + TZDRAM_SIZE) 241 #define TEE_SHMEM_SIZE 0x00100000 242 243 #ifdef CFG_TEE_LOAD_ADDR 244 #define TEE_LOAD_ADDR CFG_TEE_LOAD_ADDR 245 #else 246 #define TEE_LOAD_ADDR TEE_RAM_START 247 #endif 248 249 #endif /* CFG_WITH_PAGER */ 250 251 #endif /*PLATFORM_CONFIG_H*/ 252