1 /* 2 * Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef QOS_COMMON_H 8 #define QOS_COMMON_H 9 10 #define RCAR_REF_DEFAULT 0U 11 12 /* define used for get_refperiod. */ 13 /* REFPERIOD_CYCLE need smaller than QOSWT_WTSET0_CYCLEs */ 14 /* refere to plat/renesas/rcar/ddr/ddr_a/ddr_init_e3.h for E3. */ 15 #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF default */ 16 #define REFPERIOD_CYCLE /* unit:ns */ \ 17 ((126 * BASE_SUB_SLOT_NUM * 1000U) / 400) 18 #else /* REF option */ 19 #define REFPERIOD_CYCLE /* unit:ns */ \ 20 ((252 * BASE_SUB_SLOT_NUM * 1000U) / 400) 21 #endif 22 23 #if (RCAR_LSI == RCAR_E3) 24 /* define used for E3 */ 25 #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 3.9usec */ 26 #define SUB_SLOT_CYCLE_E3 0xAFU /* 175 */ 27 #else /* REF 7.8usec */ 28 #define SUB_SLOT_CYCLE_E3 0x15EU /* 350 */ 29 #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */ 30 31 #define OPERATING_FREQ_E3 266U /* MHz */ 32 #define SL_INIT_SSLOTCLK_E3 (SUB_SLOT_CYCLE_E3 - 1U) 33 #endif 34 35 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N) 36 /* define used for M3N */ 37 #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */ 38 #define SUB_SLOT_CYCLE_M3N 0x7EU /* 126 */ 39 #else /* REF 3.9usec */ 40 #define SUB_SLOT_CYCLE_M3N 0xFCU /* 252 */ 41 #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */ 42 43 #define SL_INIT_SSLOTCLK_M3N (SUB_SLOT_CYCLE_M3N - 1U) 44 #define QOSWT_WTSET0_CYCLE_M3N /* unit:ns */ \ 45 ((SUB_SLOT_CYCLE_M3N * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) 46 #endif 47 48 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) 49 /* define used for H3 */ 50 #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */ 51 #define SUB_SLOT_CYCLE_H3_20 0x7EU /* 126 */ 52 #else /* REF 3.9usec */ 53 #define SUB_SLOT_CYCLE_H3_20 0xFCU /* 252 */ 54 #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */ 55 56 #define SL_INIT_SSLOTCLK_H3_20 (SUB_SLOT_CYCLE_H3_20 - 1U) 57 #define QOSWT_WTSET0_CYCLE_H3_20 /* unit:ns */ \ 58 ((SUB_SLOT_CYCLE_H3_20 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) 59 60 /* define used for H3 Cut 30 */ 61 #define SUB_SLOT_CYCLE_H3_30 (SUB_SLOT_CYCLE_H3_20) /* same as H3 Cut 20 */ 62 #define SL_INIT_SSLOTCLK_H3_30 (SUB_SLOT_CYCLE_H3_30 - 1U) 63 #define QOSWT_WTSET0_CYCLE_H3_30 /* unit:ns */ \ 64 ((SUB_SLOT_CYCLE_H3_30 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) 65 66 #endif 67 68 #if (RCAR_LSI == RCAR_H3N) 69 /* define used for H3N */ 70 #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */ 71 #define SUB_SLOT_CYCLE_H3N 0x7EU /* 126 */ 72 #else /* REF 3.9usec */ 73 #define SUB_SLOT_CYCLE_H3N 0xFCU /* 252 */ 74 #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */ 75 76 #define SL_INIT_SSLOTCLK_H3N (SUB_SLOT_CYCLE_H3N - 1U) 77 #define QOSWT_WTSET0_CYCLE_H3N /* unit:ns */ \ 78 ((SUB_SLOT_CYCLE_H3N * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) 79 80 #endif 81 82 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3) 83 /* define used for M3 */ 84 #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */ 85 #define SUB_SLOT_CYCLE_M3_11 0x7EU /* 126 */ 86 #define SUB_SLOT_CYCLE_M3_30 0x7EU /* 126 */ 87 #else /* REF 3.9usec */ 88 #define SUB_SLOT_CYCLE_M3_11 0xFCU /* 252 */ 89 #define SUB_SLOT_CYCLE_M3_30 0xFCU /* 252 */ 90 #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */ 91 92 #define SL_INIT_SSLOTCLK_M3_11 (SUB_SLOT_CYCLE_M3_11 - 1U) 93 #define SL_INIT_SSLOTCLK_M3_30 (SUB_SLOT_CYCLE_M3_30 - 1U) 94 #define QOSWT_WTSET0_CYCLE_M3_11 /* unit:ns */ \ 95 ((SUB_SLOT_CYCLE_M3_11 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) 96 #define QOSWT_WTSET0_CYCLE_M3_30 /* unit:ns */ \ 97 ((SUB_SLOT_CYCLE_M3_30 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) 98 #endif 99 100 #define OPERATING_FREQ 400U /* MHz */ 101 #define BASE_SUB_SLOT_NUM 0x6U 102 #define SUB_SLOT_CYCLE 0x7EU /* 126 */ 103 104 #define QOSWT_WTSET0_CYCLE /* unit:ns */ \ 105 ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) 106 107 #define SL_INIT_REFFSSLOT (0x3U << 24U) 108 #define SL_INIT_SLOTSSLOT ((BASE_SUB_SLOT_NUM - 1U) << 16U) 109 #define SL_INIT_SSLOTCLK (SUB_SLOT_CYCLE - 1U) 110 io_write_32(uintptr_t addr,uint32_t value)111static inline void io_write_32(uintptr_t addr, uint32_t value) 112 { 113 *(volatile uint32_t *)addr = value; 114 } 115 io_read_32(uintptr_t addr)116static inline uint32_t io_read_32(uintptr_t addr) 117 { 118 return *(volatile uint32_t *)addr; 119 } 120 io_write_64(uintptr_t addr,uint64_t value)121static inline void io_write_64(uintptr_t addr, uint64_t value) 122 { 123 *(volatile uint64_t *)addr = value; 124 } 125 126 typedef struct { 127 uintptr_t addr; 128 uint64_t value; 129 } mstat_slot_t; 130 131 struct rcar_gen3_dbsc_qos_settings { 132 uint32_t reg; 133 uint32_t val; 134 }; 135 136 extern uint32_t qos_init_ddr_ch; 137 extern uint8_t qos_init_ddr_phyvalid; 138 139 void rcar_qos_dbsc_setting(struct rcar_gen3_dbsc_qos_settings *qos, 140 unsigned int qos_size, bool dbsc_wren); 141 142 #endif /* QOS_COMMON_H */ 143