1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOC_CSS_DEF_H 8 #define SOC_CSS_DEF_H 9 10 #include <lib/utils_def.h> 11 #include <plat/common/common_def.h> 12 13 /* 14 * Definitions common to all ARM CSS SoCs 15 */ 16 17 /* Following covers ARM CSS SoC Peripherals and PCIe expansion area */ 18 #define SOC_CSS_DEVICE_BASE 0x40000000 19 #define SOC_CSS_DEVICE_SIZE 0x40000000 20 #define SOC_CSS_PCIE_CONTROL_BASE 0x7ff20000 21 22 /* PL011 UART related constants */ 23 #define SOC_CSS_UART0_BASE 0x7ff80000 24 #define SOC_CSS_UART1_BASE 0x7ff70000 25 26 #define SOC_CSS_UART0_CLK_IN_HZ 7372800 27 #define SOC_CSS_UART1_CLK_IN_HZ 7372800 28 29 /* SoC NIC-400 Global Programmers View (GPV) */ 30 #define SOC_CSS_NIC400_BASE 0x7fd00000 31 32 #define SOC_CSS_NIC400_USB_EHCI 0 33 #define SOC_CSS_NIC400_TLX_MASTER 1 34 #define SOC_CSS_NIC400_USB_OHCI 2 35 #define SOC_CSS_NIC400_PL354_SMC 3 36 /* 37 * The apb4_bridge controls access to: 38 * - the PCIe configuration registers 39 * - the MMU units for USB, HDLCD and DMA 40 */ 41 #define SOC_CSS_NIC400_APB4_BRIDGE 4 42 43 /* Non-volatile counters */ 44 #define SOC_TRUSTED_NVCTR_BASE 0x7fe70000 45 #define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0000) 46 #define TFW_NVCTR_SIZE 4 47 #define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004) 48 #define NTFW_CTR_SIZE 4 49 50 /* Keys */ 51 #define SOC_KEYS_BASE 0x7fe80000 52 #define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000) 53 #define TZ_PUB_KEY_HASH_SIZE 32 54 #define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020) 55 #define HU_KEY_SIZE 16 56 #define END_KEY_BASE (SOC_KEYS_BASE + 0x0044) 57 #define END_KEY_SIZE 32 58 59 #define SOC_CSS_MAP_DEVICE MAP_REGION_FLAT( \ 60 SOC_CSS_DEVICE_BASE, \ 61 SOC_CSS_DEVICE_SIZE, \ 62 MT_DEVICE | MT_RW | MT_SECURE) 63 64 65 /* 66 * The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs. 67 */ 68 #define SOC_CSS_NIC400_BOOTSEC_BRIDGE 5 69 #define SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1 (1 << 12) 70 71 /* 72 * Required platform porting definitions common to all ARM CSS SoCs 73 */ 74 #if JUNO_AARCH32_EL3_RUNTIME 75 /* 76 * Following change is required to initialize TZC 77 * for enabling access to the HI_VECTOR (0xFFFF0000) 78 * location needed for JUNO AARCH32 support. 79 */ 80 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x8000) 81 #else 82 /* 2MB used for SCP DDR retraining */ 83 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x00200000) 84 #endif 85 86 #endif /* SOC_CSS_DEF_H */ 87