1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2016-2017 Micron Technology, Inc.
4  *
5  *  Authors:
6  *	Peter Pan <peterpandong@micron.com>
7  */
8 #ifndef __LINUX_MTD_SPINAND_H
9 #define __LINUX_MTD_SPINAND_H
10 
11 #include <linux/mutex.h>
12 #include <linux/bitops.h>
13 #include <linux/device.h>
14 #include <linux/mtd/mtd.h>
15 #include <linux/mtd/nand.h>
16 #include <linux/spi/spi.h>
17 #include <linux/spi/spi-mem.h>
18 
19 /**
20  * Standard SPI NAND flash operations
21  */
22 
23 #define SPINAND_RESET_OP						\
24 	SPI_MEM_OP(SPI_MEM_OP_CMD(0xff, 1),				\
25 		   SPI_MEM_OP_NO_ADDR,					\
26 		   SPI_MEM_OP_NO_DUMMY,					\
27 		   SPI_MEM_OP_NO_DATA)
28 
29 #define SPINAND_WR_EN_DIS_OP(enable)					\
30 	SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1),		\
31 		   SPI_MEM_OP_NO_ADDR,					\
32 		   SPI_MEM_OP_NO_DUMMY,					\
33 		   SPI_MEM_OP_NO_DATA)
34 
35 #define SPINAND_READID_OP(naddr, ndummy, buf, len)			\
36 	SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1),				\
37 		   SPI_MEM_OP_ADDR(naddr, 0, 1),			\
38 		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
39 		   SPI_MEM_OP_DATA_IN(len, buf, 1))
40 
41 #define SPINAND_SET_FEATURE_OP(reg, valptr)				\
42 	SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1),				\
43 		   SPI_MEM_OP_ADDR(1, reg, 1),				\
44 		   SPI_MEM_OP_NO_DUMMY,					\
45 		   SPI_MEM_OP_DATA_OUT(1, valptr, 1))
46 
47 #define SPINAND_GET_FEATURE_OP(reg, valptr)				\
48 	SPI_MEM_OP(SPI_MEM_OP_CMD(0x0f, 1),				\
49 		   SPI_MEM_OP_ADDR(1, reg, 1),				\
50 		   SPI_MEM_OP_NO_DUMMY,					\
51 		   SPI_MEM_OP_DATA_IN(1, valptr, 1))
52 
53 #define SPINAND_BLK_ERASE_OP(addr)					\
54 	SPI_MEM_OP(SPI_MEM_OP_CMD(0xd8, 1),				\
55 		   SPI_MEM_OP_ADDR(3, addr, 1),				\
56 		   SPI_MEM_OP_NO_DUMMY,					\
57 		   SPI_MEM_OP_NO_DATA)
58 
59 #define SPINAND_PAGE_READ_OP(addr)					\
60 	SPI_MEM_OP(SPI_MEM_OP_CMD(0x13, 1),				\
61 		   SPI_MEM_OP_ADDR(3, addr, 1),				\
62 		   SPI_MEM_OP_NO_DUMMY,					\
63 		   SPI_MEM_OP_NO_DATA)
64 
65 #define SPINAND_PAGE_READ_FROM_CACHE_OP(fast, addr, ndummy, buf, len)	\
66 	SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1),		\
67 		   SPI_MEM_OP_ADDR(2, addr, 1),				\
68 		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
69 		   SPI_MEM_OP_DATA_IN(len, buf, 1))
70 
71 #define SPINAND_PAGE_READ_FROM_CACHE_OP_3A(fast, addr, ndummy, buf, len) \
72 	SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1),		\
73 		   SPI_MEM_OP_ADDR(3, addr, 1),				\
74 		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
75 		   SPI_MEM_OP_DATA_IN(len, buf, 1))
76 
77 #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len)	\
78 	SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1),				\
79 		   SPI_MEM_OP_ADDR(2, addr, 1),				\
80 		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
81 		   SPI_MEM_OP_DATA_IN(len, buf, 2))
82 
83 #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(addr, ndummy, buf, len)	\
84 	SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1),				\
85 		   SPI_MEM_OP_ADDR(3, addr, 1),				\
86 		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
87 		   SPI_MEM_OP_DATA_IN(len, buf, 2))
88 
89 #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len)	\
90 	SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1),				\
91 		   SPI_MEM_OP_ADDR(2, addr, 1),				\
92 		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
93 		   SPI_MEM_OP_DATA_IN(len, buf, 4))
94 
95 #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(addr, ndummy, buf, len)	\
96 	SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1),				\
97 		   SPI_MEM_OP_ADDR(3, addr, 1),				\
98 		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
99 		   SPI_MEM_OP_DATA_IN(len, buf, 4))
100 
101 #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len)	\
102 	SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1),				\
103 		   SPI_MEM_OP_ADDR(2, addr, 2),				\
104 		   SPI_MEM_OP_DUMMY(ndummy, 2),				\
105 		   SPI_MEM_OP_DATA_IN(len, buf, 2))
106 
107 #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP_3A(addr, ndummy, buf, len) \
108 	SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1),				\
109 		   SPI_MEM_OP_ADDR(3, addr, 2),				\
110 		   SPI_MEM_OP_DUMMY(ndummy, 2),				\
111 		   SPI_MEM_OP_DATA_IN(len, buf, 2))
112 
113 #define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(addr, ndummy, buf, len)	\
114 	SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1),				\
115 		   SPI_MEM_OP_ADDR(2, addr, 4),				\
116 		   SPI_MEM_OP_DUMMY(ndummy, 4),				\
117 		   SPI_MEM_OP_DATA_IN(len, buf, 4))
118 
119 #define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP_3A(addr, ndummy, buf, len) \
120 	SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1),				\
121 		   SPI_MEM_OP_ADDR(3, addr, 4),				\
122 		   SPI_MEM_OP_DUMMY(ndummy, 4),				\
123 		   SPI_MEM_OP_DATA_IN(len, buf, 4))
124 
125 #define SPINAND_PROG_EXEC_OP(addr)					\
126 	SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1),				\
127 		   SPI_MEM_OP_ADDR(3, addr, 1),				\
128 		   SPI_MEM_OP_NO_DUMMY,					\
129 		   SPI_MEM_OP_NO_DATA)
130 
131 #define SPINAND_PROG_LOAD(reset, addr, buf, len)			\
132 	SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x02 : 0x84, 1),		\
133 		   SPI_MEM_OP_ADDR(2, addr, 1),				\
134 		   SPI_MEM_OP_NO_DUMMY,					\
135 		   SPI_MEM_OP_DATA_OUT(len, buf, 1))
136 
137 #define SPINAND_PROG_LOAD_X4(reset, addr, buf, len)			\
138 	SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 : 0x34, 1),		\
139 		   SPI_MEM_OP_ADDR(2, addr, 1),				\
140 		   SPI_MEM_OP_NO_DUMMY,					\
141 		   SPI_MEM_OP_DATA_OUT(len, buf, 4))
142 
143 /**
144  * Standard SPI NAND flash commands
145  */
146 #define SPINAND_CMD_PROG_LOAD_X4		0x32
147 #define SPINAND_CMD_PROG_LOAD_RDM_DATA_X4	0x34
148 
149 /* feature register */
150 #define REG_BLOCK_LOCK		0xa0
151 #define BL_ALL_UNLOCKED		0x00
152 
153 /* configuration register */
154 #define REG_CFG			0xb0
155 #define CFG_OTP_ENABLE		BIT(6)
156 #define CFG_ECC_ENABLE		BIT(4)
157 #define CFG_QUAD_ENABLE		BIT(0)
158 
159 /* status register */
160 #define REG_STATUS		0xc0
161 #define STATUS_BUSY		BIT(0)
162 #define STATUS_ERASE_FAILED	BIT(2)
163 #define STATUS_PROG_FAILED	BIT(3)
164 #define STATUS_ECC_MASK		GENMASK(5, 4)
165 #define STATUS_ECC_NO_BITFLIPS	(0 << 4)
166 #define STATUS_ECC_HAS_BITFLIPS	(1 << 4)
167 #define STATUS_ECC_UNCOR_ERROR	(2 << 4)
168 
169 struct spinand_op;
170 struct spinand_device;
171 
172 #define SPINAND_MAX_ID_LEN	4
173 /*
174  * For erase, write and read operation, we got the following timings :
175  * tBERS (erase) 1ms to 4ms
176  * tPROG 300us to 400us
177  * tREAD 25us to 100us
178  * In order to minimize latency, the min value is divided by 4 for the
179  * initial delay, and dividing by 20 for the poll delay.
180  * For reset, 5us/10us/500us if the device is respectively
181  * reading/programming/erasing when the RESET occurs. Since we always
182  * issue a RESET when the device is IDLE, 5us is selected for both initial
183  * and poll delay.
184  */
185 #define SPINAND_READ_INITIAL_DELAY_US	6
186 #define SPINAND_READ_POLL_DELAY_US	5
187 #define SPINAND_RESET_INITIAL_DELAY_US	5
188 #define SPINAND_RESET_POLL_DELAY_US	5
189 #define SPINAND_WRITE_INITIAL_DELAY_US	75
190 #define SPINAND_WRITE_POLL_DELAY_US	15
191 #define SPINAND_ERASE_INITIAL_DELAY_US	250
192 #define SPINAND_ERASE_POLL_DELAY_US	50
193 
194 #define SPINAND_WAITRDY_TIMEOUT_MS	400
195 
196 /**
197  * struct spinand_id - SPI NAND id structure
198  * @data: buffer containing the id bytes. Currently 4 bytes large, but can
199  *	  be extended if required
200  * @len: ID length
201  */
202 struct spinand_id {
203 	u8 data[SPINAND_MAX_ID_LEN];
204 	int len;
205 };
206 
207 enum spinand_readid_method {
208 	SPINAND_READID_METHOD_OPCODE,
209 	SPINAND_READID_METHOD_OPCODE_ADDR,
210 	SPINAND_READID_METHOD_OPCODE_DUMMY,
211 };
212 
213 /**
214  * struct spinand_devid - SPI NAND device id structure
215  * @id: device id of current chip
216  * @len: number of bytes in device id
217  * @method: method to read chip id
218  *	    There are 3 possible variants:
219  *	    SPINAND_READID_METHOD_OPCODE: chip id is returned immediately
220  *	    after read_id opcode.
221  *	    SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after
222  *	    read_id opcode + 1-byte address.
223  *	    SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after
224  *	    read_id opcode + 1 dummy byte.
225  */
226 struct spinand_devid {
227 	const u8 *id;
228 	const u8 len;
229 	const enum spinand_readid_method method;
230 };
231 
232 /**
233  * struct manufacurer_ops - SPI NAND manufacturer specific operations
234  * @init: initialize a SPI NAND device
235  * @cleanup: cleanup a SPI NAND device
236  *
237  * Each SPI NAND manufacturer driver should implement this interface so that
238  * NAND chips coming from this vendor can be initialized properly.
239  */
240 struct spinand_manufacturer_ops {
241 	int (*init)(struct spinand_device *spinand);
242 	void (*cleanup)(struct spinand_device *spinand);
243 };
244 
245 /**
246  * struct spinand_manufacturer - SPI NAND manufacturer instance
247  * @id: manufacturer ID
248  * @name: manufacturer name
249  * @devid_len: number of bytes in device ID
250  * @chips: supported SPI NANDs under current manufacturer
251  * @nchips: number of SPI NANDs available in chips array
252  * @ops: manufacturer operations
253  */
254 struct spinand_manufacturer {
255 	u8 id;
256 	char *name;
257 	const struct spinand_info *chips;
258 	const size_t nchips;
259 	const struct spinand_manufacturer_ops *ops;
260 };
261 
262 /* SPI NAND manufacturers */
263 extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
264 extern const struct spinand_manufacturer macronix_spinand_manufacturer;
265 extern const struct spinand_manufacturer micron_spinand_manufacturer;
266 extern const struct spinand_manufacturer paragon_spinand_manufacturer;
267 extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
268 extern const struct spinand_manufacturer winbond_spinand_manufacturer;
269 
270 /**
271  * struct spinand_op_variants - SPI NAND operation variants
272  * @ops: the list of variants for a given operation
273  * @nops: the number of variants
274  *
275  * Some operations like read-from-cache/write-to-cache have several variants
276  * depending on the number of IO lines you use to transfer data or address
277  * cycles. This structure is a way to describe the different variants supported
278  * by a chip and let the core pick the best one based on the SPI mem controller
279  * capabilities.
280  */
281 struct spinand_op_variants {
282 	const struct spi_mem_op *ops;
283 	unsigned int nops;
284 };
285 
286 #define SPINAND_OP_VARIANTS(name, ...)					\
287 	const struct spinand_op_variants name = {			\
288 		.ops = (struct spi_mem_op[]) { __VA_ARGS__ },		\
289 		.nops = sizeof((struct spi_mem_op[]){ __VA_ARGS__ }) /	\
290 			sizeof(struct spi_mem_op),			\
291 	}
292 
293 /**
294  * spinand_ecc_info - description of the on-die ECC implemented by a SPI NAND
295  *		      chip
296  * @get_status: get the ECC status. Should return a positive number encoding
297  *		the number of corrected bitflips if correction was possible or
298  *		-EBADMSG if there are uncorrectable errors. I can also return
299  *		other negative error codes if the error is not caused by
300  *		uncorrectable bitflips
301  * @ooblayout: the OOB layout used by the on-die ECC implementation
302  */
303 struct spinand_ecc_info {
304 	int (*get_status)(struct spinand_device *spinand, u8 status);
305 	const struct mtd_ooblayout_ops *ooblayout;
306 };
307 
308 #define SPINAND_HAS_QE_BIT		BIT(0)
309 #define SPINAND_HAS_CR_FEAT_BIT		BIT(1)
310 
311 /**
312  * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure
313  * @status: status of the last wait operation that will be used in case
314  *          ->get_status() is not populated by the spinand device.
315  */
316 struct spinand_ondie_ecc_conf {
317 	u8 status;
318 };
319 
320 /**
321  * struct spinand_info - Structure used to describe SPI NAND chips
322  * @model: model name
323  * @devid: device ID
324  * @flags: OR-ing of the SPINAND_XXX flags
325  * @memorg: memory organization
326  * @eccreq: ECC requirements
327  * @eccinfo: on-die ECC info
328  * @op_variants: operations variants
329  * @op_variants.read_cache: variants of the read-cache operation
330  * @op_variants.write_cache: variants of the write-cache operation
331  * @op_variants.update_cache: variants of the update-cache operation
332  * @select_target: function used to select a target/die. Required only for
333  *		   multi-die chips
334  *
335  * Each SPI NAND manufacturer driver should have a spinand_info table
336  * describing all the chips supported by the driver.
337  */
338 struct spinand_info {
339 	const char *model;
340 	struct spinand_devid devid;
341 	u32 flags;
342 	struct nand_memory_organization memorg;
343 	struct nand_ecc_props eccreq;
344 	struct spinand_ecc_info eccinfo;
345 	struct {
346 		const struct spinand_op_variants *read_cache;
347 		const struct spinand_op_variants *write_cache;
348 		const struct spinand_op_variants *update_cache;
349 	} op_variants;
350 	int (*select_target)(struct spinand_device *spinand,
351 			     unsigned int target);
352 };
353 
354 #define SPINAND_ID(__method, ...)					\
355 	{								\
356 		.id = (const u8[]){ __VA_ARGS__ },			\
357 		.len = sizeof((u8[]){ __VA_ARGS__ }),			\
358 		.method = __method,					\
359 	}
360 
361 #define SPINAND_INFO_OP_VARIANTS(__read, __write, __update)		\
362 	{								\
363 		.read_cache = __read,					\
364 		.write_cache = __write,					\
365 		.update_cache = __update,				\
366 	}
367 
368 #define SPINAND_ECCINFO(__ooblayout, __get_status)			\
369 	.eccinfo = {							\
370 		.ooblayout = __ooblayout,				\
371 		.get_status = __get_status,				\
372 	}
373 
374 #define SPINAND_SELECT_TARGET(__func)					\
375 	.select_target = __func,
376 
377 #define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants,	\
378 		     __flags, ...)					\
379 	{								\
380 		.model = __model,					\
381 		.devid = __id,						\
382 		.memorg = __memorg,					\
383 		.eccreq = __eccreq,					\
384 		.op_variants = __op_variants,				\
385 		.flags = __flags,					\
386 		__VA_ARGS__						\
387 	}
388 
389 struct spinand_dirmap {
390 	struct spi_mem_dirmap_desc *wdesc;
391 	struct spi_mem_dirmap_desc *rdesc;
392 };
393 
394 /**
395  * struct spinand_device - SPI NAND device instance
396  * @base: NAND device instance
397  * @spimem: pointer to the SPI mem object
398  * @lock: lock used to serialize accesses to the NAND
399  * @id: NAND ID as returned by READ_ID
400  * @flags: NAND flags
401  * @op_templates: various SPI mem op templates
402  * @op_templates.read_cache: read cache op template
403  * @op_templates.write_cache: write cache op template
404  * @op_templates.update_cache: update cache op template
405  * @select_target: select a specific target/die. Usually called before sending
406  *		   a command addressing a page or an eraseblock embedded in
407  *		   this die. Only required if your chip exposes several dies
408  * @cur_target: currently selected target/die
409  * @eccinfo: on-die ECC information
410  * @cfg_cache: config register cache. One entry per die
411  * @databuf: bounce buffer for data
412  * @oobbuf: bounce buffer for OOB data
413  * @scratchbuf: buffer used for everything but page accesses. This is needed
414  *		because the spi-mem interface explicitly requests that buffers
415  *		passed in spi_mem_op be DMA-able, so we can't based the bufs on
416  *		the stack
417  * @manufacturer: SPI NAND manufacturer information
418  * @priv: manufacturer private data
419  */
420 struct spinand_device {
421 	struct nand_device base;
422 	struct spi_mem *spimem;
423 	struct mutex lock;
424 	struct spinand_id id;
425 	u32 flags;
426 
427 	struct {
428 		const struct spi_mem_op *read_cache;
429 		const struct spi_mem_op *write_cache;
430 		const struct spi_mem_op *update_cache;
431 	} op_templates;
432 
433 	struct spinand_dirmap *dirmaps;
434 
435 	int (*select_target)(struct spinand_device *spinand,
436 			     unsigned int target);
437 	unsigned int cur_target;
438 
439 	struct spinand_ecc_info eccinfo;
440 
441 	u8 *cfg_cache;
442 	u8 *databuf;
443 	u8 *oobbuf;
444 	u8 *scratchbuf;
445 	const struct spinand_manufacturer *manufacturer;
446 	void *priv;
447 };
448 
449 /**
450  * mtd_to_spinand() - Get the SPI NAND device attached to an MTD instance
451  * @mtd: MTD instance
452  *
453  * Return: the SPI NAND device attached to @mtd.
454  */
mtd_to_spinand(struct mtd_info * mtd)455 static inline struct spinand_device *mtd_to_spinand(struct mtd_info *mtd)
456 {
457 	return container_of(mtd_to_nanddev(mtd), struct spinand_device, base);
458 }
459 
460 /**
461  * spinand_to_mtd() - Get the MTD device embedded in a SPI NAND device
462  * @spinand: SPI NAND device
463  *
464  * Return: the MTD device embedded in @spinand.
465  */
spinand_to_mtd(struct spinand_device * spinand)466 static inline struct mtd_info *spinand_to_mtd(struct spinand_device *spinand)
467 {
468 	return nanddev_to_mtd(&spinand->base);
469 }
470 
471 /**
472  * nand_to_spinand() - Get the SPI NAND device embedding an NAND object
473  * @nand: NAND object
474  *
475  * Return: the SPI NAND device embedding @nand.
476  */
nand_to_spinand(struct nand_device * nand)477 static inline struct spinand_device *nand_to_spinand(struct nand_device *nand)
478 {
479 	return container_of(nand, struct spinand_device, base);
480 }
481 
482 /**
483  * spinand_to_nand() - Get the NAND device embedded in a SPI NAND object
484  * @spinand: SPI NAND device
485  *
486  * Return: the NAND device embedded in @spinand.
487  */
488 static inline struct nand_device *
spinand_to_nand(struct spinand_device * spinand)489 spinand_to_nand(struct spinand_device *spinand)
490 {
491 	return &spinand->base;
492 }
493 
494 /**
495  * spinand_set_of_node - Attach a DT node to a SPI NAND device
496  * @spinand: SPI NAND device
497  * @np: DT node
498  *
499  * Attach a DT node to a SPI NAND device.
500  */
spinand_set_of_node(struct spinand_device * spinand,struct device_node * np)501 static inline void spinand_set_of_node(struct spinand_device *spinand,
502 				       struct device_node *np)
503 {
504 	nanddev_set_of_node(&spinand->base, np);
505 }
506 
507 int spinand_match_and_init(struct spinand_device *spinand,
508 			   const struct spinand_info *table,
509 			   unsigned int table_size,
510 			   enum spinand_readid_method rdid_method);
511 
512 int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val);
513 int spinand_select_target(struct spinand_device *spinand, unsigned int target);
514 
515 #endif /* __LINUX_MTD_SPINAND_H */
516