1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 */
5
6 #ifndef __LINUX_MTD_SPI_NOR_H
7 #define __LINUX_MTD_SPI_NOR_H
8
9 #include <linux/bitops.h>
10 #include <linux/mtd/cfi.h>
11 #include <linux/mtd/mtd.h>
12 #include <linux/spi/spi-mem.h>
13
14 /*
15 * Note on opcode nomenclature: some opcodes have a format like
16 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
17 * of I/O lines used for the opcode, address, and data (respectively). The
18 * FUNCTION has an optional suffix of '4', to represent an opcode which
19 * requires a 4-byte (32-bit) address.
20 */
21
22 /* Flash opcodes. */
23 #define SPINOR_OP_WRDI 0x04 /* Write disable */
24 #define SPINOR_OP_WREN 0x06 /* Write enable */
25 #define SPINOR_OP_RDSR 0x05 /* Read status register */
26 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
27 #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
28 #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
29 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
30 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
31 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
32 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
33 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
34 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
35 #define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
36 #define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
37 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
38 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
39 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
40 #define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
41 #define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
42 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
43 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
44 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
45 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
46 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
47 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
48 #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
49 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */
50 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
51 #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
52 #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
53 #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
54 #define SPINOR_OP_SRSTEN 0x66 /* Software Reset Enable */
55 #define SPINOR_OP_SRST 0x99 /* Software Reset */
56 #define SPINOR_OP_GBULK 0x98 /* Global Block Unlock */
57
58 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
59 #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
60 #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
61 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
62 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
63 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
64 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
65 #define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
66 #define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
67 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
68 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
69 #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
70 #define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
71 #define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
72 #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
73 #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
74 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
75
76 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
77 #define SPINOR_OP_READ_1_1_1_DTR 0x0d
78 #define SPINOR_OP_READ_1_2_2_DTR 0xbd
79 #define SPINOR_OP_READ_1_4_4_DTR 0xed
80
81 #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
82 #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
83 #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
84
85 /* Used for SST flashes only. */
86 #define SPINOR_OP_BP 0x02 /* Byte program */
87 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
88
89 /* Used for S3AN flashes only */
90 #define SPINOR_OP_XSE 0x50 /* Sector erase */
91 #define SPINOR_OP_XPP 0x82 /* Page program */
92 #define SPINOR_OP_XRDSR 0xd7 /* Read status register */
93
94 #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
95 #define XSR_RDY BIT(7) /* Ready */
96
97
98 /* Used for Macronix and Winbond flashes. */
99 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
100 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
101
102 /* Used for Spansion flashes only. */
103 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
104 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
105
106 /* Used for Micron flashes only. */
107 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
108 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
109
110 /* Used for GigaDevices and Winbond flashes. */
111 #define SPINOR_OP_ESECR 0x44 /* Erase Security registers */
112 #define SPINOR_OP_PSECR 0x42 /* Program Security registers */
113 #define SPINOR_OP_RSECR 0x48 /* Read Security registers */
114
115 /* Status Register bits. */
116 #define SR_WIP BIT(0) /* Write in progress */
117 #define SR_WEL BIT(1) /* Write enable latch */
118 /* meaning of other SR_* bits may differ between vendors */
119 #define SR_BP0 BIT(2) /* Block protect 0 */
120 #define SR_BP1 BIT(3) /* Block protect 1 */
121 #define SR_BP2 BIT(4) /* Block protect 2 */
122 #define SR_BP3 BIT(5) /* Block protect 3 */
123 #define SR_TB_BIT5 BIT(5) /* Top/Bottom protect */
124 #define SR_BP3_BIT6 BIT(6) /* Block protect 3 */
125 #define SR_TB_BIT6 BIT(6) /* Top/Bottom protect */
126 #define SR_SRWD BIT(7) /* SR write protect */
127 /* Spansion/Cypress specific status bits */
128 #define SR_E_ERR BIT(5)
129 #define SR_P_ERR BIT(6)
130
131 #define SR1_QUAD_EN_BIT6 BIT(6)
132
133 #define SR_BP_SHIFT 2
134
135 /* Enhanced Volatile Configuration Register bits */
136 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
137
138 /* Flag Status Register bits */
139 #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
140 #define FSR_E_ERR BIT(5) /* Erase operation status */
141 #define FSR_P_ERR BIT(4) /* Program operation status */
142 #define FSR_PT_ERR BIT(1) /* Protection error bit */
143
144 /* Status Register 2 bits. */
145 #define SR2_QUAD_EN_BIT1 BIT(1)
146 #define SR2_LB1 BIT(3) /* Security Register Lock Bit 1 */
147 #define SR2_LB2 BIT(4) /* Security Register Lock Bit 2 */
148 #define SR2_LB3 BIT(5) /* Security Register Lock Bit 3 */
149 #define SR2_QUAD_EN_BIT7 BIT(7)
150
151 /* Supported SPI protocols */
152 #define SNOR_PROTO_INST_MASK GENMASK(23, 16)
153 #define SNOR_PROTO_INST_SHIFT 16
154 #define SNOR_PROTO_INST(_nbits) \
155 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
156 SNOR_PROTO_INST_MASK)
157
158 #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
159 #define SNOR_PROTO_ADDR_SHIFT 8
160 #define SNOR_PROTO_ADDR(_nbits) \
161 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
162 SNOR_PROTO_ADDR_MASK)
163
164 #define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
165 #define SNOR_PROTO_DATA_SHIFT 0
166 #define SNOR_PROTO_DATA(_nbits) \
167 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
168 SNOR_PROTO_DATA_MASK)
169
170 #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
171
172 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
173 (SNOR_PROTO_INST(_inst_nbits) | \
174 SNOR_PROTO_ADDR(_addr_nbits) | \
175 SNOR_PROTO_DATA(_data_nbits))
176 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
177 (SNOR_PROTO_IS_DTR | \
178 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
179
180 enum spi_nor_protocol {
181 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
182 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
183 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
184 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
185 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
186 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
187 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
188 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
189 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
190 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
191
192 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
193 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
194 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
195 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
196 SNOR_PROTO_8_8_8_DTR = SNOR_PROTO_DTR(8, 8, 8),
197 };
198
spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)199 static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
200 {
201 return !!(proto & SNOR_PROTO_IS_DTR);
202 }
203
spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)204 static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
205 {
206 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
207 SNOR_PROTO_INST_SHIFT;
208 }
209
spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)210 static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
211 {
212 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
213 SNOR_PROTO_ADDR_SHIFT;
214 }
215
spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)216 static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
217 {
218 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
219 SNOR_PROTO_DATA_SHIFT;
220 }
221
spi_nor_get_protocol_width(enum spi_nor_protocol proto)222 static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
223 {
224 return spi_nor_get_protocol_data_nbits(proto);
225 }
226
227 /**
228 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
229 * supported by the SPI controller (bus master).
230 * @mask: the bitmask listing all the supported hw capabilies
231 */
232 struct spi_nor_hwcaps {
233 u32 mask;
234 };
235
236 /*
237 *(Fast) Read capabilities.
238 * MUST be ordered by priority: the higher bit position, the higher priority.
239 * As a matter of performances, it is relevant to use Octal SPI protocols first,
240 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
241 * (Slow) Read.
242 */
243 #define SNOR_HWCAPS_READ_MASK GENMASK(15, 0)
244 #define SNOR_HWCAPS_READ BIT(0)
245 #define SNOR_HWCAPS_READ_FAST BIT(1)
246 #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
247
248 #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
249 #define SNOR_HWCAPS_READ_1_1_2 BIT(3)
250 #define SNOR_HWCAPS_READ_1_2_2 BIT(4)
251 #define SNOR_HWCAPS_READ_2_2_2 BIT(5)
252 #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
253
254 #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
255 #define SNOR_HWCAPS_READ_1_1_4 BIT(7)
256 #define SNOR_HWCAPS_READ_1_4_4 BIT(8)
257 #define SNOR_HWCAPS_READ_4_4_4 BIT(9)
258 #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
259
260 #define SNOR_HWCAPS_READ_OCTAL GENMASK(15, 11)
261 #define SNOR_HWCAPS_READ_1_1_8 BIT(11)
262 #define SNOR_HWCAPS_READ_1_8_8 BIT(12)
263 #define SNOR_HWCAPS_READ_8_8_8 BIT(13)
264 #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
265 #define SNOR_HWCAPS_READ_8_8_8_DTR BIT(15)
266
267 /*
268 * Page Program capabilities.
269 * MUST be ordered by priority: the higher bit position, the higher priority.
270 * Like (Fast) Read capabilities, Octal/Quad SPI protocols are preferred to the
271 * legacy SPI 1-1-1 protocol.
272 * Note that Dual Page Programs are not supported because there is no existing
273 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
274 * implements such commands.
275 */
276 #define SNOR_HWCAPS_PP_MASK GENMASK(23, 16)
277 #define SNOR_HWCAPS_PP BIT(16)
278
279 #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
280 #define SNOR_HWCAPS_PP_1_1_4 BIT(17)
281 #define SNOR_HWCAPS_PP_1_4_4 BIT(18)
282 #define SNOR_HWCAPS_PP_4_4_4 BIT(19)
283
284 #define SNOR_HWCAPS_PP_OCTAL GENMASK(23, 20)
285 #define SNOR_HWCAPS_PP_1_1_8 BIT(20)
286 #define SNOR_HWCAPS_PP_1_8_8 BIT(21)
287 #define SNOR_HWCAPS_PP_8_8_8 BIT(22)
288 #define SNOR_HWCAPS_PP_8_8_8_DTR BIT(23)
289
290 #define SNOR_HWCAPS_X_X_X (SNOR_HWCAPS_READ_2_2_2 | \
291 SNOR_HWCAPS_READ_4_4_4 | \
292 SNOR_HWCAPS_READ_8_8_8 | \
293 SNOR_HWCAPS_PP_4_4_4 | \
294 SNOR_HWCAPS_PP_8_8_8)
295
296 #define SNOR_HWCAPS_X_X_X_DTR (SNOR_HWCAPS_READ_8_8_8_DTR | \
297 SNOR_HWCAPS_PP_8_8_8_DTR)
298
299 #define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1_1_DTR | \
300 SNOR_HWCAPS_READ_1_2_2_DTR | \
301 SNOR_HWCAPS_READ_1_4_4_DTR | \
302 SNOR_HWCAPS_READ_1_8_8_DTR | \
303 SNOR_HWCAPS_READ_8_8_8_DTR)
304
305 #define SNOR_HWCAPS_ALL (SNOR_HWCAPS_READ_MASK | \
306 SNOR_HWCAPS_PP_MASK)
307
308 /* Forward declaration that is used in 'struct spi_nor_controller_ops' */
309 struct spi_nor;
310
311 /**
312 * struct spi_nor_controller_ops - SPI NOR controller driver specific
313 * operations.
314 * @prepare: [OPTIONAL] do some preparations for the
315 * read/write/erase/lock/unlock operations.
316 * @unprepare: [OPTIONAL] do some post work after the
317 * read/write/erase/lock/unlock operations.
318 * @read_reg: read out the register.
319 * @write_reg: write data to the register.
320 * @read: read data from the SPI NOR.
321 * @write: write data to the SPI NOR.
322 * @erase: erase a sector of the SPI NOR at the offset @offs; if
323 * not provided by the driver, SPI NOR will send the erase
324 * opcode via write_reg().
325 */
326 struct spi_nor_controller_ops {
327 int (*prepare)(struct spi_nor *nor);
328 void (*unprepare)(struct spi_nor *nor);
329 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len);
330 int (*write_reg)(struct spi_nor *nor, u8 opcode, const u8 *buf,
331 size_t len);
332
333 ssize_t (*read)(struct spi_nor *nor, loff_t from, size_t len, u8 *buf);
334 ssize_t (*write)(struct spi_nor *nor, loff_t to, size_t len,
335 const u8 *buf);
336 int (*erase)(struct spi_nor *nor, loff_t offs);
337 };
338
339 /**
340 * enum spi_nor_cmd_ext - describes the command opcode extension in DTR mode
341 * @SPI_NOR_EXT_NONE: no extension. This is the default, and is used in Legacy
342 * SPI mode
343 * @SPI_NOR_EXT_REPEAT: the extension is same as the opcode
344 * @SPI_NOR_EXT_INVERT: the extension is the bitwise inverse of the opcode
345 * @SPI_NOR_EXT_HEX: the extension is any hex value. The command and opcode
346 * combine to form a 16-bit opcode.
347 */
348 enum spi_nor_cmd_ext {
349 SPI_NOR_EXT_NONE = 0,
350 SPI_NOR_EXT_REPEAT,
351 SPI_NOR_EXT_INVERT,
352 SPI_NOR_EXT_HEX,
353 };
354
355 /*
356 * Forward declarations that are used internally by the core and manufacturer
357 * drivers.
358 */
359 struct flash_info;
360 struct spi_nor_manufacturer;
361 struct spi_nor_flash_parameter;
362
363 /**
364 * struct spi_nor - Structure for defining the SPI NOR layer
365 * @mtd: an mtd_info structure
366 * @lock: the lock for the read/write/erase/lock/unlock operations
367 * @dev: pointer to an SPI device or an SPI NOR controller device
368 * @spimem: pointer to the SPI memory device
369 * @bouncebuf: bounce buffer used when the buffer passed by the MTD
370 * layer is not DMA-able
371 * @bouncebuf_size: size of the bounce buffer
372 * @info: SPI NOR part JEDEC MFR ID and other info
373 * @manufacturer: SPI NOR manufacturer
374 * @page_size: the page size of the SPI NOR
375 * @addr_width: number of address bytes
376 * @erase_opcode: the opcode for erasing a sector
377 * @read_opcode: the read opcode
378 * @read_dummy: the dummy needed by the read operation
379 * @program_opcode: the program opcode
380 * @sst_write_second: used by the SST write operation
381 * @flags: flag options for the current SPI NOR (SNOR_F_*)
382 * @cmd_ext_type: the command opcode extension type for DTR mode.
383 * @read_proto: the SPI protocol for read operations
384 * @write_proto: the SPI protocol for write operations
385 * @reg_proto: the SPI protocol for read_reg/write_reg/erase operations
386 * @sfdp: the SFDP data of the flash
387 * @controller_ops: SPI NOR controller driver specific operations.
388 * @params: [FLASH-SPECIFIC] SPI NOR flash parameters and settings.
389 * The structure includes legacy flash parameters and
390 * settings that can be overwritten by the spi_nor_fixups
391 * hooks, or dynamically when parsing the SFDP tables.
392 * @dirmap: pointers to struct spi_mem_dirmap_desc for reads/writes.
393 * @priv: pointer to the private data
394 */
395 struct spi_nor {
396 struct mtd_info mtd;
397 struct mutex lock;
398 struct device *dev;
399 struct spi_mem *spimem;
400 u8 *bouncebuf;
401 size_t bouncebuf_size;
402 const struct flash_info *info;
403 const struct spi_nor_manufacturer *manufacturer;
404 u32 page_size;
405 u8 addr_width;
406 u8 erase_opcode;
407 u8 read_opcode;
408 u8 read_dummy;
409 u8 program_opcode;
410 enum spi_nor_protocol read_proto;
411 enum spi_nor_protocol write_proto;
412 enum spi_nor_protocol reg_proto;
413 bool sst_write_second;
414 u32 flags;
415 enum spi_nor_cmd_ext cmd_ext_type;
416 struct sfdp *sfdp;
417
418 const struct spi_nor_controller_ops *controller_ops;
419
420 struct spi_nor_flash_parameter *params;
421
422 struct {
423 struct spi_mem_dirmap_desc *rdesc;
424 struct spi_mem_dirmap_desc *wdesc;
425 } dirmap;
426
427 void *priv;
428 };
429
spi_nor_set_flash_node(struct spi_nor * nor,struct device_node * np)430 static inline void spi_nor_set_flash_node(struct spi_nor *nor,
431 struct device_node *np)
432 {
433 mtd_set_of_node(&nor->mtd, np);
434 }
435
spi_nor_get_flash_node(struct spi_nor * nor)436 static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
437 {
438 return mtd_get_of_node(&nor->mtd);
439 }
440
441 /**
442 * spi_nor_scan() - scan the SPI NOR
443 * @nor: the spi_nor structure
444 * @name: the chip type name
445 * @hwcaps: the hardware capabilities supported by the controller driver
446 *
447 * The drivers can use this function to scan the SPI NOR.
448 * In the scanning, it will try to get all the necessary information to
449 * fill the mtd_info{} and the spi_nor{}.
450 *
451 * The chip type name can be provided through the @name parameter.
452 *
453 * Return: 0 for success, others for failure.
454 */
455 int spi_nor_scan(struct spi_nor *nor, const char *name,
456 const struct spi_nor_hwcaps *hwcaps);
457
458 /**
459 * spi_nor_restore_addr_mode() - restore the status of SPI NOR
460 * @nor: the spi_nor structure
461 */
462 void spi_nor_restore(struct spi_nor *nor);
463
464 #endif
465