1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2019 Intel Corporation <www.intel.com> 4 */ 5 6 #ifndef _SYSTEM_MANAGER_SOC64_H_ 7 #define _SYSTEM_MANAGER_SOC64_H_ 8 9 #include <linux/bitops.h> 10 void sysmgr_pinmux_init(void); 11 void populate_sysmgr_fpgaintf_module(void); 12 void populate_sysmgr_pinmux(void); 13 void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len); 14 void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len); 15 void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len); 16 void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len); 17 18 #define SYSMGR_SOC64_WDDBG 0x08 19 #define SYSMGR_SOC64_DMA 0x20 20 #define SYSMGR_SOC64_DMA_PERIPH 0x24 21 #define SYSMGR_SOC64_SDMMC 0x28 22 #define SYSMGR_SOC64_SDMMC_L3MASTER 0x2c 23 #define SYSMGR_SOC64_EMAC_GLOBAL 0x40 24 #define SYSMGR_SOC64_EMAC0 0x44 25 #define SYSMGR_SOC64_EMAC1 0x48 26 #define SYSMGR_SOC64_EMAC2 0x4c 27 #define SYSMGR_SOC64_EMAC0_ACE 0x50 28 #define SYSMGR_SOC64_EMAC1_ACE 0x54 29 #define SYSMGR_SOC64_EMAC2_ACE 0x58 30 #define SYSMGR_SOC64_NAND_AXUSER 0x5c 31 #define SYSMGR_SOC64_FPGAINTF_EN1 0x68 32 #define SYSMGR_SOC64_FPGAINTF_EN2 0x6c 33 #define SYSMGR_SOC64_FPGAINTF_EN3 0x70 34 #define SYSMGR_SOC64_DMA_L3MASTER 0x74 35 #define SYSMGR_SOC64_HMC_CLK 0xb4 36 #define SYSMGR_SOC64_IO_PA_CTRL 0xb8 37 #define SYSMGR_SOC64_NOC_TIMEOUT 0xc0 38 #define SYSMGR_SOC64_NOC_IDLEREQ_SET 0xc4 39 #define SYSMGR_SOC64_NOC_IDLEREQ_CLR 0xc8 40 #define SYSMGR_SOC64_NOC_IDLEREQ_VAL 0xcc 41 #define SYSMGR_SOC64_NOC_IDLEACK 0xd0 42 #define SYSMGR_SOC64_NOC_IDLESTATUS 0xd4 43 #define SYSMGR_SOC64_FPGA2SOC_CTRL 0xd8 44 #define SYSMGR_SOC64_FPGA_CONFIG 0xdc 45 #define SYSMGR_SOC64_IOCSRCLK_GATE 0xe0 46 #define SYSMGR_SOC64_GPO 0xe4 47 #define SYSMGR_SOC64_GPI 0xe8 48 #define SYSMGR_SOC64_MPU 0xf0 49 /* store qspi ref clock */ 50 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200 51 /* store osc1 clock freq */ 52 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204 53 /* store fpga clock freq */ 54 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD2 0x208 55 /* reserved for customer use */ 56 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD3 0x20c 57 /* store PSCI_CPU_ON value */ 58 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD4 0x210 59 /* store PSCI_CPU_ON value */ 60 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD5 0x214 61 /* store VBAR_EL3 value */ 62 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD6 0x218 63 /* store VBAR_EL3 value */ 64 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD7 0x21c 65 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD8 0x220 66 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD9 0x224 67 #define SYSMGR_SOC64_PINSEL0 0x1000 68 #define SYSMGR_SOC64_IOCTRL0 0x1130 69 #define SYSMGR_SOC64_EMAC0_USEFPGA 0x1300 70 #define SYSMGR_SOC64_EMAC1_USEFPGA 0x1304 71 #define SYSMGR_SOC64_EMAC2_USEFPGA 0x1308 72 #define SYSMGR_SOC64_I2C0_USEFPGA 0x130c 73 #define SYSMGR_SOC64_I2C1_USEFPGA 0x1310 74 #define SYSMGR_SOC64_I2C_EMAC0_USEFPGA 0x1314 75 #define SYSMGR_SOC64_I2C_EMAC1_USEFPGA 0x1318 76 #define SYSMGR_SOC64_I2C_EMAC2_USEFPGA 0x131c 77 #define SYSMGR_SOC64_NAND_USEFPGA 0x1320 78 #define SYSMGR_SOC64_SPIM0_USEFPGA 0x1328 79 #define SYSMGR_SOC64_SPIM1_USEFPGA 0x132c 80 #define SYSMGR_SOC64_SPIS0_USEFPGA 0x1330 81 #define SYSMGR_SOC64_SPIS1_USEFPGA 0x1334 82 #define SYSMGR_SOC64_UART0_USEFPGA 0x1338 83 #define SYSMGR_SOC64_UART1_USEFPGA 0x133c 84 #define SYSMGR_SOC64_MDIO0_USEFPGA 0x1340 85 #define SYSMGR_SOC64_MDIO1_USEFPGA 0x1344 86 #define SYSMGR_SOC64_MDIO2_USEFPGA 0x1348 87 #define SYSMGR_SOC64_JTAG_USEFPGA 0x1350 88 #define SYSMGR_SOC64_SDMMC_USEFPGA 0x1354 89 #define SYSMGR_SOC64_HPS_OSC_CLK 0x1358 90 #define SYSMGR_SOC64_IODELAY0 0x1400 91 92 #define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC 93 94 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) 95 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1) 96 #define SYSMGR_ECC_OCRAM_EN BIT(0) 97 #define SYSMGR_ECC_OCRAM_SERR BIT(3) 98 #define SYSMGR_ECC_OCRAM_DERR BIT(4) 99 #define SYSMGR_FPGACONFIG_FPGA_COMPLETE BIT(0) 100 #define SYSMGR_FPGACONFIG_EARLY_USERMODE BIT(1) 101 #define SYSMGR_FPGACONFIG_READY_MASK (SYSMGR_FPGACONFIG_FPGA_COMPLETE | \ 102 SYSMGR_FPGACONFIG_EARLY_USERMODE) 103 104 #define SYSMGR_FPGAINTF_USEFPGA 0x1 105 #define SYSMGR_FPGAINTF_NAND BIT(4) 106 #define SYSMGR_FPGAINTF_SDMMC BIT(8) 107 #define SYSMGR_FPGAINTF_SPIM0 BIT(16) 108 #define SYSMGR_FPGAINTF_SPIM1 BIT(24) 109 #define SYSMGR_FPGAINTF_EMAC0 BIT(0) 110 #define SYSMGR_FPGAINTF_EMAC1 BIT(8) 111 #define SYSMGR_FPGAINTF_EMAC2 BIT(16) 112 113 #define SYSMGR_SDMMC_SMPLSEL_SHIFT 4 114 #define SYSMGR_SDMMC_DRVSEL_SHIFT 0 115 116 /* EMAC Group Bit definitions */ 117 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 118 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 119 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 120 121 #define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0 122 #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 123 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3 124 125 #define SYSMGR_NOC_H2F_MSK 0x00000001 126 #define SYSMGR_NOC_LWH2F_MSK 0x00000010 127 #define SYSMGR_HMC_CLK_STATUS_MSK 0x00000001 128 129 #define SYSMGR_DMA_IRQ_NS 0xFF000000 130 #define SYSMGR_DMA_MGR_NS 0x00010000 131 132 #define SYSMGR_DMAPERIPH_ALL_NS 0xFFFFFFFF 133 134 #define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F 135 136 #endif /* _SYSTEM_MANAGER_SOC64_H_ */ 137