1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #ifndef __DML2_DISPLAY_MODE_VBA_H__ 28 #define __DML2_DISPLAY_MODE_VBA_H__ 29 30 struct display_mode_lib; 31 32 void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib); 33 34 #define dml_get_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes) 35 36 dml_get_attr_decl(clk_dcf_deepsleep); 37 dml_get_attr_decl(wm_urgent); 38 dml_get_attr_decl(wm_memory_trip); 39 dml_get_attr_decl(wm_writeback_urgent); 40 dml_get_attr_decl(wm_stutter_exit); 41 dml_get_attr_decl(wm_stutter_enter_exit); 42 dml_get_attr_decl(wm_z8_stutter_exit); 43 dml_get_attr_decl(wm_z8_stutter_enter_exit); 44 dml_get_attr_decl(stutter_efficiency_z8); 45 dml_get_attr_decl(stutter_num_bursts_z8); 46 dml_get_attr_decl(wm_dram_clock_change); 47 dml_get_attr_decl(wm_writeback_dram_clock_change); 48 dml_get_attr_decl(stutter_efficiency_no_vblank); 49 dml_get_attr_decl(stutter_efficiency); 50 dml_get_attr_decl(stutter_period); 51 dml_get_attr_decl(urgent_latency); 52 dml_get_attr_decl(urgent_extra_latency); 53 dml_get_attr_decl(nonurgent_latency); 54 dml_get_attr_decl(dram_clock_change_latency); 55 dml_get_attr_decl(dispclk_calculated); 56 dml_get_attr_decl(total_data_read_bw); 57 dml_get_attr_decl(return_bw); 58 dml_get_attr_decl(tcalc); 59 dml_get_attr_decl(fraction_of_urgent_bandwidth); 60 dml_get_attr_decl(fraction_of_urgent_bandwidth_imm_flip); 61 62 #define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe) 63 64 dml_get_pipe_attr_decl(dsc_delay); 65 dml_get_pipe_attr_decl(dppclk_calculated); 66 dml_get_pipe_attr_decl(dscclk_calculated); 67 dml_get_pipe_attr_decl(min_ttu_vblank); 68 dml_get_pipe_attr_decl(min_ttu_vblank_in_us); 69 dml_get_pipe_attr_decl(vratio_prefetch_l); 70 dml_get_pipe_attr_decl(vratio_prefetch_c); 71 dml_get_pipe_attr_decl(dst_x_after_scaler); 72 dml_get_pipe_attr_decl(dst_y_after_scaler); 73 dml_get_pipe_attr_decl(dst_y_per_vm_vblank); 74 dml_get_pipe_attr_decl(dst_y_per_row_vblank); 75 dml_get_pipe_attr_decl(dst_y_prefetch); 76 dml_get_pipe_attr_decl(dst_y_per_vm_flip); 77 dml_get_pipe_attr_decl(dst_y_per_row_flip); 78 dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank); 79 dml_get_pipe_attr_decl(refcyc_per_vm_group_flip); 80 dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank); 81 dml_get_pipe_attr_decl(refcyc_per_vm_req_flip); 82 dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank_in_us); 83 dml_get_pipe_attr_decl(refcyc_per_vm_group_flip_in_us); 84 dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank_in_us); 85 dml_get_pipe_attr_decl(refcyc_per_vm_req_flip_in_us); 86 dml_get_pipe_attr_decl(refcyc_per_vm_dmdata_in_us); 87 dml_get_pipe_attr_decl(dmdata_dl_delta_in_us); 88 dml_get_pipe_attr_decl(refcyc_per_line_delivery_l_in_us); 89 dml_get_pipe_attr_decl(refcyc_per_line_delivery_c_in_us); 90 dml_get_pipe_attr_decl(refcyc_per_line_delivery_pre_l_in_us); 91 dml_get_pipe_attr_decl(refcyc_per_line_delivery_pre_c_in_us); 92 dml_get_pipe_attr_decl(refcyc_per_req_delivery_l_in_us); 93 dml_get_pipe_attr_decl(refcyc_per_req_delivery_c_in_us); 94 dml_get_pipe_attr_decl(refcyc_per_req_delivery_pre_l_in_us); 95 dml_get_pipe_attr_decl(refcyc_per_req_delivery_pre_c_in_us); 96 dml_get_pipe_attr_decl(refcyc_per_cursor_req_delivery_in_us); 97 dml_get_pipe_attr_decl(refcyc_per_cursor_req_delivery_pre_in_us); 98 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_nom_l_in_us); 99 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_nom_c_in_us); 100 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_vblank_l_in_us); 101 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_vblank_c_in_us); 102 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_l_in_us); 103 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_c_in_us); 104 105 dml_get_pipe_attr_decl(vstartup); 106 dml_get_pipe_attr_decl(vupdate_offset); 107 dml_get_pipe_attr_decl(vupdate_width); 108 dml_get_pipe_attr_decl(vready_offset); 109 dml_get_pipe_attr_decl(vready_at_or_after_vsync); 110 dml_get_pipe_attr_decl(min_dst_y_next_start); 111 112 double get_total_immediate_flip_bytes( 113 struct display_mode_lib *mode_lib, 114 const display_e2e_pipe_params_st *pipes, 115 unsigned int num_pipes); 116 double get_total_immediate_flip_bw( 117 struct display_mode_lib *mode_lib, 118 const display_e2e_pipe_params_st *pipes, 119 unsigned int num_pipes); 120 double get_total_prefetch_bw( 121 struct display_mode_lib *mode_lib, 122 const display_e2e_pipe_params_st *pipes, 123 unsigned int num_pipes); 124 unsigned int dml_get_voltage_level( 125 struct display_mode_lib *mode_lib, 126 const display_e2e_pipe_params_st *pipes, 127 unsigned int num_pipes); 128 129 void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct display_mode_lib *mode_lib); 130 131 bool Calculate256BBlockSizes( 132 enum source_format_class SourcePixelFormat, 133 enum dm_swizzle_mode SurfaceTiling, 134 unsigned int BytePerPixelY, 135 unsigned int BytePerPixelC, 136 unsigned int *BlockHeight256BytesY, 137 unsigned int *BlockHeight256BytesC, 138 unsigned int *BlockWidth256BytesY, 139 unsigned int *BlockWidth256BytesC); 140 141 struct vba_vars_st { 142 ip_params_st ip; 143 soc_bounding_box_st soc; 144 145 int maxMpcComb; 146 bool UseMaximumVStartup; 147 148 double WritebackDISPCLK; 149 double DPPCLKUsingSingleDPPLuma; 150 double DPPCLKUsingSingleDPPChroma; 151 double DISPCLKWithRamping; 152 double DISPCLKWithoutRamping; 153 double GlobalDPPCLK; 154 double DISPCLKWithRampingRoundedToDFSGranularity; 155 double DISPCLKWithoutRampingRoundedToDFSGranularity; 156 double MaxDispclkRoundedToDFSGranularity; 157 bool DCCEnabledAnyPlane; 158 double ReturnBandwidthToDCN; 159 unsigned int TotalActiveDPP; 160 unsigned int TotalDCCActiveDPP; 161 double UrgentRoundTripAndOutOfOrderLatency; 162 double StutterPeriod; 163 double FrameTimeForMinFullDETBufferingTime; 164 double AverageReadBandwidth; 165 double TotalRowReadBandwidth; 166 double PartOfBurstThatFitsInROB; 167 double StutterBurstTime; 168 unsigned int NextPrefetchMode; 169 double NextMaxVStartup; 170 double VBlankTime; 171 double SmallestVBlank; 172 double DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX]; 173 double EffectiveDETPlusLBLinesLuma; 174 double EffectiveDETPlusLBLinesChroma; 175 double UrgentLatencySupportUsLuma; 176 double UrgentLatencySupportUsChroma; 177 unsigned int DSCFormatFactor; 178 179 bool DummyPStateCheck; 180 bool DRAMClockChangeSupportsVActive; 181 bool PrefetchModeSupported; 182 bool PrefetchAndImmediateFlipSupported; 183 enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank; // Mode Support only 184 double XFCRemoteSurfaceFlipDelay; 185 double TInitXFill; 186 double TslvChk; 187 double SrcActiveDrainRate; 188 bool ImmediateFlipSupported; 189 enum mpc_combine_affinity WhenToDoMPCCombine; // Mode Support only 190 191 bool PrefetchERROR; 192 193 unsigned int VStartupLines; 194 unsigned int ActiveDPPs; 195 unsigned int LBLatencyHidingSourceLinesY; 196 unsigned int LBLatencyHidingSourceLinesC; 197 double ActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX]; 198 double MinActiveDRAMClockChangeMargin; 199 double InitFillLevel; 200 double FinalFillMargin; 201 double FinalFillLevel; 202 double RemainingFillLevel; 203 double TFinalxFill; 204 205 // 206 // SOC Bounding Box Parameters 207 // 208 double SRExitTime; 209 double SREnterPlusExitTime; 210 double UrgentLatencyPixelDataOnly; 211 double UrgentLatencyPixelMixedWithVMData; 212 double UrgentLatencyVMDataOnly; 213 double UrgentLatency; // max of the above three 214 double WritebackLatency; 215 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly; // Mode Support 216 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData; // Mode Support 217 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly; // Mode Support 218 double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation; // Mode Support 219 double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation; // Mode Support 220 double NumberOfChannels; 221 double DRAMChannelWidth; 222 double FabricDatapathToDCNDataReturn; 223 double ReturnBusWidth; 224 double Downspreading; 225 double DISPCLKDPPCLKDSCCLKDownSpreading; 226 double DISPCLKDPPCLKVCOSpeed; 227 double RoundTripPingLatencyCycles; 228 double UrgentOutOfOrderReturnPerChannel; 229 double UrgentOutOfOrderReturnPerChannelPixelDataOnly; 230 double UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData; 231 double UrgentOutOfOrderReturnPerChannelVMDataOnly; 232 unsigned int VMMPageSize; 233 double DRAMClockChangeLatency; 234 double XFCBusTransportTime; 235 bool UseUrgentBurstBandwidth; 236 double XFCXBUFLatencyTolerance; 237 238 // 239 // IP Parameters 240 // 241 unsigned int ROBBufferSizeInKByte; 242 unsigned int DETBufferSizeInKByte[DC__NUM_DPP__MAX]; 243 double DETBufferSizeInTime; 244 unsigned int DPPOutputBufferPixels; 245 unsigned int OPPOutputBufferLines; 246 unsigned int PixelChunkSizeInKByte; 247 double ReturnBW; 248 bool GPUVMEnable; 249 bool HostVMEnable; 250 unsigned int GPUVMMaxPageTableLevels; 251 unsigned int HostVMMaxPageTableLevels; 252 unsigned int HostVMCachedPageTableLevels; 253 unsigned int OverrideGPUVMPageTableLevels; 254 unsigned int OverrideHostVMPageTableLevels; 255 unsigned int MetaChunkSize; 256 unsigned int MinMetaChunkSizeBytes; 257 unsigned int WritebackChunkSize; 258 bool ODMCapability; 259 unsigned int NumberOfDSC; 260 unsigned int LineBufferSize; 261 unsigned int MaxLineBufferLines; 262 unsigned int WritebackInterfaceLumaBufferSize; 263 unsigned int WritebackInterfaceChromaBufferSize; 264 unsigned int WritebackChromaLineBufferWidth; 265 enum writeback_config WritebackConfiguration; 266 double MaxDCHUBToPSCLThroughput; 267 double MaxPSCLToLBThroughput; 268 unsigned int PTEBufferSizeInRequestsLuma; 269 unsigned int PTEBufferSizeInRequestsChroma; 270 double DISPCLKRampingMargin; 271 unsigned int MaxInterDCNTileRepeaters; 272 bool XFCSupported; 273 double XFCSlvChunkSize; 274 double XFCFillBWOverhead; 275 double XFCFillConstant; 276 double XFCTSlvVupdateOffset; 277 double XFCTSlvVupdateWidth; 278 double XFCTSlvVreadyOffset; 279 double DPPCLKDelaySubtotal; 280 double DPPCLKDelaySCL; 281 double DPPCLKDelaySCLLBOnly; 282 double DPPCLKDelayCNVCFormater; 283 double DPPCLKDelayCNVCCursor; 284 double DISPCLKDelaySubtotal; 285 bool ProgressiveToInterlaceUnitInOPP; 286 // Pipe/Plane Parameters 287 int VoltageLevel; 288 double FabricClock; 289 double DRAMSpeed; 290 double DISPCLK; 291 double SOCCLK; 292 double DCFCLK; 293 294 unsigned int NumberOfActivePlanes; 295 unsigned int NumberOfDSCSlices[DC__NUM_DPP__MAX]; 296 unsigned int ViewportWidth[DC__NUM_DPP__MAX]; 297 unsigned int ViewportHeight[DC__NUM_DPP__MAX]; 298 unsigned int ViewportYStartY[DC__NUM_DPP__MAX]; 299 unsigned int ViewportYStartC[DC__NUM_DPP__MAX]; 300 unsigned int PitchY[DC__NUM_DPP__MAX]; 301 unsigned int PitchC[DC__NUM_DPP__MAX]; 302 double HRatio[DC__NUM_DPP__MAX]; 303 double VRatio[DC__NUM_DPP__MAX]; 304 unsigned int htaps[DC__NUM_DPP__MAX]; 305 unsigned int vtaps[DC__NUM_DPP__MAX]; 306 unsigned int HTAPsChroma[DC__NUM_DPP__MAX]; 307 unsigned int VTAPsChroma[DC__NUM_DPP__MAX]; 308 unsigned int HTotal[DC__NUM_DPP__MAX]; 309 unsigned int VTotal[DC__NUM_DPP__MAX]; 310 unsigned int VTotal_Max[DC__NUM_DPP__MAX]; 311 unsigned int VTotal_Min[DC__NUM_DPP__MAX]; 312 int DPPPerPlane[DC__NUM_DPP__MAX]; 313 double PixelClock[DC__NUM_DPP__MAX]; 314 double PixelClockBackEnd[DC__NUM_DPP__MAX]; 315 bool DCCEnable[DC__NUM_DPP__MAX]; 316 bool FECEnable[DC__NUM_DPP__MAX]; 317 unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX]; 318 unsigned int DCCMetaPitchC[DC__NUM_DPP__MAX]; 319 enum scan_direction_class SourceScan[DC__NUM_DPP__MAX]; 320 enum source_format_class SourcePixelFormat[DC__NUM_DPP__MAX]; 321 bool WritebackEnable[DC__NUM_DPP__MAX]; 322 unsigned int ActiveWritebacksPerPlane[DC__NUM_DPP__MAX]; 323 double WritebackDestinationWidth[DC__NUM_DPP__MAX]; 324 double WritebackDestinationHeight[DC__NUM_DPP__MAX]; 325 double WritebackSourceHeight[DC__NUM_DPP__MAX]; 326 enum source_format_class WritebackPixelFormat[DC__NUM_DPP__MAX]; 327 unsigned int WritebackLumaHTaps[DC__NUM_DPP__MAX]; 328 unsigned int WritebackLumaVTaps[DC__NUM_DPP__MAX]; 329 unsigned int WritebackChromaHTaps[DC__NUM_DPP__MAX]; 330 unsigned int WritebackChromaVTaps[DC__NUM_DPP__MAX]; 331 double WritebackHRatio[DC__NUM_DPP__MAX]; 332 double WritebackVRatio[DC__NUM_DPP__MAX]; 333 unsigned int HActive[DC__NUM_DPP__MAX]; 334 unsigned int VActive[DC__NUM_DPP__MAX]; 335 bool Interlace[DC__NUM_DPP__MAX]; 336 enum dm_swizzle_mode SurfaceTiling[DC__NUM_DPP__MAX]; 337 unsigned int ScalerRecoutWidth[DC__NUM_DPP__MAX]; 338 bool DynamicMetadataEnable[DC__NUM_DPP__MAX]; 339 int DynamicMetadataLinesBeforeActiveRequired[DC__NUM_DPP__MAX]; 340 unsigned int DynamicMetadataTransmittedBytes[DC__NUM_DPP__MAX]; 341 double DCCRate[DC__NUM_DPP__MAX]; 342 double AverageDCCCompressionRate; 343 enum odm_combine_mode ODMCombineEnabled[DC__NUM_DPP__MAX]; 344 double OutputBpp[DC__NUM_DPP__MAX]; 345 bool DSCEnabled[DC__NUM_DPP__MAX]; 346 unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX]; 347 enum output_format_class OutputFormat[DC__NUM_DPP__MAX]; 348 enum output_encoder_class Output[DC__NUM_DPP__MAX]; 349 bool skip_dio_check[DC__NUM_DPP__MAX]; 350 unsigned int BlendingAndTiming[DC__NUM_DPP__MAX]; 351 bool SynchronizedVBlank; 352 unsigned int NumberOfCursors[DC__NUM_DPP__MAX]; 353 unsigned int CursorWidth[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX]; 354 unsigned int CursorBPP[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX]; 355 bool XFCEnabled[DC__NUM_DPP__MAX]; 356 bool ScalerEnabled[DC__NUM_DPP__MAX]; 357 358 // Intermediates/Informational 359 bool ImmediateFlipSupport; 360 unsigned int DETBufferSizeY[DC__NUM_DPP__MAX]; 361 unsigned int DETBufferSizeC[DC__NUM_DPP__MAX]; 362 unsigned int SwathHeightY[DC__NUM_DPP__MAX]; 363 unsigned int SwathHeightC[DC__NUM_DPP__MAX]; 364 unsigned int LBBitPerPixel[DC__NUM_DPP__MAX]; 365 double LastPixelOfLineExtraWatermark; 366 double TotalDataReadBandwidth; 367 unsigned int TotalActiveWriteback; 368 unsigned int EffectiveLBLatencyHidingSourceLinesLuma; 369 unsigned int EffectiveLBLatencyHidingSourceLinesChroma; 370 double BandwidthAvailableForImmediateFlip; 371 unsigned int PrefetchMode[DC__VOLTAGE_STATES][2]; 372 unsigned int PrefetchModePerState[DC__VOLTAGE_STATES][2]; 373 unsigned int MinPrefetchMode; 374 unsigned int MaxPrefetchMode; 375 bool AnyLinesForVMOrRowTooLarge; 376 double MaxVStartup; 377 bool IgnoreViewportPositioning; 378 bool ErrorResult[DC__NUM_DPP__MAX]; 379 // 380 // Calculated dml_ml->vba.Outputs 381 // 382 double DCFCLKDeepSleep; 383 double UrgentWatermark; 384 double UrgentExtraLatency; 385 double WritebackUrgentWatermark; 386 double StutterExitWatermark; 387 double StutterEnterPlusExitWatermark; 388 double DRAMClockChangeWatermark; 389 double WritebackDRAMClockChangeWatermark; 390 double StutterEfficiency; 391 double StutterEfficiencyNotIncludingVBlank; 392 double NonUrgentLatencyTolerance; 393 double MinActiveDRAMClockChangeLatencySupported; 394 395 // These are the clocks calcuated by the library but they are not actually 396 // used explicitly. They are fetched by tests and then possibly used. The 397 // ultimate values to use are the ones specified by the parameters to DML 398 double DISPCLK_calculated; 399 double DPPCLK_calculated[DC__NUM_DPP__MAX]; 400 401 unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX]; 402 double VUpdateWidthPix[DC__NUM_DPP__MAX]; 403 double VReadyOffsetPix[DC__NUM_DPP__MAX]; 404 405 unsigned int TotImmediateFlipBytes; 406 double TCalc; 407 408 display_e2e_pipe_params_st cache_pipes[DC__NUM_DPP__MAX]; 409 unsigned int cache_num_pipes; 410 unsigned int pipe_plane[DC__NUM_DPP__MAX]; 411 412 /* vba mode support */ 413 /*inputs*/ 414 bool SupportGFX7CompatibleTilingIn32bppAnd64bpp; 415 double MaxHSCLRatio; 416 double MaxVSCLRatio; 417 unsigned int MaxNumWriteback; 418 bool WritebackLumaAndChromaScalingSupported; 419 bool Cursor64BppSupport; 420 double DCFCLKPerState[DC__VOLTAGE_STATES]; 421 double DCFCLKState[DC__VOLTAGE_STATES][2]; 422 double FabricClockPerState[DC__VOLTAGE_STATES]; 423 double SOCCLKPerState[DC__VOLTAGE_STATES]; 424 double PHYCLKPerState[DC__VOLTAGE_STATES]; 425 double DTBCLKPerState[DC__VOLTAGE_STATES]; 426 double MaxDppclk[DC__VOLTAGE_STATES]; 427 double MaxDSCCLK[DC__VOLTAGE_STATES]; 428 double DRAMSpeedPerState[DC__VOLTAGE_STATES]; 429 double MaxDispclk[DC__VOLTAGE_STATES]; 430 int VoltageOverrideLevel; 431 432 /*outputs*/ 433 bool ScaleRatioAndTapsSupport; 434 bool SourceFormatPixelAndScanSupport; 435 double TotalBandwidthConsumedGBytePerSecond; 436 bool DCCEnabledInAnyPlane; 437 bool WritebackLatencySupport; 438 bool WritebackModeSupport; 439 bool Writeback10bpc420Supported; 440 bool BandwidthSupport[DC__VOLTAGE_STATES]; 441 unsigned int TotalNumberOfActiveWriteback; 442 double CriticalPoint; 443 double ReturnBWToDCNPerState; 444 bool IsErrorResult[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 445 bool prefetch_vm_bw_valid; 446 bool prefetch_row_bw_valid; 447 bool NumberOfOTGSupport; 448 bool NonsupportedDSCInputBPC; 449 bool WritebackScaleRatioAndTapsSupport; 450 bool CursorSupport; 451 bool PitchSupport; 452 enum dm_validation_status ValidationStatus[DC__VOLTAGE_STATES]; 453 454 double WritebackLineBufferLumaBufferSize; 455 double WritebackLineBufferChromaBufferSize; 456 double WritebackMinHSCLRatio; 457 double WritebackMinVSCLRatio; 458 double WritebackMaxHSCLRatio; 459 double WritebackMaxVSCLRatio; 460 double WritebackMaxHSCLTaps; 461 double WritebackMaxVSCLTaps; 462 unsigned int MaxNumDPP; 463 unsigned int MaxNumOTG; 464 double CursorBufferSize; 465 double CursorChunkSize; 466 unsigned int Mode; 467 double OutputLinkDPLanes[DC__NUM_DPP__MAX]; 468 double ForcedOutputLinkBPP[DC__NUM_DPP__MAX]; // Mode Support only 469 double ImmediateFlipBW[DC__NUM_DPP__MAX]; 470 double MaxMaxVStartup[DC__VOLTAGE_STATES][2]; 471 472 double WritebackLumaVExtra; 473 double WritebackChromaVExtra; 474 double WritebackRequiredDISPCLK; 475 double MaximumSwathWidthSupport; 476 double MaximumSwathWidthInDETBuffer; 477 double MaximumSwathWidthInLineBuffer; 478 double MaxDispclkRoundedDownToDFSGranularity; 479 double MaxDppclkRoundedDownToDFSGranularity; 480 double PlaneRequiredDISPCLKWithoutODMCombine; 481 double PlaneRequiredDISPCLKWithODMCombine; 482 double PlaneRequiredDISPCLK; 483 double TotalNumberOfActiveOTG; 484 double FECOverhead; 485 double EffectiveFECOverhead; 486 double Outbpp; 487 unsigned int OutbppDSC; 488 double TotalDSCUnitsRequired; 489 double bpp; 490 unsigned int slices; 491 double SwathWidthGranularityY; 492 double RoundedUpMaxSwathSizeBytesY; 493 double SwathWidthGranularityC; 494 double RoundedUpMaxSwathSizeBytesC; 495 double EffectiveDETLBLinesLuma; 496 double EffectiveDETLBLinesChroma; 497 double ProjectedDCFCLKDeepSleep[DC__VOLTAGE_STATES][2]; 498 double PDEAndMetaPTEBytesPerFrameY; 499 double PDEAndMetaPTEBytesPerFrameC; 500 unsigned int MetaRowBytesY; 501 unsigned int MetaRowBytesC; 502 unsigned int DPTEBytesPerRowC; 503 unsigned int DPTEBytesPerRowY; 504 double ExtraLatency; 505 double TimeCalc; 506 double TWait; 507 double MaximumReadBandwidthWithPrefetch; 508 double MaximumReadBandwidthWithoutPrefetch; 509 double total_dcn_read_bw_with_flip; 510 double total_dcn_read_bw_with_flip_no_urgent_burst; 511 double FractionOfUrgentBandwidth; 512 double FractionOfUrgentBandwidthImmediateFlip; // Mode Support debugging output 513 514 /* ms locals */ 515 double IdealSDPPortBandwidthPerState[DC__VOLTAGE_STATES][2]; 516 unsigned int NoOfDPP[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 517 int NoOfDPPThisState[DC__NUM_DPP__MAX]; 518 enum odm_combine_mode ODMCombineEnablePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 519 double SwathWidthYThisState[DC__NUM_DPP__MAX]; 520 unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 521 unsigned int SwathHeightYThisState[DC__NUM_DPP__MAX]; 522 unsigned int SwathHeightCThisState[DC__NUM_DPP__MAX]; 523 double VRatioPreY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 524 double VRatioPreC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 525 double RequiredPrefetchPixelDataBWLuma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 526 double RequiredPrefetchPixelDataBWChroma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 527 double RequiredDPPCLK[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 528 double RequiredDPPCLKThisState[DC__NUM_DPP__MAX]; 529 bool PTEBufferSizeNotExceededY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 530 bool PTEBufferSizeNotExceededC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 531 bool BandwidthWithoutPrefetchSupported[DC__VOLTAGE_STATES][2]; 532 bool PrefetchSupported[DC__VOLTAGE_STATES][2]; 533 bool VRatioInPrefetchSupported[DC__VOLTAGE_STATES][2]; 534 double RequiredDISPCLK[DC__VOLTAGE_STATES][2]; 535 bool DISPCLK_DPPCLK_Support[DC__VOLTAGE_STATES][2]; 536 bool TotalAvailablePipesSupport[DC__VOLTAGE_STATES][2]; 537 unsigned int TotalNumberOfActiveDPP[DC__VOLTAGE_STATES][2]; 538 unsigned int TotalNumberOfDCCActiveDPP[DC__VOLTAGE_STATES][2]; 539 bool ModeSupport[DC__VOLTAGE_STATES][2]; 540 double ReturnBWPerState[DC__VOLTAGE_STATES][2]; 541 bool DIOSupport[DC__VOLTAGE_STATES]; 542 bool NotEnoughDSCUnits[DC__VOLTAGE_STATES]; 543 bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES]; 544 bool DTBCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES]; 545 double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES]; 546 bool ROBSupport[DC__VOLTAGE_STATES][2]; 547 bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES][2]; 548 bool TotalVerticalActiveBandwidthSupport[DC__VOLTAGE_STATES][2]; 549 double MaxTotalVerticalActiveAvailableBandwidth[DC__VOLTAGE_STATES][2]; 550 double PrefetchBW[DC__NUM_DPP__MAX]; 551 double PDEAndMetaPTEBytesPerFrame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 552 double MetaRowBytes[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 553 double DPTEBytesPerRow[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 554 double PrefetchLinesY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 555 double PrefetchLinesC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 556 unsigned int MaxNumSwY[DC__NUM_DPP__MAX]; 557 unsigned int MaxNumSwC[DC__NUM_DPP__MAX]; 558 double PrefillY[DC__NUM_DPP__MAX]; 559 double PrefillC[DC__NUM_DPP__MAX]; 560 double LineTimesForPrefetch[DC__NUM_DPP__MAX]; 561 double LinesForMetaPTE[DC__NUM_DPP__MAX]; 562 double LinesForMetaAndDPTERow[DC__NUM_DPP__MAX]; 563 double MinDPPCLKUsingSingleDPP[DC__NUM_DPP__MAX]; 564 double SwathWidthYSingleDPP[DC__NUM_DPP__MAX]; 565 double BytePerPixelInDETY[DC__NUM_DPP__MAX]; 566 double BytePerPixelInDETC[DC__NUM_DPP__MAX]; 567 bool RequiresDSC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 568 unsigned int NumberOfDSCSlice[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 569 double RequiresFEC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 570 double OutputBppPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 571 double DSCDelayPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 572 bool ViewportSizeSupport[DC__VOLTAGE_STATES][2]; 573 unsigned int Read256BlockHeightY[DC__NUM_DPP__MAX]; 574 unsigned int Read256BlockWidthY[DC__NUM_DPP__MAX]; 575 unsigned int Read256BlockHeightC[DC__NUM_DPP__MAX]; 576 unsigned int Read256BlockWidthC[DC__NUM_DPP__MAX]; 577 double MaxSwathHeightY[DC__NUM_DPP__MAX]; 578 double MaxSwathHeightC[DC__NUM_DPP__MAX]; 579 double MinSwathHeightY[DC__NUM_DPP__MAX]; 580 double MinSwathHeightC[DC__NUM_DPP__MAX]; 581 double ReadBandwidthLuma[DC__NUM_DPP__MAX]; 582 double ReadBandwidthChroma[DC__NUM_DPP__MAX]; 583 double ReadBandwidth[DC__NUM_DPP__MAX]; 584 double WriteBandwidth[DC__NUM_DPP__MAX]; 585 double PSCL_FACTOR[DC__NUM_DPP__MAX]; 586 double PSCL_FACTOR_CHROMA[DC__NUM_DPP__MAX]; 587 double MaximumVStartup[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 588 unsigned int MacroTileWidthY[DC__NUM_DPP__MAX]; 589 unsigned int MacroTileWidthC[DC__NUM_DPP__MAX]; 590 double AlignedDCCMetaPitch[DC__NUM_DPP__MAX]; 591 double AlignedYPitch[DC__NUM_DPP__MAX]; 592 double AlignedCPitch[DC__NUM_DPP__MAX]; 593 double MaximumSwathWidth[DC__NUM_DPP__MAX]; 594 double cursor_bw[DC__NUM_DPP__MAX]; 595 double cursor_bw_pre[DC__NUM_DPP__MAX]; 596 double Tno_bw[DC__NUM_DPP__MAX]; 597 double prefetch_vmrow_bw[DC__NUM_DPP__MAX]; 598 double DestinationLinesToRequestVMInImmediateFlip[DC__NUM_DPP__MAX]; 599 double DestinationLinesToRequestRowInImmediateFlip[DC__NUM_DPP__MAX]; 600 double final_flip_bw[DC__NUM_DPP__MAX]; 601 bool ImmediateFlipSupportedForState[DC__VOLTAGE_STATES][2]; 602 double WritebackDelay[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 603 unsigned int vm_group_bytes[DC__NUM_DPP__MAX]; 604 unsigned int dpte_group_bytes[DC__NUM_DPP__MAX]; 605 unsigned int dpte_row_height[DC__NUM_DPP__MAX]; 606 unsigned int meta_req_height[DC__NUM_DPP__MAX]; 607 unsigned int meta_req_width[DC__NUM_DPP__MAX]; 608 unsigned int meta_row_height[DC__NUM_DPP__MAX]; 609 unsigned int meta_row_width[DC__NUM_DPP__MAX]; 610 unsigned int dpte_row_height_chroma[DC__NUM_DPP__MAX]; 611 unsigned int meta_req_height_chroma[DC__NUM_DPP__MAX]; 612 unsigned int meta_req_width_chroma[DC__NUM_DPP__MAX]; 613 unsigned int meta_row_height_chroma[DC__NUM_DPP__MAX]; 614 unsigned int meta_row_width_chroma[DC__NUM_DPP__MAX]; 615 bool ImmediateFlipSupportedForPipe[DC__NUM_DPP__MAX]; 616 double meta_row_bw[DC__NUM_DPP__MAX]; 617 double dpte_row_bw[DC__NUM_DPP__MAX]; 618 double DisplayPipeLineDeliveryTimeLuma[DC__NUM_DPP__MAX]; // WM 619 double DisplayPipeLineDeliveryTimeChroma[DC__NUM_DPP__MAX]; // WM 620 double DisplayPipeRequestDeliveryTimeLuma[DC__NUM_DPP__MAX]; 621 double DisplayPipeRequestDeliveryTimeChroma[DC__NUM_DPP__MAX]; 622 enum clock_change_support DRAMClockChangeSupport[DC__VOLTAGE_STATES][2]; 623 double UrgentBurstFactorCursor[DC__NUM_DPP__MAX]; 624 double UrgentBurstFactorCursorPre[DC__NUM_DPP__MAX]; 625 double UrgentBurstFactorLuma[DC__NUM_DPP__MAX]; 626 double UrgentBurstFactorLumaPre[DC__NUM_DPP__MAX]; 627 double UrgentBurstFactorChroma[DC__NUM_DPP__MAX]; 628 double UrgentBurstFactorChromaPre[DC__NUM_DPP__MAX]; 629 630 631 bool MPCCombine[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 632 double SwathWidthCSingleDPP[DC__NUM_DPP__MAX]; 633 double MaximumSwathWidthInLineBufferLuma; 634 double MaximumSwathWidthInLineBufferChroma; 635 double MaximumSwathWidthLuma[DC__NUM_DPP__MAX]; 636 double MaximumSwathWidthChroma[DC__NUM_DPP__MAX]; 637 enum odm_combine_mode odm_combine_dummy[DC__NUM_DPP__MAX]; 638 double dummy1[DC__NUM_DPP__MAX]; 639 double dummy2[DC__NUM_DPP__MAX]; 640 unsigned int dummy3[DC__NUM_DPP__MAX]; 641 unsigned int dummy4[DC__NUM_DPP__MAX]; 642 double dummy5; 643 double dummy6; 644 double dummy7[DC__NUM_DPP__MAX]; 645 double dummy8[DC__NUM_DPP__MAX]; 646 double dummy13[DC__NUM_DPP__MAX]; 647 unsigned int dummyinteger1ms[DC__NUM_DPP__MAX]; 648 double dummyinteger2ms[DC__NUM_DPP__MAX]; 649 unsigned int dummyinteger3[DC__NUM_DPP__MAX]; 650 unsigned int dummyinteger4[DC__NUM_DPP__MAX]; 651 unsigned int dummyinteger5; 652 unsigned int dummyinteger6; 653 unsigned int dummyinteger7; 654 unsigned int dummyinteger8; 655 unsigned int dummyinteger9; 656 unsigned int dummyinteger10; 657 unsigned int dummyinteger11; 658 unsigned int dummyinteger12; 659 unsigned int dummyinteger30; 660 unsigned int dummyinteger31; 661 unsigned int dummyinteger32; 662 unsigned int dummyintegerarr1[DC__NUM_DPP__MAX]; 663 unsigned int dummyintegerarr2[DC__NUM_DPP__MAX]; 664 unsigned int dummyintegerarr3[DC__NUM_DPP__MAX]; 665 unsigned int dummyintegerarr4[DC__NUM_DPP__MAX]; 666 bool dummysinglestring; 667 bool SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX]; 668 double PlaneRequiredDISPCLKWithODMCombine2To1; 669 double PlaneRequiredDISPCLKWithODMCombine4To1; 670 unsigned int TotalNumberOfSingleDPPPlanes[DC__VOLTAGE_STATES][2]; 671 bool LinkDSCEnable; 672 bool ODMCombine4To1SupportCheckOK[DC__VOLTAGE_STATES]; 673 enum odm_combine_mode ODMCombineEnableThisState[DC__NUM_DPP__MAX]; 674 double SwathWidthCThisState[DC__NUM_DPP__MAX]; 675 bool ViewportSizeSupportPerPlane[DC__NUM_DPP__MAX]; 676 double AlignedDCCMetaPitchY[DC__NUM_DPP__MAX]; 677 double AlignedDCCMetaPitchC[DC__NUM_DPP__MAX]; 678 679 unsigned int NotEnoughUrgentLatencyHiding[DC__VOLTAGE_STATES][2]; 680 unsigned int NotEnoughUrgentLatencyHidingPre; 681 int PTEBufferSizeInRequestsForLuma; 682 int PTEBufferSizeInRequestsForChroma; 683 684 // Missing from VBA 685 int dpte_group_bytes_chroma; 686 unsigned int vm_group_bytes_chroma; 687 double dst_x_after_scaler; 688 double dst_y_after_scaler; 689 unsigned int VStartupRequiredWhenNotEnoughTimeForDynamicMetadata; 690 691 /* perf locals*/ 692 double PrefetchBandwidth[DC__NUM_DPP__MAX]; 693 double VInitPreFillY[DC__NUM_DPP__MAX]; 694 double VInitPreFillC[DC__NUM_DPP__MAX]; 695 unsigned int MaxNumSwathY[DC__NUM_DPP__MAX]; 696 unsigned int MaxNumSwathC[DC__NUM_DPP__MAX]; 697 unsigned int VStartup[DC__NUM_DPP__MAX]; 698 double DSTYAfterScaler[DC__NUM_DPP__MAX]; 699 double DSTXAfterScaler[DC__NUM_DPP__MAX]; 700 bool AllowDRAMClockChangeDuringVBlank[DC__NUM_DPP__MAX]; 701 bool AllowDRAMSelfRefreshDuringVBlank[DC__NUM_DPP__MAX]; 702 double VRatioPrefetchY[DC__NUM_DPP__MAX]; 703 double VRatioPrefetchC[DC__NUM_DPP__MAX]; 704 double DestinationLinesForPrefetch[DC__NUM_DPP__MAX]; 705 double DestinationLinesToRequestVMInVBlank[DC__NUM_DPP__MAX]; 706 double DestinationLinesToRequestRowInVBlank[DC__NUM_DPP__MAX]; 707 double MinTTUVBlank[DC__NUM_DPP__MAX]; 708 double BytePerPixelDETY[DC__NUM_DPP__MAX]; 709 double BytePerPixelDETC[DC__NUM_DPP__MAX]; 710 double SwathWidthY[DC__NUM_DPP__MAX]; 711 double SwathWidthSingleDPPY[DC__NUM_DPP__MAX]; 712 double CursorRequestDeliveryTime[DC__NUM_DPP__MAX]; 713 double CursorRequestDeliveryTimePrefetch[DC__NUM_DPP__MAX]; 714 double ReadBandwidthPlaneLuma[DC__NUM_DPP__MAX]; 715 double ReadBandwidthPlaneChroma[DC__NUM_DPP__MAX]; 716 double DisplayPipeLineDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX]; 717 double DisplayPipeLineDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX]; 718 double DisplayPipeRequestDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX]; 719 double DisplayPipeRequestDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX]; 720 double PixelPTEBytesPerRow[DC__NUM_DPP__MAX]; 721 double PDEAndMetaPTEBytesFrame[DC__NUM_DPP__MAX]; 722 double MetaRowByte[DC__NUM_DPP__MAX]; 723 double PrefetchSourceLinesY[DC__NUM_DPP__MAX]; 724 double RequiredPrefetchPixDataBWLuma[DC__NUM_DPP__MAX]; 725 double RequiredPrefetchPixDataBWChroma[DC__NUM_DPP__MAX]; 726 double PrefetchSourceLinesC[DC__NUM_DPP__MAX]; 727 double PSCL_THROUGHPUT_LUMA[DC__NUM_DPP__MAX]; 728 double PSCL_THROUGHPUT_CHROMA[DC__NUM_DPP__MAX]; 729 double DSCCLK_calculated[DC__NUM_DPP__MAX]; 730 unsigned int DSCDelay[DC__NUM_DPP__MAX]; 731 unsigned int MaxVStartupLines[DC__NUM_DPP__MAX]; 732 double DPPCLKUsingSingleDPP[DC__NUM_DPP__MAX]; 733 double DPPCLK[DC__NUM_DPP__MAX]; 734 unsigned int DCCYMaxUncompressedBlock[DC__NUM_DPP__MAX]; 735 unsigned int DCCYMaxCompressedBlock[DC__NUM_DPP__MAX]; 736 unsigned int DCCYIndependent64ByteBlock[DC__NUM_DPP__MAX]; 737 double MaximumDCCCompressionYSurface[DC__NUM_DPP__MAX]; 738 unsigned int BlockHeight256BytesY[DC__NUM_DPP__MAX]; 739 unsigned int BlockHeight256BytesC[DC__NUM_DPP__MAX]; 740 unsigned int BlockWidth256BytesY[DC__NUM_DPP__MAX]; 741 unsigned int BlockWidth256BytesC[DC__NUM_DPP__MAX]; 742 double XFCSlaveVUpdateOffset[DC__NUM_DPP__MAX]; 743 double XFCSlaveVupdateWidth[DC__NUM_DPP__MAX]; 744 double XFCSlaveVReadyOffset[DC__NUM_DPP__MAX]; 745 double XFCTransferDelay[DC__NUM_DPP__MAX]; 746 double XFCPrechargeDelay[DC__NUM_DPP__MAX]; 747 double XFCRemoteSurfaceFlipLatency[DC__NUM_DPP__MAX]; 748 double XFCPrefetchMargin[DC__NUM_DPP__MAX]; 749 unsigned int dpte_row_width_luma_ub[DC__NUM_DPP__MAX]; 750 unsigned int dpte_row_width_chroma_ub[DC__NUM_DPP__MAX]; 751 double FullDETBufferingTimeY[DC__NUM_DPP__MAX]; // WM 752 double FullDETBufferingTimeC[DC__NUM_DPP__MAX]; // WM 753 double DST_Y_PER_PTE_ROW_NOM_L[DC__NUM_DPP__MAX]; 754 double DST_Y_PER_PTE_ROW_NOM_C[DC__NUM_DPP__MAX]; 755 double DST_Y_PER_META_ROW_NOM_L[DC__NUM_DPP__MAX]; 756 double TimePerMetaChunkNominal[DC__NUM_DPP__MAX]; 757 double TimePerMetaChunkVBlank[DC__NUM_DPP__MAX]; 758 double TimePerMetaChunkFlip[DC__NUM_DPP__MAX]; 759 unsigned int swath_width_luma_ub[DC__NUM_DPP__MAX]; 760 unsigned int swath_width_chroma_ub[DC__NUM_DPP__MAX]; 761 unsigned int PixelPTEReqWidthY[DC__NUM_DPP__MAX]; 762 unsigned int PixelPTEReqHeightY[DC__NUM_DPP__MAX]; 763 unsigned int PTERequestSizeY[DC__NUM_DPP__MAX]; 764 unsigned int PixelPTEReqWidthC[DC__NUM_DPP__MAX]; 765 unsigned int PixelPTEReqHeightC[DC__NUM_DPP__MAX]; 766 unsigned int PTERequestSizeC[DC__NUM_DPP__MAX]; 767 double time_per_pte_group_nom_luma[DC__NUM_DPP__MAX]; 768 double time_per_pte_group_nom_chroma[DC__NUM_DPP__MAX]; 769 double time_per_pte_group_vblank_luma[DC__NUM_DPP__MAX]; 770 double time_per_pte_group_vblank_chroma[DC__NUM_DPP__MAX]; 771 double time_per_pte_group_flip_luma[DC__NUM_DPP__MAX]; 772 double time_per_pte_group_flip_chroma[DC__NUM_DPP__MAX]; 773 double TimePerVMGroupVBlank[DC__NUM_DPP__MAX]; 774 double TimePerVMGroupFlip[DC__NUM_DPP__MAX]; 775 double TimePerVMRequestVBlank[DC__NUM_DPP__MAX]; 776 double TimePerVMRequestFlip[DC__NUM_DPP__MAX]; 777 unsigned int dpde0_bytes_per_frame_ub_l[DC__NUM_DPP__MAX]; 778 unsigned int meta_pte_bytes_per_frame_ub_l[DC__NUM_DPP__MAX]; 779 unsigned int dpde0_bytes_per_frame_ub_c[DC__NUM_DPP__MAX]; 780 unsigned int meta_pte_bytes_per_frame_ub_c[DC__NUM_DPP__MAX]; 781 double LinesToFinishSwathTransferStutterCriticalPlane; 782 unsigned int BytePerPixelYCriticalPlane; 783 double SwathWidthYCriticalPlane; 784 double LinesInDETY[DC__NUM_DPP__MAX]; 785 double LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX]; 786 787 double SwathWidthSingleDPPC[DC__NUM_DPP__MAX]; 788 double SwathWidthC[DC__NUM_DPP__MAX]; 789 unsigned int BytePerPixelY[DC__NUM_DPP__MAX]; 790 unsigned int BytePerPixelC[DC__NUM_DPP__MAX]; 791 unsigned int dummyinteger1; 792 unsigned int dummyinteger2; 793 double FinalDRAMClockChangeLatency; 794 double Tdmdl_vm[DC__NUM_DPP__MAX]; 795 double Tdmdl[DC__NUM_DPP__MAX]; 796 double TSetup[DC__NUM_DPP__MAX]; 797 unsigned int ThisVStartup; 798 bool WritebackAllowDRAMClockChangeEndPosition[DC__NUM_DPP__MAX]; 799 double DST_Y_PER_META_ROW_NOM_C[DC__NUM_DPP__MAX]; 800 double TimePerChromaMetaChunkNominal[DC__NUM_DPP__MAX]; 801 double TimePerChromaMetaChunkVBlank[DC__NUM_DPP__MAX]; 802 double TimePerChromaMetaChunkFlip[DC__NUM_DPP__MAX]; 803 unsigned int DCCCMaxUncompressedBlock[DC__NUM_DPP__MAX]; 804 unsigned int DCCCMaxCompressedBlock[DC__NUM_DPP__MAX]; 805 unsigned int DCCCIndependent64ByteBlock[DC__NUM_DPP__MAX]; 806 double VStartupMargin; 807 bool NotEnoughTimeForDynamicMetadata[DC__NUM_DPP__MAX]; 808 809 /* Missing from VBA */ 810 unsigned int MaximumMaxVStartupLines; 811 double FabricAndDRAMBandwidth; 812 double LinesInDETLuma; 813 double LinesInDETChroma; 814 unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX]; 815 unsigned int LinesInDETC[DC__NUM_DPP__MAX]; 816 unsigned int LinesInDETCRoundedDownToSwath[DC__NUM_DPP__MAX]; 817 double UrgentLatencySupportUsPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 818 double UrgentLatencySupportUs[DC__NUM_DPP__MAX]; 819 double FabricAndDRAMBandwidthPerState[DC__VOLTAGE_STATES]; 820 bool UrgentLatencySupport[DC__VOLTAGE_STATES][2]; 821 unsigned int SwathWidthYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 822 unsigned int SwathHeightYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 823 double qual_row_bw[DC__NUM_DPP__MAX]; 824 double prefetch_row_bw[DC__NUM_DPP__MAX]; 825 double prefetch_vm_bw[DC__NUM_DPP__MAX]; 826 827 double PTEGroupSize; 828 unsigned int PDEProcessingBufIn64KBReqs; 829 830 double MaxTotalVActiveRDBandwidth; 831 bool DoUrgentLatencyAdjustment; 832 double UrgentLatencyAdjustmentFabricClockComponent; 833 double UrgentLatencyAdjustmentFabricClockReference; 834 double MinUrgentLatencySupportUs; 835 double MinFullDETBufferingTime; 836 double AverageReadBandwidthGBytePerSecond; 837 bool FirstMainPlane; 838 839 unsigned int ViewportWidthChroma[DC__NUM_DPP__MAX]; 840 unsigned int ViewportHeightChroma[DC__NUM_DPP__MAX]; 841 double HRatioChroma[DC__NUM_DPP__MAX]; 842 double VRatioChroma[DC__NUM_DPP__MAX]; 843 int WritebackSourceWidth[DC__NUM_DPP__MAX]; 844 845 bool ModeIsSupported; 846 bool ODMCombine4To1Supported; 847 848 unsigned int SurfaceWidthY[DC__NUM_DPP__MAX]; 849 unsigned int SurfaceWidthC[DC__NUM_DPP__MAX]; 850 unsigned int SurfaceHeightY[DC__NUM_DPP__MAX]; 851 unsigned int SurfaceHeightC[DC__NUM_DPP__MAX]; 852 unsigned int WritebackHTaps[DC__NUM_DPP__MAX]; 853 unsigned int WritebackVTaps[DC__NUM_DPP__MAX]; 854 bool DSCEnable[DC__NUM_DPP__MAX]; 855 856 double DRAMClockChangeLatencyOverride; 857 858 double GPUVMMinPageSize; 859 double HostVMMinPageSize; 860 861 bool MPCCombineEnable[DC__NUM_DPP__MAX]; 862 unsigned int HostVMMaxNonCachedPageTableLevels; 863 bool DynamicMetadataVMEnabled; 864 double WritebackInterfaceBufferSize; 865 double WritebackLineBufferSize; 866 867 double DCCRateLuma[DC__NUM_DPP__MAX]; 868 double DCCRateChroma[DC__NUM_DPP__MAX]; 869 870 double PHYCLKD18PerState[DC__VOLTAGE_STATES]; 871 872 bool WritebackSupportInterleaveAndUsingWholeBufferForASingleStream; 873 bool NumberOfHDMIFRLSupport; 874 unsigned int MaxNumHDMIFRLOutputs; 875 int AudioSampleRate[DC__NUM_DPP__MAX]; 876 int AudioSampleLayout[DC__NUM_DPP__MAX]; 877 878 int PercentMarginOverMinimumRequiredDCFCLK; 879 bool DynamicMetadataSupported[DC__VOLTAGE_STATES][2]; 880 enum immediate_flip_requirement ImmediateFlipRequirement[DC__NUM_DPP__MAX]; 881 unsigned int DETBufferSizeYThisState[DC__NUM_DPP__MAX]; 882 unsigned int DETBufferSizeCThisState[DC__NUM_DPP__MAX]; 883 bool NoUrgentLatencyHiding[DC__NUM_DPP__MAX]; 884 bool NoUrgentLatencyHidingPre[DC__NUM_DPP__MAX]; 885 int swath_width_luma_ub_this_state[DC__NUM_DPP__MAX]; 886 int swath_width_chroma_ub_this_state[DC__NUM_DPP__MAX]; 887 double UrgLatency[DC__VOLTAGE_STATES]; 888 double VActiveCursorBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 889 double VActivePixelBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 890 bool NoTimeForPrefetch[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 891 bool NoTimeForDynamicMetadata[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 892 double dpte_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 893 double meta_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 894 double DETBufferSizeYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 895 double DETBufferSizeCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 896 int swath_width_luma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 897 int swath_width_chroma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 898 bool NotUrgentLatencyHiding[DC__VOLTAGE_STATES][2]; 899 unsigned int SwathHeightYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 900 unsigned int SwathHeightCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 901 unsigned int SwathWidthYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 902 unsigned int SwathWidthCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 903 double TotalDPTERowBandwidth[DC__VOLTAGE_STATES][2]; 904 double TotalMetaRowBandwidth[DC__VOLTAGE_STATES][2]; 905 double TotalVActiveCursorBandwidth[DC__VOLTAGE_STATES][2]; 906 double TotalVActivePixelBandwidth[DC__VOLTAGE_STATES][2]; 907 double WritebackDelayTime[DC__NUM_DPP__MAX]; 908 unsigned int DCCYIndependentBlock[DC__NUM_DPP__MAX]; 909 unsigned int DCCCIndependentBlock[DC__NUM_DPP__MAX]; 910 unsigned int dummyinteger15; 911 unsigned int dummyinteger16; 912 unsigned int dummyinteger17; 913 unsigned int dummyinteger18; 914 unsigned int dummyinteger19; 915 unsigned int dummyinteger20; 916 unsigned int dummyinteger21; 917 unsigned int dummyinteger22; 918 unsigned int dummyinteger23; 919 unsigned int dummyinteger24; 920 unsigned int dummyinteger25; 921 unsigned int dummyinteger26; 922 unsigned int dummyinteger27; 923 unsigned int dummyinteger28; 924 unsigned int dummyinteger29; 925 bool dummystring[DC__NUM_DPP__MAX]; 926 double BPP; 927 enum odm_combine_policy ODMCombinePolicy; 928 bool UseMinimumRequiredDCFCLK; 929 bool ClampMinDCFCLK; 930 bool AllowDramClockChangeOneDisplayVactive; 931 932 double MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation; 933 double PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency; 934 double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData; 935 double PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly; 936 double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly; 937 double SRExitZ8Time; 938 double SREnterPlusExitZ8Time; 939 double Z8StutterExitWatermark; 940 double Z8StutterEnterPlusExitWatermark; 941 double Z8StutterEfficiencyNotIncludingVBlank; 942 double Z8StutterEfficiency; 943 double DCCFractionOfZeroSizeRequestsLuma[DC__NUM_DPP__MAX]; 944 double DCCFractionOfZeroSizeRequestsChroma[DC__NUM_DPP__MAX]; 945 double UrgBurstFactorCursor[DC__NUM_DPP__MAX]; 946 double UrgBurstFactorLuma[DC__NUM_DPP__MAX]; 947 double UrgBurstFactorChroma[DC__NUM_DPP__MAX]; 948 double UrgBurstFactorCursorPre[DC__NUM_DPP__MAX]; 949 double UrgBurstFactorLumaPre[DC__NUM_DPP__MAX]; 950 double UrgBurstFactorChromaPre[DC__NUM_DPP__MAX]; 951 bool NotUrgentLatencyHidingPre[DC__NUM_DPP__MAX]; 952 bool LinkCapacitySupport[DC__NUM_DPP__MAX]; 953 bool VREADY_AT_OR_AFTER_VSYNC[DC__NUM_DPP__MAX]; 954 unsigned int MIN_DST_Y_NEXT_START[DC__NUM_DPP__MAX]; 955 unsigned int VFrontPorch[DC__NUM_DPP__MAX]; 956 int ConfigReturnBufferSizeInKByte; 957 enum unbounded_requesting_policy UseUnboundedRequesting; 958 int CompressedBufferSegmentSizeInkByte; 959 int CompressedBufferSizeInkByte; 960 int MetaFIFOSizeInKEntries; 961 int ZeroSizeBufferEntries; 962 int COMPBUF_RESERVED_SPACE_64B; 963 int COMPBUF_RESERVED_SPACE_ZS; 964 bool UnboundedRequestEnabled; 965 bool DSC422NativeSupport; 966 bool NoEnoughUrgentLatencyHiding; 967 bool NoEnoughUrgentLatencyHidingPre; 968 int NumberOfStutterBurstsPerFrame; 969 int Z8NumberOfStutterBurstsPerFrame; 970 unsigned int MaximumDSCBitsPerComponent; 971 unsigned int NotEnoughUrgentLatencyHidingA[DC__VOLTAGE_STATES][2]; 972 }; 973 974 bool CalculateMinAndMaxPrefetchMode( 975 enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank, 976 unsigned int *MinPrefetchMode, 977 unsigned int *MaxPrefetchMode); 978 979 double CalculateWriteBackDISPCLK( 980 enum source_format_class WritebackPixelFormat, 981 double PixelClock, 982 double WritebackHRatio, 983 double WritebackVRatio, 984 unsigned int WritebackLumaHTaps, 985 unsigned int WritebackLumaVTaps, 986 unsigned int WritebackChromaHTaps, 987 unsigned int WritebackChromaVTaps, 988 double WritebackDestinationWidth, 989 unsigned int HTotal, 990 unsigned int WritebackChromaLineBufferWidth); 991 992 #endif /* _DML2_DISPLAY_MODE_VBA_H_ */ 993