1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */ 3 4 #ifndef __HALDMOUTSRC_H__ 5 #define __HALDMOUTSRC_H__ 6 7 /* Add for AP/ADSLpseudo DM structuer requirement. */ 8 /* We need to remove to other position??? */ 9 struct rtl8192cd_priv { 10 u8 temp; 11 }; 12 13 struct rtw_dig { 14 u8 Dig_Enable_Flag; 15 u8 Dig_Ext_Port_Stage; 16 17 int RssiLowThresh; 18 int RssiHighThresh; 19 20 u32 FALowThresh; 21 u32 FAHighThresh; 22 23 u8 CurSTAConnectState; 24 u8 PreSTAConnectState; 25 u8 CurMultiSTAConnectState; 26 27 u8 PreIGValue; 28 u8 CurIGValue; 29 u8 BackupIGValue; 30 31 s8 BackoffVal; 32 s8 BackoffVal_range_max; 33 s8 BackoffVal_range_min; 34 u8 rx_gain_range_max; 35 u8 rx_gain_range_min; 36 u8 Rssi_val_min; 37 38 u8 PreCCK_CCAThres; 39 u8 CurCCK_CCAThres; 40 u8 PreCCKPDState; 41 u8 CurCCKPDState; 42 43 u8 LargeFAHit; 44 u8 ForbiddenIGI; 45 u32 Recover_cnt; 46 47 u8 DIG_Dynamic_MIN_0; 48 u8 DIG_Dynamic_MIN_1; 49 bool bMediaConnect_0; 50 bool bMediaConnect_1; 51 52 u32 AntDiv_RSSI_max; 53 u32 RSSI_max; 54 }; 55 56 struct rtl_ps { 57 u8 pre_cca_state; 58 u8 cur_cca_state; 59 60 u8 pre_rf_state; 61 u8 cur_rf_state; 62 63 int rssi_val_min; 64 65 u8 initialize; 66 u32 reg_874; 67 u32 reg_c70; 68 u32 reg_85c; 69 u32 reg_a74; 70 71 }; 72 73 struct false_alarm_stats { 74 u32 Cnt_Parity_Fail; 75 u32 Cnt_Rate_Illegal; 76 u32 Cnt_Crc8_fail; 77 u32 Cnt_Mcs_fail; 78 u32 Cnt_Ofdm_fail; 79 u32 Cnt_Cck_fail; 80 u32 Cnt_all; 81 u32 Cnt_Fast_Fsync; 82 u32 Cnt_SB_Search_fail; 83 u32 Cnt_OFDM_CCA; 84 u32 Cnt_CCK_CCA; 85 u32 Cnt_CCA_all; 86 u32 Cnt_BW_USC; /* Gary */ 87 u32 Cnt_BW_LSC; /* Gary */ 88 }; 89 90 struct dyn_primary_cca { 91 u8 pri_cca_flag; 92 u8 intf_flag; 93 u8 intf_type; 94 u8 dup_rts_flag; 95 u8 monitor_flag; 96 }; 97 98 struct rx_hpc { 99 u8 RXHP_flag; 100 u8 PSD_func_trigger; 101 u8 PSD_bitmap_RXHP[80]; 102 u8 Pre_IGI; 103 u8 Cur_IGI; 104 u8 Pre_pw_th; 105 u8 Cur_pw_th; 106 bool First_time_enter; 107 bool RXHP_enable; 108 u8 TP_Mode; 109 struct timer_list PSDTimer; 110 }; 111 112 #define ODM_ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */ 113 114 struct sw_ant_switch { 115 u8 try_flag; 116 s32 PreRSSI; 117 u8 CurAntenna; 118 u8 PreAntenna; 119 u8 RSSI_Trying; 120 u8 TestMode; 121 u8 bTriggerAntennaSwitch; 122 u8 SelectAntennaMap; 123 u8 RSSI_target; 124 125 /* Before link Antenna Switch check */ 126 u8 SWAS_NoLink_State; 127 u32 SWAS_NoLink_BK_Reg860; 128 129 s32 RSSI_sum_A; 130 s32 RSSI_sum_B; 131 s32 RSSI_cnt_A; 132 s32 RSSI_cnt_B; 133 u64 lastTxOkCnt; 134 u64 lastRxOkCnt; 135 u64 TXByteCnt_A; 136 u64 TXByteCnt_B; 137 u64 RXByteCnt_A; 138 u64 RXByteCnt_B; 139 u8 TrafficLoad; 140 struct timer_list SwAntennaSwitchTimer; 141 u8 TxAnt[ODM_ASSOCIATE_ENTRY_NUM]; 142 u8 TargetSTA; 143 u8 RxIdleAnt; 144 }; 145 146 struct edca_turbo { 147 bool bCurrentTurboEDCA; 148 bool bIsCurRDLState; 149 u32 prv_traffic_idx; /* edca turbo */ 150 }; 151 152 struct odm_rate_adapt { 153 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */ 154 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */ 155 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ 156 u32 LastRATR; /* RATR Register Content */ 157 }; 158 159 #define IQK_MAC_REG_NUM 4 160 #define IQK_ADDA_REG_NUM 16 161 #define IQK_BB_REG_NUM 9 162 #define HP_THERMAL_NUM 8 163 164 #define AVG_THERMAL_NUM 8 165 #define IQK_Matrix_REG_NUM 8 166 167 struct odm_phy_dbg_info { 168 /* ODM Write,debug info */ 169 s8 RxSNRdB[MAX_PATH_NUM_92CS]; 170 u64 NumQryPhyStatus; 171 u64 NumQryPhyStatusCCK; 172 u64 NumQryPhyStatusOFDM; 173 /* Others */ 174 s32 RxEVM[MAX_PATH_NUM_92CS]; 175 }; 176 177 struct odm_per_pkt_info { 178 s8 Rate; 179 u8 StationID; 180 bool bPacketMatchBSSID; 181 bool bPacketToSelf; 182 bool bPacketBeacon; 183 }; 184 185 struct odm_mac_status_info { 186 u8 test; 187 }; 188 189 enum odm_ability { 190 /* BB Team */ 191 ODM_DIG = 0x00000001, 192 ODM_HIGH_POWER = 0x00000002, 193 ODM_CCK_CCA_TH = 0x00000004, 194 ODM_FA_STATISTICS = 0x00000008, 195 ODM_RAMASK = 0x00000010, 196 ODM_RSSI_MONITOR = 0x00000020, 197 ODM_SW_ANTDIV = 0x00000040, 198 ODM_HW_ANTDIV = 0x00000080, 199 ODM_BB_PWRSV = 0x00000100, 200 ODM_2TPATHDIV = 0x00000200, 201 ODM_1TPATHDIV = 0x00000400, 202 ODM_PSD2AFH = 0x00000800 203 }; 204 205 /* 2011/20/20 MH For MP driver RT_WLAN_STA = struct sta_info */ 206 /* Please declare below ODM relative info in your STA info structure. */ 207 208 struct odm_sta_info { 209 /* Driver Write */ 210 bool bUsed; /* record the sta status link or not? */ 211 u8 IOTPeer; /* Enum value. HT_IOT_PEER_E */ 212 213 /* ODM Write */ 214 /* 1 PHY_STATUS_INFO */ 215 u8 RSSI_Path[4]; /* */ 216 u8 RSSI_Ave; 217 u8 RXEVM[4]; 218 u8 RXSNR[4]; 219 }; 220 221 /* 2011/10/20 MH Define Common info enum for all team. */ 222 223 enum odm_common_info_def { 224 /* Fixed value: */ 225 226 /* HOOK BEFORE REG INIT----------- */ 227 ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */ 228 ODM_CMNINFO_MP_TEST_CHIP, 229 /* HOOK BEFORE REG INIT----------- */ 230 231 /* Dynamic value: */ 232 /* POINTER REFERENCE----------- */ 233 ODM_CMNINFO_TX_UNI, 234 ODM_CMNINFO_RX_UNI, 235 ODM_CMNINFO_WM_MODE, /* ODM_WIRELESS_MODE_E */ 236 ODM_CMNINFO_SEC_CHNL_OFFSET, /* ODM_SEC_CHNL_OFFSET_E */ 237 ODM_CMNINFO_SEC_MODE, /* ODM_SECURITY_E */ 238 ODM_CMNINFO_BW, /* ODM_BW_E */ 239 ODM_CMNINFO_CHNL, 240 241 ODM_CMNINFO_SCAN, 242 ODM_CMNINFO_POWER_SAVING, 243 ODM_CMNINFO_NET_CLOSED, 244 /* POINTER REFERENCE----------- */ 245 246 /* CALL BY VALUE------------- */ 247 ODM_CMNINFO_WIFI_DIRECT, 248 ODM_CMNINFO_WIFI_DISPLAY, 249 ODM_CMNINFO_LINK, 250 ODM_CMNINFO_RSSI_MIN, 251 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */ 252 /* CALL BY VALUE-------------*/ 253 }; 254 255 /* 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY */ 256 257 enum odm_ability_def { 258 /* BB ODM section BIT 0-15 */ 259 ODM_BB_DIG = BIT(0), 260 ODM_BB_RA_MASK = BIT(1), 261 ODM_BB_DYNAMIC_TXPWR = BIT(2), 262 ODM_BB_FA_CNT = BIT(3), 263 ODM_BB_RSSI_MONITOR = BIT(4), 264 ODM_BB_CCK_PD = BIT(5), 265 ODM_BB_ANT_DIV = BIT(6), 266 ODM_BB_PWR_SAVE = BIT(7), 267 ODM_BB_PWR_TRA = BIT(8), 268 ODM_BB_RATE_ADAPTIVE = BIT(9), 269 ODM_BB_PATH_DIV = BIT(10), 270 ODM_BB_PSD = BIT(11), 271 ODM_BB_RXHP = BIT(12), 272 273 /* MAC DM section BIT 16-23 */ 274 ODM_MAC_EDCA_TURBO = BIT(16), 275 ODM_MAC_EARLY_MODE = BIT(17), 276 277 /* RF ODM section BIT 24-31 */ 278 ODM_RF_TX_PWR_TRACK = BIT(24), 279 ODM_RF_RX_GAIN_TRACK = BIT(25), 280 ODM_RF_CALIBRATION = BIT(26), 281 }; 282 283 # define ODM_ITRF_USB 0x2 284 285 /* ODM_CMNINFO_OP_MODE */ 286 enum odm_operation_mode { 287 ODM_NO_LINK = BIT(0), 288 ODM_LINK = BIT(1), 289 ODM_SCAN = BIT(2), 290 ODM_POWERSAVE = BIT(3), 291 ODM_AP_MODE = BIT(4), 292 ODM_CLIENT_MODE = BIT(5), 293 ODM_AD_HOC = BIT(6), 294 ODM_WIFI_DIRECT = BIT(7), 295 ODM_WIFI_DISPLAY = BIT(8), 296 }; 297 298 /* ODM_CMNINFO_WM_MODE */ 299 enum odm_wireless_mode { 300 ODM_WM_UNKNOW = 0x0, 301 ODM_WM_B = BIT(0), 302 ODM_WM_G = BIT(1), 303 ODM_WM_N24G = BIT(3), 304 ODM_WM_AUTO = BIT(5), 305 }; 306 307 /* ODM_CMNINFO_BW */ 308 enum odm_bw { 309 ODM_BW20M = 0, 310 ODM_BW40M = 1, 311 }; 312 313 struct odm_ra_info { 314 u8 RateID; 315 u32 RateMask; 316 u32 RAUseRate; 317 u8 RateSGI; 318 u8 RssiStaRA; 319 u8 PreRssiStaRA; 320 u8 SGIEnable; 321 u8 DecisionRate; 322 u8 PreRate; 323 u8 HighestRate; 324 u8 LowestRate; 325 u32 NscUp; 326 u32 NscDown; 327 u16 RTY[5]; 328 u32 TOTAL; 329 u16 DROP; 330 u8 Active; 331 u16 RptTime; 332 u8 RAWaitingCounter; 333 u8 RAPendingCounter; 334 u8 PTActive; /* on or off */ 335 u8 PTTryState; /* 0 trying state, 1 for decision state */ 336 u8 PTStage; /* 0~6 */ 337 u8 PTStopCount; /* Stop PT counter */ 338 u8 PTPreRate; /* if rate change do PT */ 339 u8 PTPreRssi; /* if RSSI change 5% do PT */ 340 u8 PTModeSS; /* decide whitch rate should do PT */ 341 u8 RAstage; /* StageRA, decide how many times RA will be done 342 * between PT */ 343 u8 PTSmoothFactor; 344 }; 345 346 struct ijk_matrix_regs_set { 347 bool bIQKDone; 348 s32 Value[1][IQK_Matrix_REG_NUM]; 349 }; 350 351 struct odm_rf_cal { 352 /* for tx power tracking */ 353 u32 RegA24; /* for TempCCK */ 354 s32 RegE94; 355 s32 RegE9C; 356 s32 RegEB4; 357 s32 RegEBC; 358 359 u8 TXPowercount; 360 bool bTXPowerTrackingInit; 361 bool bTXPowerTracking; 362 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking 363 * as default */ 364 u8 TM_Trigger; 365 u8 InternalPA5G[2]; /* pathA / pathB */ 366 367 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, 368 * and 1 for RFIC1 */ 369 u8 ThermalValue; 370 u8 ThermalValue_LCK; 371 u8 ThermalValue_IQK; 372 u8 ThermalValue_DPK; 373 u8 ThermalValue_AVG[AVG_THERMAL_NUM]; 374 u8 ThermalValue_AVG_index; 375 u8 ThermalValue_RxGain; 376 u8 ThermalValue_Crystal; 377 u8 ThermalValue_DPKstore; 378 u8 ThermalValue_DPKtrack; 379 bool TxPowerTrackingInProgress; 380 bool bDPKenable; 381 382 bool bReloadtxpowerindex; 383 u8 bRfPiEnable; 384 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */ 385 386 u8 bCCKinCH14; 387 u8 CCK_index; 388 u8 OFDM_index[2]; 389 bool bDoneTxpower; 390 391 u8 ThermalValue_HP[HP_THERMAL_NUM]; 392 u8 ThermalValue_HP_index; 393 struct ijk_matrix_regs_set IQKMatrixRegSetting; 394 395 u8 Delta_IQK; 396 u8 Delta_LCK; 397 398 /* for IQK */ 399 u32 RegC04; 400 u32 Reg874; 401 u32 RegC08; 402 u32 RegB68; 403 u32 RegB6C; 404 u32 Reg870; 405 u32 Reg860; 406 u32 Reg864; 407 408 bool bIQKInitialized; 409 bool bAntennaDetected; 410 u32 ADDA_backup[IQK_ADDA_REG_NUM]; 411 u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; 412 u32 IQK_BB_backup_recover[9]; 413 u32 IQK_BB_backup[IQK_BB_REG_NUM]; 414 415 /* for APK */ 416 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */ 417 u8 bAPKdone; 418 u8 bAPKThermalMeterIgnore; 419 u8 bDPdone; 420 u8 bDPPathAOK; 421 u8 bDPPathBOK; 422 }; 423 424 /* ODM Dynamic common info value definition */ 425 426 struct fast_ant_train { 427 u8 Bssid[6]; 428 u8 antsel_rx_keep_0; 429 u8 antsel_rx_keep_1; 430 u8 antsel_rx_keep_2; 431 u32 antSumRSSI[7]; 432 u32 antRSSIcnt[7]; 433 u32 antAveRSSI[7]; 434 u8 FAT_State; 435 u32 TrainIdx; 436 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; 437 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; 438 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; 439 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 440 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 441 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 442 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 443 u8 RxIdleAnt; 444 bool bBecomeLinked; 445 }; 446 447 enum fat_state { 448 FAT_NORMAL_STATE = 0, 449 FAT_TRAINING_STATE = 1, 450 }; 451 452 enum ant_div_type { 453 NO_ANTDIV = 0xFF, 454 CG_TRX_HW_ANTDIV = 0x01, 455 CGCS_RX_HW_ANTDIV = 0x02, 456 FIXED_HW_ANTDIV = 0x03, 457 CG_TRX_SMART_ANTDIV = 0x04, 458 }; 459 460 /* Copy from SD4 defined structure. We use to support PHY DM integration. */ 461 struct odm_dm_struct { 462 /* Add for different team use temporarily */ 463 struct adapter *Adapter; /* For CE/NIC team */ 464 struct rtl8192cd_priv *priv; /* For AP/ADSL team */ 465 /* WHen you use above pointers, they must be initialized. */ 466 bool odm_ready; 467 468 struct rtl8192cd_priv *fake_priv; 469 470 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 471 bool bCckHighPower; 472 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */ 473 u8 ControlChannel; 474 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 475 476 /* 1 COMMON INFORMATION */ 477 /* Init Value */ 478 /* HOOK BEFORE REG INIT----------- */ 479 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/ �K�K = 1/2/3/�K */ 480 u32 SupportAbility; 481 482 u32 BK_SupportAbility; 483 u8 AntDivType; 484 /* HOOK BEFORE REG INIT----------- */ 485 486 /* Dynamic Value */ 487 /* POINTER REFERENCE----------- */ 488 489 u8 u8_temp; 490 bool bool_temp; 491 struct adapter *adapter_temp; 492 493 /* TX Unicast byte count */ 494 u64 *pNumTxBytesUnicast; 495 /* RX Unicast byte count */ 496 u64 *pNumRxBytesUnicast; 497 /* Wireless mode B/G/A/N = BIT(0)/BIT(1)/BIT(2)/BIT(3) */ 498 u8 *pWirelessMode; /* ODM_WIRELESS_MODE_E */ 499 /* Secondary channel offset don't_care/below/above = 0/1/2 */ 500 u8 *pSecChOffset; 501 /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */ 502 u8 *pSecurity; 503 /* BW info 20M/40M/80M = 0/1/2 */ 504 u8 *pBandWidth; 505 /* Central channel location Ch1/Ch2/.... */ 506 u8 *pChannel; /* central channel number */ 507 /* Common info for 92D DMSP */ 508 509 bool *pbGetValueFromOtherMac; 510 struct adapter **pBuddyAdapter; 511 bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */ 512 /* Common info for Status */ 513 bool *pbScanInProcess; 514 bool *pbPowerSaving; 515 /* CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */ 516 u8 *pOnePathCCA; 517 /* pMgntInfo->AntennaTest */ 518 u8 *pAntennaTest; 519 bool *pbNet_closed; 520 /* POINTER REFERENCE----------- */ 521 /* */ 522 /* CALL BY VALUE------------- */ 523 bool bWIFI_Direct; 524 bool bWIFI_Display; 525 bool bLinked; 526 u8 RSSI_Min; 527 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */ 528 bool bIsMPChip; 529 bool bOneEntryOnly; 530 /* Common info for BTDM */ 531 bool bBtDisabled; /* BT is disabled */ 532 bool bBtHsOperation; /* BT HS mode is under progress */ 533 u8 btHsDigVal; /* use BT rssi to decide the DIG value */ 534 bool bBtDisableEdcaTurbo;/* Under some condition, don't enable the 535 * EDCA Turbo */ 536 bool bBtBusy; /* BT is busy. */ 537 /* CALL BY VALUE------------- */ 538 539 /* 2 Define STA info. */ 540 /* _ODM_STA_INFO */ 541 /* For MP, we need to reduce one array pointer for default port.?? */ 542 struct sta_info *pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; 543 544 u16 CurrminRptTime; 545 struct odm_ra_info RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; /* Use MacID as 546 * array index. STA MacID=0, 547 * VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} */ 548 549 /* Latest packet phy info (ODM write) */ 550 struct odm_phy_dbg_info PhyDbgInfo; 551 552 /* Latest packet phy info (ODM write) */ 553 struct odm_mac_status_info *pMacInfo; 554 555 /* Different Team independt structure?? */ 556 557 /* ODM Structure */ 558 struct fast_ant_train DM_FatTable; 559 struct rtw_dig DM_DigTable; 560 struct rtl_ps DM_PSTable; 561 struct dyn_primary_cca DM_PriCCA; 562 struct rx_hpc DM_RXHP_Table; 563 struct false_alarm_stats FalseAlmCnt; 564 struct false_alarm_stats FlaseAlmCntBuddyAdapter; 565 struct sw_ant_switch DM_SWAT_Table; 566 bool RSSI_test; 567 568 struct edca_turbo DM_EDCA_Table; 569 u32 WMMEDCA_BE; 570 /* Copy from SD4 structure */ 571 /* */ 572 /* ================================================== */ 573 /* */ 574 575 bool *pbDriverStopped; 576 bool *pbDriverIsGoingToPnpSetPowerSleep; 577 bool *pinit_adpt_in_progress; 578 579 /* PSD */ 580 bool bUserAssignLevel; 581 struct timer_list PSDTimer; 582 u8 RSSI_BT; /* come from BT */ 583 bool bPSDinProcess; 584 bool bDMInitialGainEnable; 585 586 struct odm_rate_adapt RateAdaptive; 587 588 struct odm_rf_cal RFCalibrateInfo; 589 590 /* TX power tracking */ 591 u8 BbSwingIdxOfdm; 592 u8 BbSwingIdxOfdmCurrent; 593 u8 BbSwingIdxOfdmBase; 594 bool BbSwingFlagOfdm; 595 u8 BbSwingIdxCck; 596 u8 BbSwingIdxCckCurrent; 597 u8 BbSwingIdxCckBase; 598 bool BbSwingFlagCck; 599 /* ODM system resource. */ 600 601 /* ODM relative time. */ 602 struct timer_list PathDivSwitchTimer; 603 /* 2011.09.27 add for Path Diversity */ 604 struct timer_list CCKPathDiversityTimer; 605 struct timer_list FastAntTrainingTimer; 606 }; /* DM_Dynamic_Mechanism_Structure */ 607 608 enum odm_bb_config_type { 609 CONFIG_BB_PHY_REG, 610 CONFIG_BB_AGC_TAB, 611 CONFIG_BB_AGC_TAB_2G, 612 CONFIG_BB_PHY_REG_PG, 613 }; 614 615 #define DM_DIG_THRESH_HIGH 40 616 #define DM_DIG_THRESH_LOW 35 617 618 #define DM_false_ALARM_THRESH_LOW 400 619 #define DM_false_ALARM_THRESH_HIGH 1000 620 621 #define DM_DIG_MAX_NIC 0x4e 622 #define DM_DIG_MIN_NIC 0x1e /* 0x22/0x1c */ 623 624 #define DM_DIG_MAX_AP 0x32 625 626 /* vivi 92c&92d has different definition, 20110504 */ 627 /* this is for 92c */ 628 #define DM_DIG_FA_TH0 0x200/* 0x20 */ 629 #define DM_DIG_FA_TH1 0x300/* 0x100 */ 630 #define DM_DIG_FA_TH2 0x400/* 0x200 */ 631 632 #define DM_DIG_BACKOFF_MAX 12 633 #define DM_DIG_BACKOFF_MIN -4 634 #define DM_DIG_BACKOFF_DEFAULT 10 635 636 /* 3=========================================================== */ 637 /* 3 Rate Adaptive */ 638 /* 3=========================================================== */ 639 #define DM_RATR_STA_INIT 0 640 #define DM_RATR_STA_HIGH 1 641 #define DM_RATR_STA_MIDDLE 2 642 #define DM_RATR_STA_LOW 3 643 644 /* 3=========================================================== */ 645 /* 3 BB Power Save */ 646 /* 3=========================================================== */ 647 648 enum dm_1r_cca { 649 CCA_1R = 0, 650 CCA_2R = 1, 651 CCA_MAX = 2, 652 }; 653 654 enum dm_rf { 655 RF_Save = 0, 656 RF_Normal = 1, 657 RF_MAX = 2, 658 }; 659 660 /* 3=========================================================== */ 661 /* 3 Antenna Diversity */ 662 /* 3=========================================================== */ 663 enum dm_swas { 664 Antenna_A = 1, 665 Antenna_B = 2, 666 Antenna_MAX = 3, 667 }; 668 669 /* Extern Global Variables. */ 670 #define OFDM_TABLE_SIZE_92D 43 671 #define CCK_TABLE_SIZE 33 672 673 extern u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D]; 674 extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; 675 extern u8 CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]; 676 677 /* check Sta pointer valid or not */ 678 #define IS_STA_VALID(pSta) (pSta) 679 680 void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI); 681 void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres); 682 683 void ODM_SetAntenna(struct odm_dm_struct *pDM_Odm, u8 Antenna); 684 685 void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal); 686 687 void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm); 688 689 bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI, 690 bool bForceUpdate, u8 *pRATRState); 691 692 u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid, 693 u32 ra_mask, u8 rssi_level); 694 695 void ODM_DMInit(struct odm_dm_struct *pDM_Odm); 696 697 void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm); 698 699 void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm, 700 enum odm_common_info_def CmnInfo, u32 Value); 701 702 void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm, 703 enum odm_common_info_def CmnInfo, void *pValue); 704 705 void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value); 706 707 #endif 708